JPH0619726B2 - Information processing equipment - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly, to a debugging function of the information processing apparatus, and more particularly, a means for confirming a failure processing function when a machine error is detected.

[Prior art]

High-performance electronic computers require high reliability as well as high-speed computing capability. For this reason, computers have various fault handling functions. For example, (1) Machine error detection reporting function, (2) Machine error report failure information collection function, (3) Retryable retry function, (4) Fixed failure processor relief function, (5) Retry Not possible / retry failure There is a function to isolate the failed processor related to failure. The normal operation of these functions makes it possible to completely eliminate or minimize damage when a failure occurs in the computer system. These fault handling functions are complicated and are implemented by sharing the functions of computer hardware, firmware, and operating systems. Therefore, whether or not these fault handling functions operate correctly is an important issue regarding the reliability of the computer system.
Usually, in order to diagnose these fault handling functions, a method is adopted in which a pseudo machine error is generated inside the computer and it is checked whether the machine operates normally at that time.

[Problems to be solved by the invention]

Conventionally, in this type of information processing apparatus, a signal pin on the back panel of a computer is manually clamped to cause a pseudo machine error to occur asynchronously during program execution. In this way, since it is manually clamped, it takes time and effort, and mistakes are likely to occur.
There is a drawback in that it is not possible to automatically generate a pseudo fault.
Another drawback is that it causes a pseudo failure asynchronously during program execution, and thus has no reproducibility.

Due to these shortcomings, hardware / firmware /
It is also difficult to diagnose the fault handling function realized by the operating system, which is also a factor that makes it easier to see design mistakes. Also, due to the recent technological advances, the back panel pins themselves are connected by a cable, which makes it impossible to clamp the back panel pins like a conventional computer.

INDUSTRIAL APPLICABILITY The present invention facilitates programming and automation of occurrence of a pseudo fault by causing the occurrence of the pseudo fault at an arbitrary time specified in a program, and is realized by hardware, firmware, and operating system sharing functions. The present invention aims to provide an information processing device which can effectively confirm the normality of the failure processing function.

[Means for solving problems]

According to the present invention, in an information processing device for processing data, a control register for instructing the occurrence of a machine error by a program instruction, a counting means for counting a time interval, and a value can be set by a program instruction. A timer register that is counted by, a detection unit that detects that the content of the timer register has reached a predetermined value, and that the timer register has reached a predetermined value as the program instruction is executed. And a machine error control circuit for generating a machine error report when a machine error is instructed by the control register.

[Action]

According to the present invention, the pseudo failure mode is set by the program instruction, and when the timer register reaches a predetermined value after the data is set in the timer register by the program instruction, a pseudo machine error is generated to cause a failure. Check the normality of processing functions.

[Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.

In FIG. 1 showing an embodiment of the present invention, an information processing apparatus decodes and executes a main memory 1 in which a program to be processed is stored and a program instruction read from the main memory 1. An arithmetic control circuit 2 (which also generates an instruction address to be accessed next) is provided, and a control register 3 for controlling the occurrence of a machine error by a program instruction and a machine error occurrence control circuit 4 are provided as a pseudo fault occurrence means. ing. Further, as means for setting the occurrence timing of the pseudo fault, a timer register 5, a timer register all-zero detection circuit 6 for detecting that the timer register 5 has reached a predetermined value, a counting circuit 7 and a selection circuit 8 are provided. Have

The selection circuit 8 sets the value of the counter data line 25 in the 48-bit timer register 5 according to the instruction of the counter set instruction line 24 from the arithmetic control circuit 2. The counting circuit 7 counts down the contents of the timer register 5 by 1 in units of one machine clock. When the timer register all-zero detection circuit 6 detects that the countdown (timer register all-zero) corresponding to the contents of the timer register 5 is performed, it outputs an all-zero detection signal so as to generate a pseudo fault. In the machine error generation control circuit 4, when the output signal 29 from the control register 3 is valid when the all-zero detection signal 28 is input, a machine error is reported. It should be noted that the control register 3 is set via the signal line 26 as to whether the pseudo failure occurrence mode is enabled or disabled, and the output signal 29 is enabled when it is enabled.

A failure processing device 9 executes various kinds of failure processing in response to the machine error report signal 27 from the machine error occurrence control circuit 4.

As described above, in the present invention, the pseudo failure occurrence mode is instructed by the program instruction described later, and the underflow of the timer register 5 (timer register all zero) is detected by the means for setting the occurrence timing of the pseudo failure described above. When this happens, a pseudo fault (machine error) occurs.

During normal operation, the arithmetic control circuit 2 accesses the main memory 1 using the main memory request address signal 23 and the main memory request signal 22 and decodes the read program instruction using the main memory read path 21. Running. The write operation from the arithmetic control circuit 2 to the main memory 1 is executed using the main memory request address signal 23, the main memory request signal 22 and the main memory write path 20. The timer register 5 and the counting circuit 7 together 48
It functions as a bit counter and counts down by one every one machine clock, and starts counting again from the maximum value even if an underflow occurs. The timer register 5 is cleared to 0 by the initialization of the processor, and thereafter, the counting circuit 7 counts down by one every machine cycle. When the contents of the timer register 5 underflow, the timer register all-zero detection circuit 6 outputs the all-zero detection signal 28. When the all-zero detection signal 28 is input, the machine error generation control circuit 4 determines whether the output signal 29 from the control register 3 is valid. During normal operation, the control register 3 is not set to enable the output signal 29, so the machine error report signal 27 is not output, and the timer register 5 that has reached the maximum value again after underflow is counted again. Circuit 7
Then, one is counted down every machine cycle.

Next, the operation at the time of implementing the pseudo fault will be described with reference to the programs shown in FIGS. 2 and 3.

FIG. 2 is an example of a program for setting a pseudo fault, in which four program instructions are extracted from a series of program instructions.

The first program instruction is 186600 in the register D.
_This is an instruction to load _(H) . The second program instruction is an instruction to multiply the contents of the register A and the contents of the register B and store the result in the register A.
The third program instruction is an instruction to store the contents of the register A at the address of the main memory 1 modified by the contents of the register D. The fourth program instruction is an instruction for subtracting the content of the register C from the content of the register A and storing the result in the content of the register A. A, B, C, D are general-purpose registers,
The arithmetic control circuit 2 controls the program instructions as described above. In this embodiment,
A pseudo fault shall occur 48 machine cycles after the execution of the first instruction.

FIG. 3 shows a program in which a program instruction for generating a pseudo fault is inserted in order to generate a pseudo fault 48 machine cycles after the execution of the first instruction in the program of FIG. Of the six program instructions in FIG. 3, the first, fourth, fifth, and sixth program instructions are the same as the first, second, third, and fourth program instructions in FIG. The second and third program instructions are pseudo-fault program instructions. That is, the second program instruction in FIG. 3 is an instruction to load the content of 30 _(H) into the timer register 5. The contents of timer register 5, which is 30 _(H), is 48 more.
It is shown that the underflow is detected by the timer register all-zero detection circuit 6 when the machine cycle has elapsed.

The third program instruction is a program instruction for enabling the control register 3 to enable the pseudo failure generation mode, that is, setting the output signal 29 to be effective. When the timer register 5 underflows after the execution of this instruction. ，
This indicates that the machine error report signal 27 is output by the machine error occurrence control circuit 4. That is, the counter circuit 7 counts down the contents of the timer register 5, and when 48 machine cycles have passed, the timer register all-zero detection circuit 6 detects an underflow. Timer register all-zero detection signal by underflow detection
When 28 is output, the machine error occurrence control circuit 4 determines whether the output signal 29 from the control register 3 is valid. When the pseudo fault is executed, the control register 3 is set by the program instruction so as to enable the output signal 29. Therefore, the machine error report signal 27 is output and reported to the fault processing device 9, and the predetermined fault treatment is performed. Be implemented.

〔The invention's effect〕

As described above, according to the present invention, the pseudo failure mode is set by the program instruction, and the timer register is set so that the machine error can be generated at the time specified in the program in advance, so that the pseudo failure can be automated. This has the effect of facilitating the verification of the failure processing function realized by the hardware / firmware / operating system, and making it easy and reproducible.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing an example of a program instruction, and FIG. 3 is a diagram showing an example of a program instruction in which a pseudo fault is set. In the figure, 1 is a main memory device, 2 is an arithmetic control circuit, and 9 is a failure processing device.

Claims (1)

[Claims] 1. A control register for instructing the occurrence of a machine error by a program instruction, a counting means, a timer register whose value can be set by a program instruction, and a timer register which is counted by the counting means, and the contents of the timer register. Means for detecting that a predetermined value has been reached, and when it is detected that the contents of the timer register have reached a predetermined value, the control register is instructed to generate a machine error. An information processing apparatus having a machine error generation control circuit for generating a machine error report.