JPS6051273B2 - semiconductor output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Conventionally, in the CMOS integrated circuit structure shown in FIG.
The npn bipolar transistor 28 parasitic to the rLMOS transistor (drain 15, gate 16, source 17) using
, gate 13, source 12) constitutes a pnpn type thyristor.

At this time, an nMOS transistor (drain 4, gate 34, source 5, well 19, well bias high concentration layer 6, 3) and a bipolar transistor (base 20, emitter 8, base extraction high concentration layer 7, When one surge is applied to the output terminal 36 of 9), the np
The base of n transistor 28 is biased to 1, pn
The pn thyristor has turned on. This on state is called a latch-up state, and must be avoided because a large current flows through the element. Furthermore, when a Θ surge is applied to 36, the base of transistor 1 is bypassed to a negative voltage through transistor 2, resulting in a similar latch-up state.
The present invention improves the shortcomings of conventional CMOS integrated circuits,
An object of the present invention is to provide an output circuit that is less likely to cause latch-up due to external surges.

The gist of the present invention will be explained below with reference to FIG.

In FIG. 2, 60 Npn bipolar transistors have Npn bipolar transistors in type breakdown layers 40 and 45 formed in an n-type Si substrate 39.
It operates by applying 5V from the electrode 46, and its emitter breakdown layer 43 is connected to the resistance of the polycrystalline Sl layer 49 through the A1 layer 48 and to the drain n+ type layer 52 of the RlMOs transistor 61 through the A1 electrode 50. 52 is also connected to an output terminal 62.

Also, the base p-type layer 42 of the Npn bipolar transistor
, A1 taken out from the low resistance p+ type layers 41 and 44
Electrode 47 is connected to internal circuit 101 and supplied with a signal. Further, a signal is similarly supplied from the internal circuit 101 to the gate electrode 54 of the RlMOS transistor. Second
In the figure, 52 is a p-type well forming an NMOS transistor 61, 51 and 57 are p+-type layers for well bias, 55 is a source n+-type layer of an RlMOS transistor, and 5
6 and 58 are AI electrodes.

FIG. 3 compares the circuit of this embodiment with a conventional circuit (a circuit without the resistor 49 in FIG. 2).
In the case of = 0, latch-up occurs at a single surge voltage of approximately 100V, but by applying the present invention, it has become possible to tolerate surge voltages three times as high as 300V or more. Note that in this embodiment, since a high surge voltage is applied to the resistor, it is not suitable to form the resistor twice inside the substrate, such as in a diffusion layer, and it is preferable to form the resistor on the SlO2 surface.

For example, if a polycrystalline S] layer used for the gate is used, a resistive layer meeting the desired purpose can be formed, but it goes without saying that the present invention can be applied to any other resistor. The value of the resistor is desirably 1000 or less in view of the need to increase the high level voltage at the output terminal and the need to charge the load capacitance at the output terminal at high speed.

For example, the output amplitude at TTL level, that is, the output high level ■. To achieve H>2.4■, considering the bipolar voltage drop of 0.5■, the loss due to resistance must be 2V or less, so 100f! , when I. H is 207
TLA acceptable. In the above, we have described an example in which bipolar transistors are used in the output stage, but as shown in FIG. 4, RlMOS transistors 63 and 65, as shown in FIG.
It has been found that in the output stage using PMOS transistors 69 and 27, latch-up against surge voltages from output terminals 66 and 71 can be prevented by the same means using resistors 64 and 70.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the element structure of the internal circuit section and output circuit section of a conventional CMOS integrated circuit, FIG. 2A is a sectional view showing the element structure of an embodiment of the present invention, and FIG. 2B is a circuit diagram of one embodiment of the present invention, FIG. 3 is a characteristic diagram showing the effects of the present invention, and FIGS. 4 and 5 are circuit diagrams showing other embodiments of the present invention. 46... Collector electrode of Npn bipolar transistor, 47... Base electrode of Npn bipolar transistor, 49... Polycrystalline silicon resistor, 54... Gate electrode of NMOS transistor, 60
...Npn bipolar transistor, 61...
・NMOS transistor, 62...Output terminal.

Claims (1)

[Claims] 1 The collector of the bipolar transistor is connected to the power supply voltage Vc
c, the emitter is connected to the output terminal through a resistor R, the drain and source of the MOS transistor are connected between the output terminal and ground, and the base of the bipolar transistor and the gate of the MOS transistor are connected to a signal from other internal circuits. A semiconductor output circuit that is supplied with a signal, shapes and amplifies the signal, and supplies it to the output terminal.