JPS6052466B2 - Distributed interrupt priority control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a split control method and device for priority control when a system is configured with a device shared by a plurality of devices.

In many cases, a plurality of devices are connected to a shared bus line, and each device transmits information via the shared bus line.

Furthermore, although each of the plurality of devices is independently connected to a shared device, the devices cannot be used at the same time, and unless some kind of priority control is performed, a conflict problem will occur and confusion will occur. Therefore, it is necessary to perform some kind of priority control when using the above-mentioned shared buses or shared devices (hereinafter referred to as shared resources). Conventionally, the following methods have been used to address this problem. One method is to provide a priority control device that controls usage requests from multiple devices.

This device accepts usage requests from multiple devices and grants each device permission to use the shared resource according to a predetermined priority order. However, a priority control device is required, and a signal line is required for receiving requests, returning permission signals, etc.Furthermore, an abnormality in the priority control device will affect all of the multiple devices. There are drawbacks. Another example is the Special Publication of 1984-2948.

This is a method that does not provide a centralized priority control device as described above. In addition to distributing contention control, the right to use resources is passed in a round-robin manner, and requires a priority storage element reset signal line, a mask signal line, etc., and is not compatible with the so-called daisy chain method. Applicable. However, there is a drawback that if a part of the chain is removed or breaks down, priority control of subsequent devices becomes impossible. Another technique of this type is Japanese Patent Application Laid-Open No. 181734, but it has the same drawbacks. In order to solve these drawbacks, the inventors invented the method described below, and filed patent application No. 56-35378 (Showa 5@
A patent application was filed as (patent application dated March 13). We have already filed an application to solve these shortcomings.

The gist of this is that each device that shares one resource determines whether the shared resource is currently being used by any device, and the time when the shared resource is no longer used or the estimated time when it will no longer be used. When the elapsed time is equal to the unique time set for each device, if the device requests the use of the shared resource, the device is granted the right to use the shared resource. The advantage lies in making it possible to use shared resources. However, if there are differences in shared device use request labels among multiple devices, such as regular use and emergency use, this may not be able to be adequately addressed. In other words, if there is a device that is used infrequently in normal times and has a low priority for shared device use, but requires high priority in an emergency, this invention alone cannot solve the problem! There is no concept of regular use, emergency use, or interruption. If the priority of the device is set high, the waiting time of other devices becomes long, and if the priority is set low, the interrupt is of no use. The present invention is a control method that improves the above invention, divides requests for use of a shared device into three levels within each device, and performs contention control when using the shared device according to each level by distributing it to each device. It provides:

In the present invention, in each device that shares one equipment, it is determined whether the shared device is currently being used by any device or not, and the time when the shared device is no longer used or the time when the shared device is no longer used or Measure the elapsed time from the time of use,
When the measured times match a predetermined period, if any device receives an interrupt request, that device notifies the other devices of the interrupt request, and then transmits the interrupt request to each of the multiple devices at a unique preset time. If no other device is able to monopolize the shared device within a period of time, the shared device is used exclusively, and the shared device is made known to other devices that the shared device is dedicated, and the shared device is used interruptively. It is distinctive in that it has been made to work.

Embodiments of the present invention will be described below with reference to the drawings.

) FIG. 1 shows an embodiment of the present invention. In this example, a plurality of devices (CPUs) 11 to 13 share a bus 101 and an input/output device (1/σ) 10. The CPUs 11-13 mutually monitor the usage status of the bus 101 via the busy line 100. In this embodiment, the busy line 100 is short-circuited, indicating that the I/O bus 101 is in use, and in the open 7 state, indicating that the I/O bus 101 is not in use. Hereinafter, how each CPUll-13 obtains the right to use the I/0 bus 101 will be explained with reference to FIG. FIG. 2 shows a portion of the I/0 bus 101 usage right control circuit of each CPU11-13 according to the present invention. Clock pulses are inputted via a frequency divider 127 to a counter 120 that cyclically counts the pulses of the clock CLK.

When the busy line 100 is in the short state (hereinafter expressed as “L”), it is in the set state, and when the busy line is in the open state (hereinafter expressed as ゜゜H゛), it starts counting. That is, when the busy line is in the “゜゜” From L゛ to “H”
When any CPU finishes using the I/O bus 101, the counters 12 in each CPU11 to 13
0 starts counting at the same time. The counter output is input to a comparator 121 and compared with a set value C3 which is set to a different value for each CPU, and only when they match, an output signal is generated.
trigger. When the flip-flop 122 is triggered, if there is no usage request Sreq or Leq, the flip-flop 122 remains in the set state and the I/0 bus 1
01 and the busy line 100.

On the other hand, when the flip-flop is triggered, if there is a normal use request (S, eq) or an interrupt use request (,Eq), the flip-flop 122 is set and generates an output signal. Then, when there is a request for use, the flip-flop 122
Under the condition that is 0N, the AND gate 123 becomes 0N, and the transmission data is transmitted via the output gate 125 using the bus 101. It starts occupying the bus 101 and puts the busy line 100 in the "L" state. This can be realized by the transistor circuit 124 as shown in FIG. 2. In this state, the counter 1 of all CPUs (devices)
20 enters the reset state, and CPUs other than the CPU (12 and 13 if the CPU is 11) are unable to use the bus 101.

The CPU that has obtained the right to use the 1/O bus 101 releases the use request after completing a series of data transmission processes.

releasing output gate 125 for 1/0 bus 101;
At the same time, the busy line 100 is set to the "H'3" state.

Thereafter, the counter 120 in each CPU starts counting from the initial state and repeats the above operation.

The above is the operation common to the normal use request and the interrupt use request. Next, the operation specific to the interrupt use request will be explained. The comparator 131 generates an output signal only when the output of the counter 120 becomes "1.3" and triggers the flip-flop 132 by the output signal Tei.

When flip-flop 132 is triggered, if there is no interrupt use request (1, q), flip-flop 13
2 The one-shot trigger circuit 134 maintains the set state.
has no effect on. On the other hand, when the flip-flop 132 is triggered, if the interrupt use request (, Eq
), the flip-flop 132 is set, and its output triggers the re-upshot trigger circuit 134, which sets the busy line 100 to "L" for a certain period of time via the logical sum 135 and the transistor 124 to issue an interrupt request.
In this way, if one of the devices sets the busy line 100 to 0.0L when the counter value is 66r1, the flip-flop 130 is set. Based on the above explanation, the operations will be explained based on the presence or absence of an interrupt request and whether the device issuing the interrupt request is the device or another device. 1) If none of the devices generates an interrupt request, the counter 120 counts up, and the flip-flop 130 and the flip-flop 13
2 is not set, AND gate 133 is turned off, and OR gate 129 is not affected.

1) When the device issues an interrupt request, the counter 120 is counted up and the flip-flops 130 and 132 are both set, so the AND gate 133 becomes an OR state and the OR gate 129 is not affected.

In this case, since an interrupt request (1.eq) is output, if the counter matches the set value (C,), the device obtains the right to use the bus 101 as described above. However, if another device with a higher priority, that is, a smaller setting value, performs a similar operation than the device in question, the frequency divider 127 and counter 120 will be reset by the busy signal issued from that device. , the output Tc$ of the comparator 121 is not generated, and the use of the bus 101 by the device is made to wait until after other devices finish using the bus 101. {) If the device in question does not issue an interrupt request, but one or more other devices issue an interrupt request, counter 120 counts up, flip-flop 130 is set, and flip-flop 1
32 maintains the set state, so the AND gate 133 becomes 0.
Flip-flop 12 through N and OR gate 129
2 is kept in the set state and requests for use of the device Sreq
and Ireq will not be accepted.

This state is maintained until one of the other devices, ie, the device with the highest priority among the devices that issued the interrupt request, occupies the bus 101 and issues a busy signal. 128 is 0R
A gate, Sreq, . I. This is to reset the flip-flop 122 when neither eq is asserted.

As described above, interrupt requests for any device have priority over normal usage requests for the other device, and among multiple interrupt requests, priority is given to the first come first served, and if they are simultaneous, priority is given according to the set value. , the use of bus 101] is allowed.

Time 1 art in the case where there is no interruption among the above operations is shown in FIGS. 3a to 3h. In Figure 3, the setting value Cs assigned to each CPU is ゜゜2゛, CPUll is ゜゜2゛,
2 is set to "3", and CPU13 is set to "4". First, at the time 160 when the counter value reaches ゜゜2゛, the CPU1
1 and CPU 13 are issuing usage requests 151 and 154.

At this point, CPUll, whose set value is 2, acquires the right to use the bus and immediately sends a busy signal 150 to the busy line to use the bus. This resets the counter, which remains in that state until CPU11 finishes using the bus. When CPUll finishes using the bus 152, the busy line is released and the counter starts counting again. Here, the usage request 154 from the CPU 13 is accepted at the time 161 when the counter value reaches '6'', and the CPU 13 performs the predetermined operation as described above. Usage request 15 from CPUl2 issued after that
7 is accepted at the time 162 when the bus use 155 of CPU13 is finished and the counter value reaches ゜"3゛. 154
The CPU 13 terminates the use of the bus 155 and releases the request, and at the same time releases the busy line 153.

Next, time charts for the case where there is an interruption will be explained with reference to FIGS. 4a to 4k. Also in this figure, the set value Cs assigned to each CPU is the same as in FIG. 3. First, at the time 261 when the counter value reaches "1", the CPU
A normal use request 259 for CPU 1 and an interrupt use request 252 for CPU 13 are issued.

At this point, the CP that is issuing the interrupt request 252
Ul3 outputs an interrupt request signal 250 on the busy line, inhibiting requests from other CPUs. Thereafter, the counter that has been set once is counted up, and when the count value reaches "4", the CPU 13 sends out a busy signal 251 and uses the bus.The counter is thereby reset, and the state is such that the CPU 13 does not use the bus. Continues until finished.
When the CPU 13 finishes using the bus 253, the busy line is released and the counter starts counting again. Next, at the time 263 when the counter value reaches "1", the CPU
A normal use request for CPU l is output, but at the same time
Since the interrupt use request is output, CPU12 operates in the same manner as CPU13 described above. Counting starts after the bus use of CPU12 ends 257, and at the time 265 when the counter value reaches ゜゜1゛, no interrupt request has been issued from any CPU, and only the normal use request of CPUll has been output. , when the count value reaches 6.2 degrees, CPUll issues a busy signal and the bus can be used. 259 is the point at which CPUll terminates the use of the bus 260 and releases the request, and at the same time releases the busy line 258.

FIGS. 5a to 5k show a case in which normal use requests are issued from CPUll and CPUl2, and an interrupt use request is issued from CPUl3 at the time when CPUll has already acquired the right to use the bus.

At the time point 360 when the counter value reaches 6621, the CPU
A normal use request 351 for CPU11 and a normal use request 358 for CPU12 are issued.

At this point, CPUll sends a busy signal 350 and uses the bus 352. Furthermore, if an interrupt use request 355 occurs to CPU13 while CPU11 is using the bus, CPU11 finishes using the bus 351, and at the time 361 when the counter value reaches ゛゜1゛, an interrupt is issued from CPU13 on the busy line. Input request signal 353 is output and other CP
Forbid U's request. After that, the same operation as explained in FIG.
A normal use 359 of Ul2 takes place. As described above, if an interrupt use request is issued to a CPU while one CPU is using the bus, the bus use that is currently in progress will not be affected and the bus will continue to be used. It can be seen that after bus use is finished, interrupt requests take priority over any normal use requests.

As described above, this embodiment makes it possible to control interrupts, but it should be noted that the reason for using "1" as the setting value for interrupt requests is that This is to simplify the hardware.In some cases, by configuring the interrupt time slot with separate hardware, it is possible to eliminate the need to use the set value of ゜゜1゛.Also, It is easy to imagine that the up counter, comparator, etc. in this embodiment can be replaced with a down counter or presettable counter.

Furthermore, in this embodiment, the busy line is released after the shared resource is used, but this is done to simplify the hardware. If it is desired to further improve the throughput, a method can be adopted in which the busy line is released within a certain period of time before the end of use of the shared resource. However, in this case,
It is necessary to set the above-mentioned certain period of time to ensure that at the time one device starts using the shared resource, other devices have finished using the shared resource. This is done in order to increase the efficiency of shared resource usage by predicting the end time in advance and starting counting on the counter, so that the device that has issued the usage request can use the shared resource as soon as it ends. be.

Further, in this embodiment, a counter and a clock are used to measure the time elapsed after bus use ends, but this portion can be replaced with, for example, a one-shot circuit.

Furthermore, in a device that uses a counter and a clock signal as in this embodiment, if no usage request is issued for a long time, that is, if no busy signal is issued from any device, the frequency of each clock will change. Due to the discrepancy, there is a risk that each counter will not be able to synchronize and count.

In order to avoid this, if the counter counts out, a busy signal is forcibly transmitted for a moment, and the counter is synchronized by the busy signal. Furthermore, it was stated in the earlier application that the present invention does not particularly require a busy line.

I will omit that here. According to the present invention, in addition to the normal use of a shared device in a shared system, contention control can be distributed to each device for interruptive use, thereby improving reliability and responsiveness.

[Brief explanation of drawings]

FIG. 1 shows a system configuration of an embodiment in which the present invention is adopted for shared bus right control between multiple CPUs, FIG. 2 shows a control circuit configuration according to the present invention in FIG. 1, and FIGS. 1 shows the transition of bus usage rights in FIG. 1, and FIG. 5 shows a diagram explaining the relationship between normal requests and interrupt requests. 121, 131... Comparator, 120, 130,
122, 132...Flip-flop, 134.
...One shot circuit.

Claims (1)

[Claims] 1 Has a shared device that can be used by multiple devices,
A system in which the plurality of devices monitor the usage status of the shared device and use the shared device as necessary, and at the point when it is determined that the shared device is no longer being used by any of the plurality of devices; The device uses the shared device when the measured elapsed time matches a unique time set in advance and there is a request for the device to use the shared device. In a system that allows interrupt requests to be made to the plurality of devices, the interrupt request from the other device will be processed within the minimum count time from the point in time when there is no longer any use from any of the plurality of devices. When the use of the shared device is prohibited and the measured elapsed time coincides with a unique time set in advance, the device transmits an interrupt request with priority over the use requests of other devices and uses the shared device. A split-type priority interrupt control method characterized in that it is used.