JPS6052497B2 - Signal recording and reproducing device using PCM method - Google Patents

Description

[Detailed description of the invention] The present invention relates to a signal recording/reproducing device using the PCM method.

When the PCM system is used, a normal audio tape recorder is unsuitable as a recording/playback device because the signal spans a wide band. Therefore, a VTR (video tape recorder)
It is possible to use A VTR originally has the function of recording and reproducing television signals, and it is preferable that it can record and reproduce PCM digital signals without impairing this function. Taking these points into consideration, the present invention is applied to a device that changes a PCM digital signal into a waveform similar to a television signal, thereby making it possible to record and reproduce PCM signals without making any changes to the VTR itself. It is something.

Figure 1 shows an outline of a device for recording and reproducing acoustic signals in PCM format using a VTR.
It shows a head type VTR, 2i is its recording signal input terminal,
20 is its reproduction signal output terminal.

Further, 3L indicates an input terminal for the left signal of an acoustic signal, for example, a 2-channel stereo signal, and this signal is passed through a low-pass filter 4L, so that the high frequency range is somewhat limited, and is sampled by a sampling and holding circuit 5L. 6L converts the J sampling output into a parallel code, which is further converted into a serial code by a parallel-to-serial converter 7, and is written into the memory device 8. On the other hand, the right signal is supplied from the input terminal 3R, is converted into a parallel code by passing through a low-pass filter 4R, a sampling hold circuit 5R, and an AD converter 6R, and is further converted into a serial code by a parallel-serial converter 7. , written to the memory device 8. The readout output of the memory device 8 is supplied to a mixer 9, where an equalization pulse and a synchronization signal are added, and then supplied to the recording signal input terminal 21 of the VTR1, which is composed of an FM modulator and the like (not shown). The data are sequentially recorded as inclined tracks on a magnetic tape by two rotating magnetic heads through a recording system of a VTR1. Note that 10 is a pulse generator that generates gate pulses supplied to sampling and hold circuits 5L and 5R, clock pulses for AD converters 6L and 6R and parallel-serial converter 7, clock pulses for memory device 8, equalization pulses, and synchronization signals. , and 11 indicates a fixed reference clock generator.

During playback, a playback signal with a waveform similar to the above-mentioned recording signal waveform appears from the output terminal 20 and is supplied to the synchronization separation circuit 29, and only data is obtained at its output, which is written into the memory device 28.

The memory device 2 expands the data along the time axis, contrary to the recording process, and removes time axis fluctuations such as jitter, so that the read output of the memory device 28 has no missing data and no time axis fluctuations. This is converted into a parallel code by the serial/parallel converter 27, and then converted into a parallel code by the DA converter 26L, 26R and the low-pass filter 24L, 24.
A stereo left signal and a stereo right signal continuous to the terminals 23L and 23R are demodulated and obtained through the terminals R, respectively. The synchronization signals separated by the synchronization separation circuit 29 are supplied to the pulse generator 20, and based on these synchronization signals, clock pulses and control pulses for the memory device 28, serial/parallel converter 27, and DA converters 26L and 2 are generated.
A clock pulse for 6R is formed. As described above, when an audio signal is recorded and reproduced using the PCM method using a VTR1, the recording signal waveform containing digital information is formally the same as the television signal.

This records audio signals using the PCM method! The signal processing circuit for playback is in the form of an adapter, and in addition to the original function of recording and playing back television signals, by attaching the above adapter, you can record and play back high-quality audio signals without making any changes to the VTR itself. This is so that you can do it. Second
Figure A shows a recording signal waveform considered based on such considerations, in which the horizontal synchronizing signal HD, the vertical synchronizing signal VD, and data are arranged in series in units of one field of the television signal.

As an example, based on the frequency characteristics of TRl, the maximum transmission bit rate is 1.4 MbIsec, and the number of bits required to encode an audio signal is 26 bits per word, and each word (hereinafter referred to as 1 block) has a maximum transmission bit rate of 1.4 MbIsec. The number of bits allocated to the horizontal synchronization signal HD inserted in The transmission ray Ji-Ft per block that satisfies the conditions is 47.2
It becomes 5KHz. In addition to the above conditions, the sampling frequency Fs is determined by adding a condition to select the analog signal sampling rate Fs and transmission rate f in an integer ratio relationship in order to compress and expand the time axis of data within one field. Therefore, the sampling rate Fs is 44.1K.
Selected as Hz. At this time (F,:Fs=15:14)
becomes. Therefore, the data sampled during one field (Arec) is 735 samples. Since this is sent at a transmission rate F, which is three times the horizontal frequency of the television signal, the data in one field is 735 blocks (245H in time) as shown in FIG. 2A. Therefore, the data missing period IRG in one field is (262
．． 5H-245H=17.5H). This period 1R
As shown in FIG. 2C, an equalizing pulse is inserted into G over a targeted period similar to the equalizing pulse of the television signal, and a vertical synchronizing signal D is inserted in the targeted period following this equalizing pulse.
is inserted. The equalization pulse is a negative pulse with a pulse width equivalent to 1 bit and a period of 14 bits, and the vertical synchronization signal VD
contains a positive pulse with a pulse width equivalent to 2 bits and a period of 14 bits. In addition, the vertical synchronization signal VD in the television signal
The equalization pulse following is not particularly required and is therefore not inserted. Also, data is input from a point 3 blocks away from the trailing edge of the vertical synchronization signal VD for even fields and 2.5 blocks for odd fields, and the period is 1R.
G is set to be 17.5H on average. Furthermore, no data is inserted in the approximately 10H period before the equalization pulse, and only the horizontal synchronization signal HD is inserted, so that it is not affected by noise caused by head switching, etc. that occurs near the vertical synchronization signal D. has been done. Further, the number N of bits allocated to one block of data is selected to be 28 bits from the highest transmission bit of VTR1.

FIG. 2B shows this one block, in which one word of 26-bit data is inserted after a horizontal synchronizing signal having a pulse width equivalent to 2 bits. In this case, the left and right signal data of the two-channel stereo signal are 13 bits each, and the left signal data is inserted in the first half of one block, and the right signal data is inserted in the second half. ing. The horizontal synchronizing signal D has a more negative level than the data ゜゜0゛, and the amplitude ratio of the two is (3:7). In the above PCM recording and reproducing apparatus for acoustic signals,
Memory devices 8 and 28 are required to be able to be written and read asynchronously in order to convert the time axis of data.

For this reason, first-in-first-out (FirstInFirstOut), which can write and read simultaneously,
t) type shift register can be applied. However, this shift register is disadvantageous compared to RAM in terms of cost when applied when a capacity of several kilobits or more is required. On the other hand, when operating a RAM, it is impossible to perform writing and reading asynchronously because there is a risk that writing and reading will overlap for the same address. However, by devising control over the RAM, writing and reading can be performed asynchronously. Furthermore, although the recording and reproducing system of the acoustic signal recording and reproducing apparatus shown in FIG. desirable in that respect.

FIG. 3 shows the memory device and its peripheral circuits in this case. In Fig. 3, 30 is an input amplifier, 31 is a RAM
l32 is a memory control circuit including an address counter, etc.
37 is a serial/parallel converter. 41, 42, 43, 44,
Reference numeral 45 indicates a switching circuit that is switched depending on the operating state of the VTRl, that is, whether the TRl is in a recording state or a playback state. Here, there is something connected to the PLB side. The switching circuits 41 to 45 are the recording switch 4
The mode signal REC.6 is generated by the mode signal generator 47 based on the operation of the mode signal REC.6. ．． controlled by PLB.
During recording, the recording switch 46 is turned on and the
Parallel data from the D converter is converted into a serial code by the serial/parallel converter 37 and written to the RAM 3l via the switching circuit 41, and the time-base compressed data from the RAM 3l is sent to the mixer 9 via the switching circuit 42. A synchronizing signal is added to the mixer 9, and the signal is supplied to TRl as a recording signal.

A synchronization signal is generated by a synchronization signal generator 33 from the output of the reference clock generator 11. Furthermore, since the conversion of the time axis of data is performed in conjunction with (synchronization with) the synchronization signal, the synchronization signal is supplied to the memory control circuit 32 via the switching circuit 45. At the same time, a start/stop signal from the start/stop signal generator 35 is supplied to the memory control circuit 32 and the serial/parallel converter 37, thereby defining the timing of data processing for one field. For this purpose, mode signals REC and PLB are supplied to the start/stop signal generator 35, as well as a synchronization signal via the switching circuit 43 and the synchronization separation circuit 36. Further, a clock pulse generator 34 generates clock pulses for the RAM 31 and the serial/parallel converter 37. Next, at the time of reproduction, the recording switch 46 is turned off, and the switching circuits 41 to 45 are in a state different from the state shown in the figure, in which they are connected to the PLB side or the tile side.

Then, the reproduced signal from TRl is written to R and AM3l via the input amplifier 30 and switching circuit 41, and
A synchronization signal is separated from the reproduced signal by a synchronization separation circuit 36. A clock pulse is generated from the clock pulse generator 34 in conjunction with this synchronization signal,
A start/stop signal is generated in a start/stop signal generator 35. And RAr! 431, the time axis of the data is expanded and supplied to the serial/parallel converter 37 via the switching circuit 42, where it is converted into a parallel code and then supplied to the DA converter. The mode signal generator 47 generates a mode signal based on the on/off state of the recording switch 46, and in this case is configured so that the actually generated mode signal is synchronized with the synchronization signal. Also, mode l
In addition to the signal, a standby signal STBY is generated to clear the address counter of the memory control circuit 32 and the serial/parallel converter 37. The present invention aims to provide a start/stop signal generator 35 that can be used for both recording and reproducing as described above.

Further, one embodiment of the present invention will be described in detail. FIG. 4 shows the configuration of the mode signal generator 47. When the recording switch 46 is turned on, its output becomes "0" as shown in FIG. 5A, and this becomes a signal rainbow.

The signal is supplied to a NAND circuit 52 via an inverter 51, delayed by an integrating circuit 63, and supplied to an inverter 54. The output of this inverter 54 is as shown in FIG. 5B, and since this is supplied to the NAND circuit 52, the output of the NAND circuit 52 is as shown in FIG. 5C. Further, the output of the inverter 54 is supplied to the inverter 56 via the integrating circuit 55, and the output of the inverter 56 becomes as shown in FIG. 5D, which becomes the signal REC. In addition, when the output of the inverter 51 is ゛“0゛,
The reproduced vertical synchronization signal PSV separated from the reproduced signal shown in
A monostable multivibrator (referred to as monomulti) MMIO is provided which is triggered by the rising edge of D.
The time constant of the mono-multi MMlO is selected so that it has a metastable period longer than one field (Ec), and the structure is such that it can be retriggered. Therefore, mono-multi MM
Since lO is triggered by the first reproduced vertical synchronization signal PSVD and thereafter retriggered, its output Q is
The state of ゜゜1゛ is maintained as shown in Figure F. This output Q is supplied to the NAND circuit 57 and also to the NAND circuit 57 via the integrating circuit 58 and the inverter 59.
-The output of the inverter 59 is as shown in FIG. 5G,
Therefore, the output of the NAND circuit 57 is as shown in H in the figure. Further, the output of the inverter 59 is supplied to the inverter 61 via the integrating circuit 60, and its output (FIG. 5 1) becomes the mode signal PLB. Ma. In addition, NAND circuits 52 and 5
7 is supplied to the NAND circuit 62, and the NAND circuit 62
The output of the inverter 63 is supplied to the inverter 63, and the output of the inverter 63 shown in FIG. 5J becomes the standby signal STBY.
With the above configuration of the mode signal generator 47, the mode signals REC, . Advantageously, it is possible to form a PLB and a standby signal STBY which is generated when the recording switch 46 is turned on and when it is turned off and the first reproduction vertical synchronization signal PSVD is generated. FIG. 6 shows an example of the clock pulse generator 34 for forming clock pulses from the mode signal from the mode signal generator 47 mentioned above and the reference clock pulse from the reference clock generator 11.
The reference clock generator 11 is configured as a stable oscillator such as a crystal oscillator, and has a transmission lock frequency (28fL=1.
323MHz) signal. During recording, the mode signal REC is supplied to the frequency divider 94 via the NAND circuits 91 and 92, and the frequency is divided into ± to produce the sampling signal RSM of the Sun J3O pulling frequency Fs (44.1 KHz).
PL is formed.

Furthermore, the clock 0 (; (26f9)) for converting the AD-converted parallel 26-bit signal into a serial code is a phase comparator 95, a pass filter 96, a VCO (voltage controlled variable frequency oscillator) 97, and a frequency divider. Ratio divider 98
It is formed by a PLL circuit 107 consisting of. This clock KWC serves as a write clock for the RAM 3l during recording, and is taken out via a NAND circuit 99.
PLL circuit 107 is used to synchronize sampling signal RSMPL and clock KWC.
Read clock of RAM3l during recording? is formed by passing the output of the reference clock generator 11 through the gate circuit 100. During playback, the horizontal synchronization signal PHD separated from the playback signal is passed through a PLL consisting of a phase comparator circuit 101, a low-pass filter 102, a VCO1O3, and a frequency divider 104.
A signal with a transmission lock frequency of 28f synchronized with the horizontal synchronizing signal PHD is formed by being supplied to the circuit 108, and this signal is taken out via the NAND circuit 105 only during reproduction.
The write clock information for RAM 3l is obtained. Along with this, the output of the PLL circuit 108 is transmitted to the NAND circuits 93 and 92.
The output of the PLL circuit 107 is supplied to the frequency divider 94 to form a sampling signal PSMPL during playback in the same manner as during recording.
6, and its output includes a read clock for the RAM 3l and a clock for converting serial data into parallel data. is obtained. Here, the PLL circuit 108 is designed to sufficiently respond to relatively fast time axis fluctuations such as jitter included in the reproduced signal, and even if the horizontal synchronization signal PHD is lost due to dropout etc., the oscillation frequency of the VCO103 remains unchanged. The locking range is said to be narrow to prevent large deviations.

On the other hand, the PLL circuit 107 is designed not to respond to time axis fluctuations in the reproduced signal, and generates a constant cycle clock 100 even during reproduction. As an example, if correction for time axis fluctuations is to be performed on components of 0.2 Hz or more, it is designed to respond only to slower components below that. Therefore, although the clock may have slow time axis fluctuations of 0.2 Hz or less during reproduction, there is no adverse effect when the demodulated signal is reproduced by a speaker or the like. With the above configuration, the clock pulse generator 34 can be used both during recording and during reproduction. FIG. 7 shows a start/stop signal generator 35 that generates a start/stop signal for controlling the start and stop of writing and reading of the RAM 3l according to the present invention, and in the same figure, 109, 110, and 111 are connected in series. It is a binary counter. During recording, the NAND circuit 11
2, 113, the horizontal synchronizing signal generated by the synchronizing signal generator 33 is counted by counters 109, 110, 111, and during reproduction, the reproduced composite synchronizing signal PSYNC is counted by counters 109, 110, 111 via NAND circuits 114, 113. 109,110
, 111. The reproduced composite synchronization signal PSYNC is a synchronization signal obtained by supplying the signal reproduced from TRl to the synchronization separation circuit 36 and separating it, and includes a horizontal synchronization signal and a vertical synchronization signal. Figure 8A shows the mode signal (REC
(or PLB), and B in the figure shows a horizontal synchronization signal (RHD or PSYNC) to be counted. counter 109,1
The predetermined outputs of 10 and 111 are supplied to the NAND circuit 115, and when 7 horizontal synchronizing signals are counted, the output becomes "0", and is further passed through the waveform shaping circuit 116 to produce the output as shown in FIG. A pulse shown in is obtained, and this pulse is supplied to the NAND circuit 117. Also, the NAND circuit 118
, 119, 120, the vertical synchronization signal (RSV) shown in FIG.
D or PSVD) is supplied to the NAND circuit 117. The output of the NAND circuit 117 is the counter 109, 110, 11
Therefore, the counters 109, 110, and 111 are cleared at the rising edge of the vertical synchronizing signal RSVD or PSVD or the rising edge of the output of the waveform shaping circuit 116. At the same time, the RS type flip-flop FEl is set by the rising edge of the vertical synchronizing signal obtained from the output of the NAND circuit 119, which is inverted by the inverter, and when the counting power of the counter 111 reaches 51SJ, it becomes ゜゛1゛. As a result of the fall of the output shown in FIG. 8F, the flip-flop FEl is set, and its output Q becomes the window signal WND. Wind signal WND is shown in Figure 9A.
As shown in the enlarged diagram, the period of one field is defined, and the period of 7 horizontal synchronizing signals counted from the beginning of the field is "゜1゛", and the remaining period of the field is "0". , defines the length (735 blocks) of data to be processed in one field. During recording, the window signal WND is generally not phase-synchronized with the sampling signal RSMPL that samples the analog signal, so the window signal WND cannot be used as it is as a write start/stop signal for the RAM, and is synchronized with the signal RSMPL by the D-type flip-flop DFl. The 9th
The signal RWND shown in Figure B is formed, and the signal RWND is
By being supplied to the type flip-flop DF2, a write start/stop signal RWG which becomes "1" from the trailing edge (rising edge) of the signal RWND is formed.

The read start/stop signal PRG during recording is shown in Figure 9D.
As shown in FIG. 3, the signal RWND is delayed by τ1 from the rising edge of the signal RWND. This is because, as shown in FIG. 2, data is inserted from 3 blocks away for even fields and 2.5 blocks away for odd fields. However, the vertical synchronization signal RSVD from the synchronization separation circuit 36 is delayed by one block in the case of an even field and by 0.5 blocks in the case of an odd field from the trailing edge of the actual vertical synchronization signal. Therefore, τ1 may be equal to 2 blocks. Therefore, the signal RWND. is connected to the D-type flip-flop D via NAND circuits 121 and 122.
F3 and its output Q is supplied to the D-type flip-flop D.
F4, while these D flip-flops DF
NAND circuit 124,
A horizontal synchronizing signal j is supplied through the D-type flip-flop DF4, and a read start/stop signal RRG at the time of recording is obtained at the output of the D-type flip-flop DF4. During playback, the window signal WND is connected to the NAND circuits 123 and 12.
2 to the D-type flip-flops DF3 and DF4, and the reproduced composite synchronization signal is supplied to the D-type flip-flops DF3 and DF4 via NAND circuits 126 and 125 as clock inputs, thereby starting a write start similar to that during recording. A top signal PWG is formed.

During reproduction, the read start/stop signal PRG changes to “1” at the same timing as the write start/stop signal PWG.
However, considering that the reproduced signal includes time axis fluctuations due to jitter, etc., the monomulti MMll is generated at the falling edge of the window signal WND passed through the NAND circuit 123. delayed by triggering,
The output thereof is supplied to a D-type flip-flop DF5 so as to be synchronized with the sampling signal PSMPL. FIG. 9E shows the read start/stop signal PRG. The start/stop signals RWG, RRG, PWG, and PRG formed as described above are transmitted to the memory control circuit 3.
2, and the start and stop of write and read operations of the RAM 3l are controlled. That is, during recording, the write start/stop signal RWG is used as the write clock RWC.
Writing is performed continuously by gating the continuous start/stop signal RRG, while writing is started with a delay of only the time required for data compression and τ1 by gating the continuous start/stop signal RRG. is started. And data for one field (735
The timing at which writing of the program (program) ends coincides with the timing at which reading thereof ends. During playback, writing is started by gating the write clock PWC using the write start/stop signal PWG, and then the read clock PRG is activated using the read start/stop signal PRG after a time delay necessary to compensate for time axis fluctuations. Reading is started by gating. FIG. 10 shows a RAM and its peripheral circuits (indicated by 31 in FIG. 3) that write and read data based on the above-mentioned start-stop signal and clock pulse, and 131 is, for example, 4 (32X32=10
24-bit) static MOS/RAM.

Here, the capacity CA (proc) required for compressing or expanding the time axis of data processed in units of one field, the capacity CB (proc) required for correction of time axis fluctuations,
If the total capacity is CM=CA+CB, the capacity CM is RAM
It is nothing but what is required.

As mentioned above, the writing rate to the memory device during recording is Fs (44.1 KHz), which is equal to the sampling rate, and the reading rate is Fs (44.1 KHz), which is equal to the transmission rate.
．． 25KHz). However, the frequencies Fs and F are in block units. The memory device is configured so that writing and reading can be performed independently, and reading is started after 1 sec has elapsed from the start of writing in response to the start/stop signals RWG and RRG mentioned above.
Since the timing at which data of 5 blocks is written is made to coincide with the timing at which reading thereof is finished, the minimum capacity CA required for time axis compression and expansion can be determined by the following equation. CA=49 proc=1274 bits At the next playback, start/stop signals PWG and PR
Is the compensation range for time axis fluctuation ±? (protsk)
Then, the start of reading is delayed by Sec in advance.

As an example, approximately 12 blocks of CB are required to compensate for time axis fluctuations, so the capacity CM is CM=CA+
CB=61 blocks=1586 bits.

In one embodiment of the present invention, from the viewpoint of cost, a RAM having a long cycle time is used, and two RAMs each having 1024 bits per package are operated in parallel.
Therefore, serial data is converted into 2-bit parallel data and R. It is necessary to write to AM and convert the 2-bit parallel read output of RAM to serial data. However, since this consideration is not an essential problem for the present invention, the following description will be made with respect to one RAM 13l. In FIG. 10, 132 is an x address decoder, 133 is a Y address decoder, 134 is a write circuit, and 135 is a read circuit. Data D! N is input buffer register 136
The data is converted into data BRi synchronized with the write clock WC and supplied to the write circuit 134.
The readout output via the readout circuit 135 is supplied to an output buffer register 137, from which an output BRO is taken out in synchronization with the address selection signal ADSLCT, and further supplied to the D flip-flop DF6, which is clocked at a constant rate by the readout clock RC. Output data D converted to .
O, is obtained. Note that the write/read control signal W is supplied to the write circuit 134. The memory control circuit 32 for the above-mentioned RAM 13l and its peripheral circuits has a write clock WC and a read clock R as shown in FIG.
Address selection signals ADSLCT and ADSLCT from C
, a memory control signal generation circuit 138 that generates a write/read control signal WV, and an address code A.

-A9. Here, the write clock WC is the write clock KW during recording generated by the clock pulse generator shown in FIG.
The read clock RC is obtained by supplying the NAND circuit 139 with the write clock C and the write clock during reproduction, and the read clock RC is obtained by supplying the read clock sequence during recording and the read clock C during reproduction to the NAND circuit 141. It is something that can be done. Also,
In FIG. 11, 143 is the 10-bit output WAO-
A write address counter that generates WA9, 14
4 is a read address counter that generates a 10-bit output RAO-RA9. During recording, a write clock WC gated by a write start/stop signal RWG is supplied to the write address counter 143 via NAND circuits 145 and 147, and a read start signal is supplied to the read address counter 144 via NAND circuits 148 and 150. A read clock RC gated by a stop signal RRG and a horizontal synchronization signal is provided. The purpose of gating using the horizontal synchronizing signal is to form a period in which the horizontal synchronizing signal is inserted between each block, as is clear from the recording signal waveform in FIG. During reproduction, the write address counter 143 is supplied with a write clock WC gated by the write start/stop signal PWG and the composite synchronization signal PSYNC separated from the reproduction signal via NAND circuits 146 and 147, and the read address counter 144 A read clock RC gated by a read start/stop signal PRG is supplied via NAND circuits 149 and 150 to the read clock RC. Composite synchronization signal PSYNC
The reason for this is that there is no data between the blocks of data written to the RAM. The output WAO-WA9 of the write address counter 143 and the output RAO-RA9 of the read address counter 144 are supplied to the address selector 151.
O~WA9 is address code A. -A9 is supplied to address coaters 132 and 133, and at the time of reading, RAO-RA9 is supplied to address decoders 132 and 133 as address code ~A9. Therefore, the address selector 151 receives the address selection signal ADSL.
CT and ADSLCT are supplied. The write address counter 143 and the read address counter 144 are cleared by a standby signal STBY generated by the mode signal generator 47 described above. That is, the standby signal STBY is generated when the recording switch 46 is turned on and when the first vertical synchronizing signal PSVD is applied during reproduction, and the write address counter 143 and the read address counter 144 are cleared at each time. become. Furthermore, a memory device consisting of a RAM and a memory control circuit can be written and read independently.

This will be explained with reference to the time charts of FIGS. 12 and 13. FIG. 12 shows a time chart during recording, where the period TW of the write clock RWC is in the relationship (Tw>TR) with the period TR of the read clock RRC, and the time axis of the data is compressed. The figure shows a time chart during playback, and shows the write clock PWC.
This is a case where the period Tw of the read clock PRC has a relationship (Tw<TR) with the period TR of the read clock PRC, and the time axis is extended. However, the period Tw of the write clock PWC during playback
7 has a time axis variation, but the time axis variation is corrected by reading data with a read clock PRC having a constant period TR. The operation of the memory control circuit 32 and RAM l3l will be explained using the time charts shown in FIGS.
The data BR (FIG. 12A or FIG. 13A) is synchronized with WC) (FIG. 12B or FIG. 13B).

The write address is sequentially determined by address codes WAO-WA9 formed by the write address counter 143 as shown in FIG. 12C or FIG. 13C. A mark signal MARK (FIG. 12D or FIG. 13D) having a pulse width approximately half the period Tw is generated by the write clock WC. Also, the read clock RC (RRC or PRC
) (FIG. 12E or FIG. 13E), the address codes RAO to R formed by the read address counter 144
By A9, the read address is sequentially changed as shown in FIG. 12F or FIG. 13F.

The write/read control signal WV shown in FIG. 12G or FIG. 13G defines a write cycle Twc which is the sum of the address up time t$A1 address hold time THAl write enable pulse width Tpw determined by the specifications of the RAM 13l. Also, address selection signal ADSLCT
A write address code is supplied to the address decoders 132, 133 when (FIG. 12H or FIG. 13H) is "゜1゛", and a read address code is supplied to the address decoders 132, 133 when it is "゜゜0゛". , this period of ゜゜08 becomes the read cycle TRC.Then, the write/read control signal WR and the address selection signal ADSL
Data is written into the RAM 13l bit by bit by the CT, and data is read out from the RAM 13l bit by bit. Data is read into the output buffer register 137 in synchronization with the rise of the address selection signal ADSLCT, and therefore the output BRO is the 12th buffer register 137.
The period becomes irregular as shown in FIG. 1 or FIG. 13.
If left as is, subsequent data processing will be troublesome, so the data is supplied to the D flip-flop DF6, and the output data D of a constant period shown in FIG. 12J or FIG. 13J is obtained using the readout clock RC. Convert to . Write and read RAM131 in this way. Can be operated independently (asynchronously).

And start/stop signals RWG, RRG, PWG
By processing data in units of 1 field using PRG, if the accumulated time axis fluctuation exceeds the pre-estimated correction range +5, the RAM data will be deleted.
-Overflow or underflow occurs when the next data is written before data is read out or underflow is read out when the previous data is read before data is written to RAM, but no overflow or underflow occurs unless the correction range is exceeded. It is possible to compress and expand the time axis.

As is clear from FIG. 12 or 13, the write cycle or read cycle is determined as follows.

First, when the read clock RC comes while the mark signal MARK is "1", the write cycle starts with the write clock WC (read in this case), and then the clock RC starts the write cycle without immediately entering the read cycle. make concessions.

Next, when the read clock RC comes while the mark signal MARK is 0.degree., the effective read cycle starts from this point. In other words, in this case, the write cycle yields to the read cycle as much as necessary (maximum Tw).In this case, the write cycle Tv, is RA
The time necessary for the write operation of M to be performed reliably is the sum of the address setup time TSA1, the core address hold time THAl, and the write enable pulse width Tpw. Further, the read cycle is set to be longer than the time required for the read operation and less than 112 Tw. The write/read control signal W and address selection signal ADSLCT for performing such operations are generated by the memory control signal generation circuit 13.
Formed by 8.

FIG. 14 shows an example of the structure of the memory control signal generating circuit 138, where MM1 to MM5 each represent a monomulti, and the monomulti MM1 is triggered at the rising edge of the write clock WC to form a mark signal MARK. The monomulti MM3 is triggered by the fall of the output Q of the monomulti MM2 to define the writeable pulse width Tpw, and its output n is used as the signal WI. Mono multi MM4
defines address hold time THA. The mono-multi MM5 defines a read cycle TRC after the end of the write cycle Twc, and has a retriggerable configuration. Mono multi MM5 output 100 is signal ADS
The output Q becomes the signal ADSLCT.
15 and 16 are time charts of the above-mentioned control circuit. FIG. 15 shows the time of recording, and FIG. 16 shows the time of playback. The timing is right.

FIG. 15A or FIG. 16A is the write clock WC (RW).
C or PWC), FIG. 15C or FIG. 16C shows the read clock RC (RRC or PRC), and the monomultiple MMl is triggered by the write clock WC as shown in FIG. 15B or FIG. 16B. Mark signal MAR
K is formed. Since the control circuit shown in FIG. 14 has a loop configuration, first start from the monomulti MM3 to the control circuit shown in FIG.
It is assumed that the signal W shown in FIG. 6D is obtained. At this time, the output Q of the monomulti MM3 is as shown in Fig. 15 E or 16
As shown in FIG.
As shown in FIG. 15F or FIG. 16F, a pulse WEΔ like a differential pulse of the rising edge of the signal W appears at the output of the signal W. Since this pulse WEΔ and signal MARK are supplied to the NAND circuit 154, its output becomes as shown in FIG. 15G or FIG. Q
is as shown in FIG. 15H or FIG. 16H. The output Q of the monomulti MM4 is supplied to the OR circuit 155 as it is, and is also supplied to the OR circuit 155 via the integrating circuit and the inverter 156. As shown in the figure, a pulse MM4QΔ is obtained by differentiating the falling edge of the output Q of the monomulti 4.
appears. Further, the read clock RC and the signal MARK are supplied to a NAND circuit 157, and the output thereof is shown in FIG.
Or, as shown in FIG. 16J, when the read clock RC comes when the signal MARK is "0", a negative pulse is generated.
7 is supplied to the NAND circuit 158, and the output of NAND circuit 1
A pulse shown in FIG. 15 K or FIG. 16 K is generated from 58, and the monomulti MM 5 is triggered at the rising edge of this pulse. In this case, since the monomulti MM5 is capable of being retriggered, its output Q, that is, the signal ADS pressure T, and its output O, that is, the signal MH℃T are
This is shown in Figure 6 L and M. The signal ADS field T is supplied to the NAND circuit 159 together with the signal MARK, so that the output of the NAND circuit 159 is as shown in FIG. 15N or FIG. 16N, and the signal ADSLCT and the write clock WC (PWC or PWC) is supplied to the NAND circuit 160, and this output and the output of the NAND circuit 159 are supplied to the NAND circuit 161, and the monomulti MM2 is triggered at the falling edge of the output. By doing this, the write cycle is started by the signal MCT which is RHJ and the write clock WC at the beginning of the write cycle.

The output Q of monomulti MM2 is 0 in Fig. 15 or 0 in Fig. 16.
Since the mono-multiple MM3 is triggered at the falling edge, the write/read control signal WR shown in FIG. 15D or FIG. 16D is eventually formed.
As is clear from the above, according to the present invention, in both recording and reproduction, the count output of the counter that counts the horizontal synchronization signal HD (second reference signal) inserted for each block and the vertical synchronization The window signal WND is formed by triggering the flip-flop FFl with the signal D (first reference signal), and the start-stop signal is obtained from this signal WND, so the start-stop signal generator can be shared for recording and reproduction, and the Therefore, the configuration of the device can be simplified.

[Brief explanation of drawings]

Fig. 1 is a system diagram of a signal recording/reproducing apparatus using the PCM method to which the present invention can be applied, Fig. 2 is a diagram showing the recorded signal waveform, and Fig. 3 is a main part of a signal recording/reproducing apparatus considering dual use for recording and reproducing. Figures 4 and 5 are the mode signal generator system diagram and its time chart, Figure 6 is the clock pulse generator system diagram, and Figures 7, 8, and 9 are the start. A system diagram of the stop signal generator and its time chart. Figure 10 is a system diagram of the RAM and its peripheral circuits.
Figure 1 is a system diagram of the memory control circuit, Figures 12 and 13.
The figures are memory device time charts, Figures 14 and 15.
1 and 16 are a system diagram of the memory control signal generation circuit and its time chart. 1 is TR, 2 is VTR recording signal input terminal, 20 is V
TR reproduction signal output terminal; 31 is a RAM; 32 is a memory control circuit; 33 is a synchronizing signal generator; 34 is a clock pulse generator; 35 is a start/stop signal generator;
6 is a synchronous separation circuit, 37 is a serial/parallel converter, 46 is a recording switch, 47 is a mode signal generator, 109, 110, 1
11 is a counter, FF1 is a flip-flop, 143 is a write address counter, and 144 is a read address counter.

Claims (1)

[Claims] 1. Convert the analog signal into a serial format digital signal using the PCM method, compress the time axis of this digital signal using a memory device, form a data missing period at regular intervals, and use the first standard in this data missing period. At the same time as inserting the signal, a second reference signal is inserted for each predetermined unit of the digital signal to obtain a recording signal, this recording signal is recorded on a recording medium by a wideband signal recording and reproducing device, and is reproduced from this recording medium. In a signal recording and reproducing device using the PCM system, the time axis of the signal is expanded by a memory device to fill in the data missing period, and the output of the memory device is converted from analog to analog to obtain the analog signal. During recording, the digital signal is generated by counting outputs of the inserted first reference signal and second reference signal, and during reproduction, by counting outputs of the first reference signal and second reference signal that are separated from the reproduced signal. A start/stop device that forms a window signal that defines the length of the corresponding data within a certain period of time, and supplies this window signal to the control circuit of the memory device to control the start and stop of writing and reading of the memory device. A signal recording and reproducing device using a PCM method, characterized in that it generates a signal.