JPS6052622B2 - television receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides the ability to simultaneously display two images on the screen of one television receiver.
I'm going to blow out the images of the two channels.
1■ This is related to 111.

Examples thereof will be described below with reference to the accompanying drawings.

Before explaining the processing of audio signals, the processing of video signals will be explained first. Two channels A on the same blowing surface
, B is shown in FIG. 2. In other words, the B channel is approximately 1/1 vertically of the entire screen.
2. Blow out at the bottom right corner of the screen, which is 1/2 the width and 1/4 the area. The basic idea of this method is that every other horizontal scan of the B channel, samples are stored in the memory circuit corresponding to that scanning line every other picture element (sample points necessary to reproduce an image) for one horizontal scan. When the horizontal scanning of the A channel scans the part B in FIG. 2, the image of the B channel is stored by reading out the contents of the memory circuit at twice the writing speed. It is based on the principle that the signal is blown out into the area shown in FIG. 2B as an image compressed to about 1/2 in length and width. Figure 1 shows the specific configuration. 1 is an antenna, 2 and 6 are tuners that receive broadcasts on different channels A and B, respectively, 3 and 7 are video intermediate frequency amplification circuits, and 4 and 8 are video Detection circuit, 5 and 9 are video amplification circuits, 1
0 is a circuit that generates the vertical synchronizing signal VB and horizontal synchronizing signal HB of channel B, and 11 is a circuit that generates the vertical synchronizing signal VA and horizontal synchronizing signal HB of channel A.

12 is a flip-flop that inverts its state every time the horizontal synchronizing signal HB is generated and generates an output signal d; 13 is a flip-flop that inverts its state every time the horizontal synchronizing signal HB is generated, and generates an output signal d;
The signal selection circuit selects one of q, r, and s and generates an output at the output terminal 23'', and operates as shown in FIG.

Note that the mark in the middle of the figure may be optional. 14,1
7 is an RS flip-flop having a reset terminal and a set terminal, respectively, and generates outputs A and b.

15 and 16 are counters, and 18 is a gated oscillator that stops oscillation while the horizontal synchronizing signal HA is being generated, and makes the phase relationship of its output pulse with respect to the horizontal synchronizing signal H, equal in any horizontal scan. I can do it.

A gated oscillator 19 generates an output f and has a similar relationship to the horizontal synchronizing signal HB.

Reference numeral 20 denotes a control circuit including a memory circuit for writing and reading image information, and includes the circuits shown in FIGS. 5, 7, 8, and 9.

21 and 22 are AND gates.

The oscillation frequency of the gated oscillator 18 described above is 450fHCH2 when the number of picture elements per horizontal scan is 450, and the horizontal scanning frequency is FH, and the oscillation frequency of the gated oscillator 19 is 1/2 of that, 225fHC2.
H2].

The counter 15 is a 525/2 x 2 = 132 [bit] counter for the number of horizontal scans in one field, 525/2, and when 132 horizontal synchronizing signals HA are counted, the flip-flop 14 is activated. is set, and the output a becomes a high potential state. The counter 15 and the flip-flop 14 are . It is reset by the vertical synchronization signal VA. The counter 16 calculates 450/2=225 for 450 picture elements in one horizontal scanning question.
When the [bit] counter counts 225 output pulses from the gated oscillator 18, the flip-flop 17 is set and the output B. becomes a high potential state.
Counter 16 and flip-flop 17 are reset by horizontal synchronization signal HA. With this configuration, when sweeping the part B shown in Fig. 2, the output A
, b are in a high potential state, and the output of the oscillator 18 appears at the output e of the AND gate 22. Next, the operation of the embodiment configured as above will be explained.

The broadcast signal of channel A selected for reception by tuner 2 is applied to signal selection circuit 13 via circuits 3, 4, and 5 as video signal P shown in FIG. 4A. Also, the broadcast signal of channel B selected for reception by tuner 6 is transmitted to circuits 7, 8, 9.
The control circuit 20 outputs the video signal V shown in FIG.
added to. This control circuit 20 samples the video signal V of channel B as shown in the opening of FIG. 4, stores each sample value, and reads out the stored signal at twice the speed of sampling. Then, as shown in FIG. 4C, a video signal whose time axis is compressed to 112 is obtained. This video signal appears as Q, r, and s for each field. The signal selection circuit 13 appropriately selects and switches the signals P, q, r, and s, and as shown in FIG. appears at the output terminal 23. Next, the circuits included in the control circuit 20 will be explained.

FIG. 7 shows a ring counter in which the vertical synchronizing signal B is applied several times even from any state of each flip-flop FFl, FF2, FF3.
When FF3 is triggered, the outputs M1, M2, and M3 repeat the state shown in FIG. 11 every time the synchronization signal VB arrives. These outputs M1, M2, M3 are used as signals for selecting the write circuit. FIG. 8 is a circuit that obtains signals Nl, N2, N3 from the signals Ml, M2, M3 obtained by the circuit shown in FIG. 7, the signal a, and the synchronization signal Va. It is configured as. Nl, N2, N3 are signals for selecting the readout circuit and signals P, q, r, s by the signal selection circuit 13.
It is used as a signal to select either one. Further, in FIG. 9, either the output e of the oscillator 18 or the output f of the oscillator 19 is inputted to the signal Ml, M2, M3 via the AND gate 22.
, Nl, N2, and N3 to obtain a write clock or a read clock for each write/read circuit.

FIG. 5 shows an embodiment of a memory circuit included in the control circuit 20 and a circuit for writing and reading image information therein.

206 is a storage circuit, and 205 is a shift register.

502 and 503 are circuits having the same configuration as 501, and in contrast to Ml, Nl, and Ul for the circuit 501, the circuit 50
2,503 are M2, N2, U2, M3, N3, respectively.
Becomes U3. When (Ml, M2, M3) = (1, 0, 0), the circuit 501, (Ml, M2, M3) = (a),
1, 0), in the circuit 502, (Ml, M2, M3)
When =(0, 0, 1), writing is performed in the circuit 503, respectively. Also (Nl, N2, N3) = (1, 0,
0), the circuit 501 calculates (Nl, N2, N3)=(
0, 1, 0), the circuit 502 outputs (Nl, N2, N
3) When = (0, 0, 1), the circuit 503 is read. As can be seen from FIG. 8, it is half Ni and half Mi. The write and read operations of the circuit 501 will be described. M
When 1=1, AND gates 202 and 203 are open, and AND gates 202 and 204 are closed. Therefore, shift
In the register 205, the first stage flip-flop is set by the synchronizing signal ml, and the other flip-flops are reset. That is, the state becomes 10...0. This state is 010 due to the signal d.
・0,0010......Changes to 0. U1 is equal to the output f of the oscillator 19, which creates the write clocks φ1, φ2 to the storage circuit 206. d is the synchronization signal H
Since the shift register 205 is shifted every other horizontal scan of 8, information for every other horizontal scan is stored in each storage circuit. V is a video signal. When N1=1, AND gates 201 and 203 are closed, and AND gates 202 and 204 are open. At this time, shift register 2
05 is set to the state of 100...0 by 9, and 0100...0, by HA.
The state changes from 0010...0. U1 is equal to the output e of the AND gate 22, which creates the read clocks φ1, φ2 from the storage circuit 202. The read speed is equal to the oscillation frequency of the oscillator 18. Figure 3 shows the vertical synchronization signal of the A channel and the vertical synchronization signal of the B channel,
It shows the relationship between writing and reading image information on the B channel. In other words, the part numbered B1 is the circuit 501.
, that of B2 is connected to circuit 502, and that of B3 is connected to circuit 50.
3 and it will be read in the corresponding numbered part of the A channel. The dotted line in the figure means that on the right side, the horizontal sweep is performed in the part B of FIG. 2. FIG. 6 shows an embodiment of the memory circuit.

The shift signals φ1 and φ2 are composed of rectangular waves having mutually opposite phases. The voltages on the capacitors are Vl, 2, and V3. The sample value of the signal is UK. When the base of the transistor reaches the voltage U, the transistor starts conducting, and current flows from the capacitance immediately following it until the capacitance of the previous stage reaches U. The voltage of its own stage is momentarily 2U, and for its voltage force +Uk
The charge is transferred until . Therefore, the information contained in this stage is transmitted to the next stage. Note that G is a gate signal. In the above embodiment, the case where another channel is displayed in the lower right corner of the screen of the television receiver at 1/2 the size in the vertical and horizontal directions has been described, but by changing the count values of the counters 15 and 16,
Furthermore, by replacing the flip-flop 12 with a counter having an appropriate count value, its size can be changed in various ways.

The position to be displayed is also limited to the lower right corner, but may also be the upper right corner, the upper left corner, or the lower left corner. In the above embodiment, while the broadcast signal of channel A is received by the tuner 2 and displayed, the broadcast signal of channel B is received by the tuner 6, and the screen of this channel B is displayed in a small size. It would be very convenient if the display position of the screens of channels A and B could be switched using the configuration. That is, the circuit 10 separates the horizontal synchronization signal and vertical synchronization signal of each channel.
, 11, the signals of the two channels may be exchanged using a switch or the like. It is best to install the above switch at a position where the output of the amplifier circuit 5 and the output of the amplifier circuit 9 are exchanged. By doing this, you can immediately enlarge the screen of the channel that was displayed small, which is very convenient. It's practical. An example in which two video signals are displayed on the same picture tube has been described above.

An object of the present invention is to enable such a television receiver to simultaneously listen to audio signals of two different television signals without interfering with each other. An example of this will be explained below with reference to FIGS. 1 and 2. In Figure 1, 23,2
4, 25, 26, 27, 28, and 29 circuits were added.
In the figure, 23 and 24 are SIF detection circuits, the output of which is a low-level audio signal. 2J5 and 26 are output circuits for this audio signal, 27 is a speaker connected to the output circuit 25, 28 is an earphone connected to the output circuit 26, and 29 is for switching two different audio signals to the speaker 27 and the earphone 28. This is an interlocking switch for

By switching this switch 29, the detection circuit 2
3 to the speaker 27, the output of the detection circuit 24 to the earphone 28, the output of the detection circuit 23 to the earphone 28, and the output of the detection circuit 24 to the speaker 27.
It is possible to switch between different feeding modes.
Therefore, the user can simultaneously hear the audio of the television signal from the speaker 27 and the audio from the other television signal from the earphone 28. Next, the background of obtaining such two different audio signals simultaneously and switching between them will be explained. For example, a first television signal may be receiving a baseball program and a second television signal may be receiving a song program. At times like these, many people want to listen to songs and watch baseball.

However, in the past, if a baseball program was received on the screen marked with the letters RA in Figure 2, the audio output would be a commentary on baseball.
I can't hear the song at all. Therefore, it is possible to prepare two speakers, emit the audio signal of the first television signal from the first speaker, and emit the audio signal of the second television signal from the second speaker. However, since each audio signal enters the ear at the same time, there is a problem that they interfere with each other and make it difficult to hear. In such a case, one of the audio signals is transmitted to the speaker 2 as shown in FIG.
7, by configuring the other audio signal to be supplied to the earphone 28, the baseball program can be received in the part marked with letters RAJ in FIG. 2, and the song program can be heard from the speaker 27. The letters RB in the diagram. A song program is included in the J section. By receiving the information, you can listen to the commentary on the baseball program through the earphones 28. Of course, the reverse is true (receiving a baseball program in the part marked with the letters RA, receiving an explanation of the baseball program from the speaker 27, receiving a song program in the part marked with the letters 1B, and listening to the audio of the song program from the earphones 28). It is also possible to set the TV to a state of 1), allowing two different television signals to be enjoyed at the same time in the optimum state without interfering with each other, which has an extremely great practical effect. Although the explanation has been given of switching between two different audio signals at the low level audio signal, switching may be performed at the SIF signal or the amplified audio signal.

As is clear from the above embodiments, the television receiver according to the present invention stores the second television signal in a plurality of storage means, reads the stored signal at a higher speed than the writing speed, and compresses the second television signal in a time-secure manner. A second television signal is obtained, a part of the first television signal is deleted and inserted into the second television signal, and this composite signal is displayed.

Therefore, you can also watch other programs on the same screen.
Furthermore, it can be used as a monitor in a video tape recorder. In the present invention, the audio signals in the two television signals are arbitrarily switched so that one audio signal is supplied to the speaker and the other audio signal is supplied to the earphone, so that the audio signal is not displayed on the screen. There 2
You can listen to the audio from any one of the two video screens through the speaker, and at the same time listen to the audio from the other video screen through the earphones, allowing you to listen to the audio from both without any interference from each other. It is possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a television receiver according to an embodiment of the present invention, FIG. 2 is a diagram showing how images are projected onto a television picture tube, and FIG. 3 is a diagram showing how images are projected onto a television picture tube. A diagram showing the relationship between the vertical synchronization signal and B channel writing to the storage circuit and reading from it;
Fig. 4 is a diagram showing the relationship between the video signals of A channel and B channel, Fig. 5 is an explanatory diagram of a memory circuit and a circuit for writing to and reading from it, and Fig. 6 is an explanatory diagram of the operation of the memory circuit. , FIG. 7, FIG. 8, and FIG. 9 are circuit diagrams for generating signals to be supplied to the circuit in FIG. 5, respectively. FIG. 10 is a diagram explaining the operation of the signal selection circuit, and FIG. 11 is a diagram explaining the operation of the ring counter. It is. 2, 6... Tuner, 13... Signal selection circuit, 20
. . . Control circuit including a storage circuit for writing and reading image information, 23, 24 . . . SIF detection circuit, 29 .
Selector switch, 25... Output circuit, 27, 28...
Speaker/earphone.

Claims (1)

[Claims] 1 means for simultaneously receiving first and second different television signals; storage means capable of storing the second television signal; and means for writing the second television signal into the storage means. , means for reading from the storage means at a higher speed than the writing speed to take out a second television signal compressed in a time axis; and a part of the first television signal to be transmitted to the compressed second television signal. means for projecting the second television signal on a part of the video screen of the first television signal by exchanging the signal; and a first television signal for obtaining an audio signal of the first television signal. a second audio demodulation circuit for obtaining an audio signal of the second television signal;
A speaker, an earphone, and an audio signal of the first television signal and an audio signal of the second television signal are switched, and one of the audio signals is sent to the speaker and the other audio signal is sent to the earphone, respectively. What is claimed is: 1. A television receiver comprising: switching means for supplying the television;