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JPS6054787B2 - semiconductor equipment - Google Patents
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JPS6054787B2 - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS6054787B2
JPS6054787B2 JP9359578A JP9359578A JPS6054787B2 JP S6054787 B2 JPS6054787 B2 JP S6054787B2 JP 9359578 A JP9359578 A JP 9359578A JP 9359578 A JP9359578 A JP 9359578A JP S6054787 B2 JPS6054787 B2 JP S6054787B2
Authority
JP
Japan
Prior art keywords
semiconductor device
jig
mounting
printed board
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP9359578A
Other languages
Japanese (ja)
Other versions
JPS5521122A (en
Inventor
邦彦 生崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9359578A priority Critical patent/JPS6054787B2/en
Publication of JPS5521122A publication Critical patent/JPS5521122A/en
Publication of JPS6054787B2 publication Critical patent/JPS6054787B2/en
Expired legal-status Critical Current

Links

Description

【発明の詳細な説明】 本発明は実装ボード上に実装された半導体装置の交換を
容易とするために改良された半導体素子封止パッケージ
の構造に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved structure of a semiconductor element sealed package to facilitate replacement of a semiconductor device mounted on a mounting board.

半導体装置は高信頼度を要求される装置に実装される時
、実装状態での高温動作エージング等の初期不良品除去
の為のスクリーニングが実施される。
When a semiconductor device is mounted in a device that requires high reliability, screening is performed to eliminate initial defects such as high-temperature operation aging in the mounted state.

これまでは、スクリーニング工程で発生した不良品の実
装ボードからの離脱は半導体装置が実装ボード上にハン
ダ付等で固定されている時極めて困難さをともなつた。
このためソケットを介して実装プリント板に実装すると
いう不便さがあつた。第1図において実装ボード2上に
ハンダ3で固定された半導体装置1をボードから離脱さ
せる時、半導体装置底部とボード面とのすきまが極めて
小さいため、同図に示す様に下からハンダ付部を加熱し
半導体装置側面部を治工具4でおさえて実装面から引き
離す必要がある。
Until now, it has been extremely difficult to remove defective products generated during the screening process from the mounting board when the semiconductor device is fixed to the mounting board by soldering or the like.
For this reason, there was the inconvenience of mounting on a mounting printed board via a socket. When the semiconductor device 1 fixed on the mounting board 2 with solder 3 in FIG. 1 is removed from the board, the gap between the bottom of the semiconductor device and the board surface is extremely small, so the soldered portion is removed from below as shown in the figure. It is necessary to heat the side surface of the semiconductor device and hold the side surface of the semiconductor device with the jig 4 to separate it from the mounting surface.

治具によつて与えられる引き離すための力は半半導体装
置の側面と治具との摩擦力で発生する。
The separation force applied by the jig is generated by the frictional force between the side surface of the semi-semiconductor device and the jig.

このため半導体装置を実装面から引離す時に半導体装置
側面に大きな圧力をかける必要がある。半導体装置は通
常実装ボード上に高密度で実装されているので、半導体
装置に大きな圧力をかけられる様な治具を小さな寸法で
設計せねばならず、従来からの形状の封止パッケージを
はさんで離脱するための治具設計は困難であつた。本発
明は上記の如き欠点を解決するための新規な半導体素子
封止パッケージを提供するものである。
Therefore, when separating the semiconductor device from the mounting surface, it is necessary to apply a large amount of pressure to the side surface of the semiconductor device. Semiconductor devices are usually mounted at high density on mounting boards, so it is necessary to design a jig with small dimensions that can apply a large amount of pressure to the semiconductor device, and it is necessary to design a jig with a small size that can apply a large amount of pressure to the semiconductor device. It was difficult to design a jig for detachment. The present invention provides a novel semiconductor element encapsulation package to solve the above-mentioned drawbacks.

本発明は半導体素子封止パッケージの側面あるいは上面
あるいは底面に切込みあるいは突起部をもうけて半導体
装置の実装面からの離脱を容易とならしめる封止パッケ
ージ構造を特徴とする。
The present invention is characterized by a sealed package structure in which a cut or protrusion is provided on the side, top, or bottom surface of the semiconductor element sealed package to facilitate removal of the semiconductor device from the mounting surface.

第2図は本発明の一実施例を示すものである。半導体素
子封止パッケージ1の側面部に切込み部5をもうけて第
5図に示す様に半導体装置引離し川沿工具4の先端部8
が切込部5に容易に挿入で3きる構造となつている。こ
うする事により半導体装置の実装プリント板からの離脱
が、簡単な治工具で容易に実現できる。第5図の治具は
半導体装置離脱のための治具の一例であり、9は治具で
半導体装置をおさえるためのスプリングである。第3図
及び第4図は本発明に関連する参考例で、半導体装置と
実装プリント板の間に治具4の先端部8が挿入できる様
にするものである。第3図で、半導体装置のリード部A
の寸法を1?前後に設計する事により治工具4の先端部
8を実装プリント板と半導体装置底面の間に挿入できる
。第4図では半導体装置底面の一部に突起部をもうけて
、実装プリント板と半導体装置底面の間にスペースを獲
保する構造を示す。以上に述べた封止パッケージはセラ
ミックパッケージ、レジンモールドパッケージ等の製造
工程での設計寸法のわずかな設計変更で容易に実現でき
る。
FIG. 2 shows an embodiment of the present invention. A notch 5 is formed in the side surface of the semiconductor element sealed package 1, and the tip 8 of the semiconductor device separation tool 4 is formed as shown in FIG.
The structure is such that it can be easily inserted into the notch 5. In this way, the semiconductor device can be easily removed from the mounted printed board using simple jigs and tools. The jig shown in FIG. 5 is an example of a jig for removing the semiconductor device, and 9 is a spring for holding down the semiconductor device with the jig. 3 and 4 are reference examples related to the present invention, which allow the tip 8 of the jig 4 to be inserted between a semiconductor device and a mounting printed board. In FIG. 3, the lead part A of the semiconductor device
1? By designing the front and back, the tip 8 of the jig 4 can be inserted between the mounting printed board and the bottom of the semiconductor device. FIG. 4 shows a structure in which a projection is provided on a part of the bottom surface of the semiconductor device to secure a space between the mounting printed board and the bottom surface of the semiconductor device. The above-described sealed package can be easily realized by making slight changes in design dimensions during the manufacturing process of ceramic packages, resin mold packages, and the like.

以上述べた通り、本発明により、実装プリント板上の半
導体装置を実装プリント板から治具を用いて容易に離脱
させる事が出来る様になる。
As described above, according to the present invention, a semiconductor device on a mounted printed board can be easily removed from the mounted printed board using a jig.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来構造の半導体装置を実装プリント板から離
脱させるための概念図であり、第2図aは本発明の一実
施例に係る半導体装置用封止パッケージ構造の正面図で
あり第2図bはその側面図である。 第3図及び第4図は本発明に関連する参考例に係るパッ
ケージ構造を説明するための要部正面図であり、第5図
は第2図で示した構造の半導体装置を実装プリント板か
ら治工具を用いて取り外す際の概念図である。1・・・
・・・半導体装置、2・・・・・・実装ボード、3・・
・・・・半田、4・・・・・・引き離し用治工具、5・
・・・・・切込部(凹部)、6・・・・・・外部導出リ
ード、7・・・・・・突起部、8・・・・・・治工具の
先端部、9・・・・・・スプリング。
FIG. 1 is a conceptual diagram for detaching a conventionally structured semiconductor device from a mounted printed board, and FIG. 2a is a front view of a sealed package structure for a semiconductor device according to an embodiment of the present invention. Figure b is a side view thereof. 3 and 4 are main part front views for explaining a package structure according to a reference example related to the present invention, and FIG. 5 shows a semiconductor device having the structure shown in FIG. 2 from a mounted printed board. It is a conceptual diagram when removing using a jig. 1...
... Semiconductor device, 2... Mounting board, 3...
... Solder, 4... Separation jig, 5.
...Notch (recess), 6...External lead-out lead, 7...Protrusion, 8...Tip of jig, 9... ···spring.

Claims (1)

【特許請求の範囲】[Claims] 1 その内部に半導体素子を封止した実質的に箱型のパ
ッケージと、前記パッケージの対向する側面より突出し
、その少なくとも先端部が下方に曲げられた複数のリー
ドと、前記パッケージの対向する端面と下面の境界に設
けられた切込部よりなることを特徴とする半導体装置。
1. A substantially box-shaped package in which a semiconductor element is sealed; a plurality of leads protruding from opposing side surfaces of the package and having at least their tip portions bent downward; and opposing end surfaces of the package; A semiconductor device comprising a notch provided at a boundary on a lower surface.
JP9359578A 1978-08-02 1978-08-02 semiconductor equipment Expired JPS6054787B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9359578A JPS6054787B2 (en) 1978-08-02 1978-08-02 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9359578A JPS6054787B2 (en) 1978-08-02 1978-08-02 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS5521122A JPS5521122A (en) 1980-02-15
JPS6054787B2 true JPS6054787B2 (en) 1985-12-02

Family

ID=14086652

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9359578A Expired JPS6054787B2 (en) 1978-08-02 1978-08-02 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS6054787B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59217805A (en) * 1983-05-26 1984-12-08 日工株式会社 Production of asphalt composite material due to satellite system
JPS6078005A (en) * 1983-10-03 1985-05-02 三星産業株式会社 Asphalt melting method

Also Published As

Publication number Publication date
JPS5521122A (en) 1980-02-15

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