JPS6054794B2 - Optical semiconductor device - Google Patents
Optical semiconductor deviceInfo
- Publication number
- JPS6054794B2 JPS6054794B2 JP54141808A JP14180879A JPS6054794B2 JP S6054794 B2 JPS6054794 B2 JP S6054794B2 JP 54141808 A JP54141808 A JP 54141808A JP 14180879 A JP14180879 A JP 14180879A JP S6054794 B2 JPS6054794 B2 JP S6054794B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gold
- auzn
- optical semiconductor
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/83—Electrodes
- H10H20/831—Electrodes characterised by their shape
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/85—Packages
- H10H20/858—Means for heat extraction or cooling
- H10H20/8581—Means for heat extraction or cooling characterised by their material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/83—Electrodes
- H10H20/832—Electrodes characterised by their material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/85—Packages
- H10H20/858—Means for heat extraction or cooling
- H10H20/8585—Means for heat extraction or cooling being an interconnection
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
Landscapes
- Electrodes Of Semiconductors (AREA)
- Semiconductor Lasers (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Led Device Packages (AREA)
- Led Devices (AREA)
Description
【発明の詳細な説明】
本発明は、発光ダイオード（ＬＥＤ）半導体レーザ（Ｌ
Ｄ）など光半導体装置の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a light emitting diode (LED) semiconductor laser (L
D) and other improvements to optical semiconductor devices.
従来、例えばＬＥＤとして第１図に見られる構造のもが
知られている。図に於いて、１は例えばｎ型ＧａＡｌＡ
ｓからなる光取出し層、２は活性層、３はクラッド層、
４は金亜鉛（ＡｕＺｎ）層、５は二酸化シリコン（Ｓｉ
Ｏ０）絶縁層、６はクロム層（Ｃｒ）層、７は金（Ａｕ
）層、８は金ゲルマニウム・ニッケル（ＡｕＧｅ−Ｎｉ
）或いは金ゲルマニウム・金からなる電極、９は金のヒ
ート・ジンクをそれぞれ示す。このＬＥＤを製作するに
は、単結晶基板（図示せず）上に光取出し層１を厚さ４
０〜５０〔μｍ〕程度エピタキシャル成長させ、次いで
、厚さ例えば１〔μｍ〕程度の活性層２、厚さ例えば２
〔Ｐｍ〕程度のクラッド層３を順次成長させ、次いで、
ＡｕＺｎ層４を厚さ例えば４０００〔Ａ〕程度に形−成
してから例えば直径３０〜３５〔μｍ〕程度の円形にパ
ターニングし、次いで、スパッタリング法に依りＳｉＯ
２絶縁層５を厚さ例えば６０００〔Ａ）程度に形成して
からパターニングを行つてコンタクト窓を形成してその
窓内にＡｕＺｎ層４を露出させ、次いで、厚さ例えば５
００〔Ａ）のＣｒ層６、厚さ例えば２５００〔八〕のＡ
ｕ層７を形成する。Conventionally, for example, an LED having the structure shown in FIG. 1 has been known. In the figure, 1 is, for example, n-type GaAlA
A light extraction layer consisting of s, 2 an active layer, 3 a cladding layer,
4 is a gold zinc (AuZn) layer, 5 is a silicon dioxide (Si
O0) insulating layer, 6 chromium layer (Cr) layer, 7 gold (Au)
) layer, 8 is gold germanium nickel (AuGe-Ni
) or an electrode made of gold germanium/gold, and 9 indicates a heat zinc of gold. To manufacture this LED, a light extraction layer 1 is formed on a single crystal substrate (not shown) to a thickness of 4 mm.
The active layer 2 is epitaxially grown to a thickness of about 0 to 50 [μm], and then the active layer 2 is grown to a thickness of, for example, about 1 [μm], and the active layer 2 is grown to a thickness of, for example, 2 [μm].
A cladding layer 3 of about [Pm] is grown sequentially, and then
After forming the AuZn layer 4 to a thickness of, for example, about 4000 [A], it is patterned into a circular shape with a diameter of about 30 to 35 [μm], and then SiO is formed by sputtering.
2 insulating layer 5 is formed to a thickness of, for example, 6000 [A], and then patterned to form a contact window to expose the AuZn layer 4 within the window.
00 [A) Cr layer 6, thickness for example 2500 [8] A
A u layer 7 is formed.
次いでＡｕ層７側に厚さ例えば２０〔μｍ〕の金ヒート
・ジンク９を固着する。しかる後、単結晶基板を光取出
し層１から除去し、露出された光取出し層１の面にＡｕ
Ｇｅ−Ｎｉ（或いはＡｕＧｅ−Ａｕ）層を形成し、それ
をパターニングして電極８を形成する。このＬＥＤに於
いて、絶縁層５を形成したのはノ電流狭窄を行なつて微
小な発光領域を生成させる為である。この微小な発光領
域はＬＥＤでは伝送路である光ファイバとの結合、ＬＤ
では発振特性の面て好ましい影響をもたらすものである
。さて、このＬＥＤにはいくつかの欠点がある。即ち、
ＡｕＺｎ層４はＧａＡ１Ａｓ結晶との抵抗接触性が良好
である為に用いているのであるが、Ｓｉ０。との密着性
は悪い。またＳｉ０。絶縁層５の熱伝導率が小さい為、
それを設けることに依り結晶に於いて発生する熱をヒー
ト・ジンク９に伝達するバスが５〜７〔割〕程度も狭く
なつている。更にまた、ＳｉＯ。絶縁層５とＡｕ層７と
の密着性の悪さを補償する為に介挿したＣｒ層６は、合
金化やボンデイグなどの熱処理時にＡｕと反応し、Ｇａ
Ａ１Ａｓ結晶界面でのコンタクト抵抗を大にすることが
確認されている。このような材質的な面に基因する欠点
の他に、ＡｕＺｎ層４とＳｉＯ２絶縁層５とをパターニ
ングするので、フォト・リングラフィ工程が２回必要で
ある。本発明は、良好なオーミック・コンタクトが採れ
、電極各層の密着強度も充分であるＬＥＤｌ山などの光
半導体装置を提供するものであり、以下これを詳細に説
明する。Next, gold heat zinc 9 having a thickness of, for example, 20 [μm] is fixed to the Au layer 7 side. After that, the single crystal substrate is removed from the light extraction layer 1, and Au is applied to the exposed surface of the light extraction layer 1.
A Ge-Ni (or AuGe-Au) layer is formed and patterned to form the electrode 8. In this LED, the reason why the insulating layer 5 is formed is to perform current confinement and generate a minute light emitting region. This minute light emitting area is connected to the optical fiber that is the transmission path in the LED, and the LD
This has a favorable effect on the oscillation characteristics. Now, this LED has some drawbacks. That is,
The AuZn layer 4 is used because it has good resistance contact with the GaAlAs crystal, but the AuZn layer 4 is made of Si0. Adhesion is poor. Also Si0. Since the thermal conductivity of the insulating layer 5 is low,
By providing this, the bus for transmitting the heat generated in the crystal to the heat zinc 9 becomes narrower by about 50 to 70%. Furthermore, SiO. The Cr layer 6 inserted to compensate for poor adhesion between the insulating layer 5 and the Au layer 7 reacts with Au during heat treatment such as alloying and bonding, and Ga
It has been confirmed that this increases the contact resistance at the A1As crystal interface. In addition to the drawbacks caused by the material, two photophosphorography steps are required to pattern the AuZn layer 4 and the SiO2 insulating layer 5. The present invention provides an optical semiconductor device, such as an LED stack, which has good ohmic contact and sufficient adhesion strength between electrode layers, and will be described in detail below.
第２図は本発明一実施例の要部側断面図であり、第１図
に関して説明した部分と同部分は同記号で指示してある
。FIG. 2 is a side cross-sectional view of a main part of an embodiment of the present invention, and the same parts as those explained in connection with FIG. 1 are indicated by the same symbols.
本実施例が第１図従来例と相違する点は、クラッド層３
上にＡｕＺｎ層４を形成することなくＳｉＯ２絶縁層５
を形成し、その上にＣｒ層６、Ａｕ層７を形成し、そこ
で各層を貫通する電極コンタクト窓を設け、その後で全
面にＡｕＺｎ層４を形成したとである。The difference between this embodiment and the conventional example shown in FIG. 1 is that the cladding layer 3
SiO2 insulating layer 5 without forming AuZn layer 4 on top
, a Cr layer 6 and an Au layer 7 were formed thereon, an electrode contact window was provided that penetrated each layer, and then an AuZn layer 4 was formed on the entire surface.
尚、このときＡｕＺｎ層４の厚さは〜９０００〔Ａ〕程
度である。以上の説明で判るように、本発明に依れば、
電極のコンタクト領域が全てＡｕＺｎで形成されている
のでコンタクト抵抗は充分に低く、密着強度は高い。Note that the thickness of the AuZn layer 4 at this time is about 9000 [A]. As can be seen from the above explanation, according to the present invention,
Since the contact regions of the electrodes are all made of AuZn, the contact resistance is sufficiently low and the adhesion strength is high.
また、熱処理時にＣｒとＡｕとが反応したとしても、コ
ンタクト領域には無関係であり、従つて、コンタクト領
域に於ける電流分布は均一である。更にまた、各層間の
密着強度は充分に高く、そして、電極を形成するのに適
用されてフォト・リングラフィの工程は僅か１回である
からその実施は容易である。Further, even if Cr and Au react during heat treatment, it has no relation to the contact region, and therefore the current distribution in the contact region is uniform. Furthermore, the adhesion strength between each layer is sufficiently high, and the photolithography process used to form the electrodes is performed only once, making it easy to implement.
第１図は従来例の要部側断面図、第２図は本発明一実施
例の要部側断面図である。
図に於いて、１は光取出し層、２は活性層、３はクラッ
ド層、４はＡｕＺｎ層、５は絶縁層、６はＣｒ層、７は
Ａｕ層、８は電極、９はヒート・ジンクである。FIG. 1 is a sectional side view of a main part of a conventional example, and FIG. 2 is a sectional side view of a main part of an embodiment of the present invention. In the figure, 1 is a light extraction layer, 2 is an active layer, 3 is a cladding layer, 4 is an AuZn layer, 5 is an insulating layer, 6 is a Cr layer, 7 is an Au layer, 8 is an electrode, and 9 is a heat zinc layer. It is.
Claims (1)
それ等各層を貫通する電極コンタクト窓を介して前記結
晶層に到達している金・亜鉛層、該金・亜鉛層に固着さ
れたヒート・シンクを備えてなることを特徴とする光半
導体装置。1 Insulating layer, chromium layer, and gold layer formed on the crystal layer,
An optical semiconductor device comprising: a gold/zinc layer reaching the crystal layer through an electrode contact window penetrating each layer; and a heat sink fixed to the gold/zinc layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54141808A JPS6054794B2 (en) | 1979-11-01 | 1979-11-01 | Optical semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54141808A JPS6054794B2 (en) | 1979-11-01 | 1979-11-01 | Optical semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5666079A JPS5666079A (en) | 1981-06-04 |
| JPS6054794B2 true JPS6054794B2 (en) | 1985-12-02 |
Family
ID=15300600
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54141808A Expired JPS6054794B2 (en) | 1979-11-01 | 1979-11-01 | Optical semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6054794B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58147188A (en) * | 1982-02-26 | 1983-09-01 | Fujitsu Ltd | Semiconductor laser device |
| GB2371404B (en) * | 2001-01-23 | 2003-07-09 | Univ Glasgow | Improvements in or relating to optical devices |
| CN102412361B (en) * | 2010-09-21 | 2016-06-08 | 佳胜科技股份有限公司 | Laminated heat dissipation substrate and electronic assembly structure using the laminated heat dissipation substrate |
-
1979
- 1979-11-01 JP JP54141808A patent/JPS6054794B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5666079A (en) | 1981-06-04 |
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