JPS6055853B2 - History memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for storing the history of various internal state signals of an electronic computer, and is capable of recording analog transient phenomena as required.

Modern computers have become faster and more densely packed with elements, making it difficult to investigate faults, and it has become impossible to ignore the effects of circuit output waveform distortion and noise.

Therefore, it is desirable to be able to not only store the status signals at each point in synchronization with the system clock, but also to store transient phenomena before and after the system clock at a specific point.
However, connecting a special waveform recording device or analog measuring instrument such as a memory scope for this purpose is undesirable in terms of cost and computer operation. The present invention aims to solve these problems, and will be explained in detail below with reference to the drawings. FIG. 1 is a circuit diagram of one embodiment of the present invention, R1 to R4 are signal holding circuits (registers), G1 to G8
is a 2-input NOR gate, G9 is an inverter, D1 to D3
are delay circuits connected in series, and M is a memory.

Gates G1 and G2 constitute an input switching circuit to register R1, gates G3 and G4 constitute an input switching circuit to register R2, and so on. Switching signal SEL is logic “
When the logic is 'o', the gates G1, G3, G5 and G7 are selected, and when the logic is '1', the gates G2, G4 and G6 are selected.
, G8 are selected. Input signals WD1 to WD4 are connected to gates G2, G4, G6, and G8, respectively, and input signal WDO and outputs of delay circuits D1 to D3 are connected to gates G1, G3, G5, and G7, respectively. Input gate signal W
D0 to WD4 are internal state signals of the computer, and specifically may be various gate signals or control signals, or may be the contents of a register each having a plurality of bits. In the latter case, Regis gates R1 to R4 and gates G1 to G8
It goes without saying that each bit must exist for a plurality of bits. Furthermore, WDO may be a signal different from WDl to WD4, or may be one selected from WDl to WD4. As is clear from the figure, when the switching signal SEL is at logic "0", the transient phenomenon of the input signal WDO is stored in each register R1 to R4 in time series.

Also, when SEL is ゜゜1゛, WDl to WD4 are each R.
1 to R4 are stored in parallel. If you want to record faster transient phenomena, you can increase the number of delay circuits and registers and shorten the delay time. Incidentally, when history storage for a plurality of past clocks is required, the contents of the registers R1 to R4 may be further stored in the memory M. FIG. 2 is a circuit diagram of another embodiment of the present invention, in which the same numbers as in FIG. 1 indicate the same components.

Further, L1 to L4 are latch circuits. In this embodiment, the input signal WDO is connected to the gates Gll, Gl3, Gl5, Gl7.
Commonly connected to. On the other hand, the set clock to the latch circuit is connected to one end of a delay circuit connected in series, and a slightly delayed set clock is applied to each of the latch circuits L1 to L4. Therefore, when SEL is logical ゛゜0゛, W
The DO transient phenomenon is latched in each latch L1 to L4 in chronological order. The contents of each latch are stored in memory M via registers R1 to R4 at appropriate timing. Note that the holding means that operates in synchronization with the system clock is called a register, and the holding means that operates asynchronously is called a latch, but it is also possible to use both. Also, SEL is logic “゜1
In this case, WDl to WD4 are stored in registers R1 to R and also to memory M via latches L1 to L4, respectively, but generally when storing the history of the states of multiple observation points, the values of each point at the same time are stored. It is necessary to compare the states, and for this purpose it is rather undesirable that the set timings of the latches L1 to L4 are shifted.

``Therefore, when SEL is logic ``1'', gate G9
It is desirable that the input and output of all the latches L1 to L4 be passed through by the output of the latches L1 to L4. As described above, the present invention provides a switching circuit on the input side of the conventional signal holding means, and utilizes a series-connected delay circuit to control predetermined data W.
By sequentially delaying the DO or the set clock to the holding means and holding them, detailed history storage can be performed at low cost.

It should be noted that the delay circuits D1 to D4 are not limited to those in which individual delay elements are literally connected in series, but also include ones that utilize the center tap of a single delay line.

[Brief explanation of the drawing]

FIG. 1 shows a circuit diagram of one embodiment of the invention, and FIG. 2 shows a circuit diagram of another embodiment of the invention.

Claims (1)

[Claims] 1. A history storage circuit for internal state signals of a computer, comprising a plurality of signal holding circuits, a switching circuit provided corresponding to each signal holding circuit, and a plurality of delay circuits connected in series,
A plurality of status signals are respectively connected to one input of each of the switching circuits, a predetermined status signal is connected to one end of the plurality of series-connected delay circuits, and each connection point of the plurality of delay circuits is connected to one of the inputs of each of the switching circuits. A history storage circuit, characterized in that the circuit is connected to the other input of the switching circuit. 2. A history storage circuit for internal state signals of a computer, comprising a plurality of signal holding circuits, a switching circuit provided corresponding to each signal holding circuit, and a plurality of delay circuits connected in series,
A set clock signal is connected to one end of the plural delay circuits connected in series, and each connection point of the plural delay circuits is connected to a set clock signal input of the signal holding circuit, and a plurality of status signals are connected to each of the switching circuits. A history storage circuit characterized in that the switching circuits are connected to one input of each of the switching circuits, and a predetermined status signal is commonly connected to the other input of each of the switching circuits.