JPS6056310B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a CMIS-IC that prevents the occurrence of a thyristor effect.

CMIS-ICs (integrated circuits made of complementary metal-insulator semiconductor elements), especially CMIS inverters as shown in FIG. 1, are becoming widely used in logic circuits and the like. FIG. 2 shows an equivalent circuit of this CMIS inverter, and as shown in these figures, this inverter consists of a P-channel field effect transistor (FE) formed on an N-type semiconductor substrate 1.
T) Q, and an N-channel FETQ formed in the P-type well 2 made in the substrate 1. are connected in series (of course, the reverse is also possible for P and N conduction types), and the gate electrodes G, , G are connected in series. are commonly connected to the input terminal V, and the mutually connected drain electrodes Dp and DN are the output terminal V. Connect to FETQ,,Q.
Source electrodes 5, SN are connected to power supply terminals VDD, V, , respectively. In addition, in this CMIS inverter, a protective diode D is installed to prevent dielectric breakdown of the insulating film, usually an oxide film, between the gate electrode and the substrate when an excessively positive or negative voltage is applied to the gate electrode. ,D
2 is connected between the input terminal V and the power supply terminal VDD, V,. GR is P1 formed at the periphery of P-type well 2.
It functions as a guard link in the base area. Protection diode D,,D.

The action of is as follows. If the input voltage V1 now applied to the human power terminal (for simplicity, the same sign is used for each terminal voltage) becomes excessive and becomes greater than the diode forward voltage (approximately 7 V) than the power supply terminal VDD. Diode D conducts and clamps input terminal Vi to power supply terminal VDD. As a result, the potential of the input terminal is limited and does not become excessive, and dielectric breakdown of the oxide film between the gate electrode of P-channel FET Q1 and the semiconductor substrate can be avoided. Conversely, when the voltage at the input terminal Vi falls below the power supply Vss by more than the diode forward voltage, the diode D2 becomes conductive.
Clamp the input terminal Vi to the power supply terminal ■Ss. As a result, even if the input terminal swings significantly negative, the N-channel FE
The gate oxidation of TQ2 is protected. These protection diodes are used not only when the input terminal i swings significantly positive or negative due to the signal voltage, but also when an excessive positive or negative voltage is electrostatically input during an idling state where no voltage is applied to each terminal. When the voltage is applied to the terminal (i), etc., the gate oxide film is similarly rendered conductive and protected.

The diodes Dl and D2 are constructed by forming P+ and N+ type regions 6 and 4 in the N1 type substrate 1 and the P- well 2, and connecting these to the input terminal ■l, as shown in Fig. 1. If D2 is formed in the P-type well 2, the following problem will occur.

That is, when the input voltage Vl drops below 5-0.7V, the diode D2 turns on, and the P to which the power supply terminal Vss is connected
N+ type region 4 forming diode D2 from + type region 3
A stream 1B1 flows through the P1 type well 2. This current 1B1 becomes the base current of the NPN transistor constituted by the N+ type region 4 of the diode D2, the P1 type well 2, and the N1 type substrate 1, and as a result, the collector current 1C1 flows from the N+ type region 5 for substrate contact. It starts to flow. This current 1
Since C1 flows through the substrate 1, which has a low impurity concentration and relatively high resistance, a potential difference is generated in the substrate, and the P+ of FET Ql
The type source region Sp becomes more positive than the surrounding substrate potential,
This region S2, where the current becomes higher than the diode forward current, turns on the diode formed by the substrate 1, and a current 1B2 flows out from the region Sp. This is a P+ type source region Sp,
．． Lateful N composed of an N-type substrate 1 and a P-type well 2
It becomes the base current of the PN transistor, and the P+ source region S
The collector current 1 of this Ladera PNP transistor from p
C2 also flows out, and eventually a large short-circuit current flows from the power supply terminal VDD to the power supply terminal v through the substrate 1 and the P1 type well 2.
will flow. FIG. 4 is a circuit diagram explaining the above operation, where T1 is the above-mentioned NPN transistor, T2 is the above-mentioned lateral PNP transistor, and r is the resistance of the substrate 1.

This circuit is nothing but an equivalent circuit of a thyristor (SCR).Therefore, in a CMIS inverter with the structure shown in Figure 1, when the input voltage Vi falls below ■Ss-0.7V, the SCR
It can be seen that there is a risk of destruction due to the effect. The present invention is an attempt to improve the above points, and is characterized by forming wells of opposite conductivity type in a semiconductor substrate of one conductivity type, and forming P-channels in these substrates and wells. In a CMIS type semiconductor device, in which N-channel and N-channel field effect transistors are formed, these transistors are connected in series, and protection diodes are inserted between the source regions and gate electrodes of both transistors. A contact region is provided close to the well and directly connected to a power supply line, and the contact region is located between the transistor formed on the substrate and the well, so that parasitic transistor action within the well is prevented. The current is supplied from the contact region.

Next, this will be explained in detail with reference to the drawings. Referring again to FIG. 1, the SCR effect is caused firstly by the flow of the base current 1B1, and secondly by This is due to the current 182 flowing.

Therefore, by taking measures to prevent these base currents from flowing, it is possible to prevent the SCR effect from occurring. The former has been proposed separately by the present inventor, and therefore the present invention proposes the latter. Source region S of transistor Q1
The base current B2 flows out from p to the substrate 1 because the collector current 101 flows toward the well 2 from the N+ type contact region 5, which is on the opposite side of the well 2 when viewed from the region S, as described above. This current flows through the N-type substrate 1.
This is caused by a voltage drop occurring, the source region Sp to which the power supply voltage VDD is applied has a more positive potential than the substrate 1, and the diodes constituted by the source region Sp and the substrate 1 are sequentially biased g. Here, as shown by the dotted line 5'' in FIG. 1, the contact region 5 of the substrate 1 is provided close to the well 2, so that the contact region 5'' is between the transistor Q1 formed on the substrate 1 and the well 2. Even if the collector current 101 flows from the contact region 5'' for the above-mentioned reason, the current does not pass through the substrate 1 in the area where the transistor Q1 is formed, so no voltage drop occurs in the substrate area, and therefore the transistor The base current 1B2 does not flow out from the source region Sp of Q1. In the well 2, a base current 1B1 and a collector current 101 flow in the transistor T1, which is made up of the region 4 that constitutes one side of the protection diode D2, the well 2, and the substrate 1, but these currents are changed to the current ■DO, due to the thyristor effect. ■
, s are much weaker than the current 102 that short-circuits them, and will not destroy the CMIS inverter. Figure 3 shows an application example, in which a Schottky barrier diode or germanium diode D with a smaller forward voltage drop than the diode D2 is connected in parallel with the protection diode D2 between the gate electrode power supply terminals of the CMIS inverter.
A Schottky barrier diode or germanium diode D4 is also connected between the power supply terminals ■, and the output terminal VO, and a negative feedback resistor (approximately 1KΩ) R is connected between the gate electrode and the input terminal Vi. is inserted.

These diodes D3 and D4 can be easily formed at the same time by contacting a region with a relatively low impurity concentration when aluminum is vapor-deposited and electrode wiring is performed, and the resistor R is also formed at an appropriate place on the substrate 1 as is well known. It can be easily constructed by diffusing impurities into the By doing so, the occurrence of the SCR effect can be more reliably prevented for the following reasons. That is, when diode D3 is present, the forward voltage drop of normal PN junction diode D2 is about 0.7V,
The forward voltage drop of Schottky barrier diode D3 is 0.
．． Since it is about 4V, the input voltage becomes more negative than the power supply voltage ■Ss, and a current flows through the path ■s-D3-R-Vj.
The current does not pass through diode D2. This is Figure 1. In other words, this means that the base current 1B1 does not flow, and in terms of the equivalent circuit shown in FIG. 4, the transistor T1 is not formed. The occurrence of thyristor effects is thus prevented. As is clear from the circuit of FIG. 1, the base current 1B1 is caused by an abnormal drop in the output voltage VO, which causes the power supply voltage V! ，
There is a possibility that the flow will flow along the 3-2-DN route even when the number is below S.

Although such a situation does not normally occur, it occurs when the input voltage Vi is largely dragged toward the input voltage Vi side due to parasitic capacitance or the like. Even in such a case, if there is a Schottky barrier diode D4, the output terminal VO will be clamped to the power supply terminal V9 with a difference of 0.4V, so the base current 1B1 will flow through the 3-2-DN path. This prevents the SCR effect from occurring. Furthermore, if a negative feedback resistor R is inserted on the input side, this has the effect of limiting the base current by 1B1, as is clear from the equivalent circuit in Figure 4, and the transistor T1
prevent the generation of

When these measures, namely changing the position of the contact region 5, connecting the diodes D3 and D4, and inserting the resistor R, are used together,
The effect becomes even more noticeable. As described above in detail, according to the present invention, the occurrence of the thyristor effect in the CMIS-1C can be prevented by relatively simple means, and the effect in terms of implementation is great.

[Brief explanation of the drawing]

Figure 1 is a sectional view showing an embodiment of the present invention, Figure 2 is a circuit diagram of a conventional CMIS inverter, Figure 3 is a circuit diagram explaining an application example of the present invention, Figure 4 is a circuit explaining the SCR effect. It is a diagram. In the drawing, 1 is a semiconductor substrate, 2 is a well, Ql and Q2 are P-channel FETs, and N-channel FETs 15 and 5'' are contact regions to the substrate.

Claims (1)

[Claims] 1. Create a well of an opposite conductivity type in a semiconductor substrate of one conductivity type, form P-channel and N-channel field effect transistors in these substrates and wells, connect these transistors in series, and connect the sources of both transistors. In a CMIS type semiconductor device in which a protection diode is inserted between each region and a gate electrode, a contact region for the substrate is provided close to the well and directly connected to a power supply line, and the transistor formed on the substrate A semiconductor device characterized in that the contact region is located between the well and a current flowing into the well by a parasitic transistor action from the contact region.