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JPS6057220B2 - semiconductor equipment - Google Patents
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JPS6057220B2 - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS6057220B2
JPS6057220B2 JP55185920A JP18592080A JPS6057220B2 JP S6057220 B2 JPS6057220 B2 JP S6057220B2 JP 55185920 A JP55185920 A JP 55185920A JP 18592080 A JP18592080 A JP 18592080A JP S6057220 B2 JPS6057220 B2 JP S6057220B2
Authority
JP
Japan
Prior art keywords
gold
layer
lead frame
semiconductor element
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55185920A
Other languages
Japanese (ja)
Other versions
JPS57109351A (en
Inventor
欣男 伊藤
三男 小林
俊夫 鉄矢
修 薄田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP55185920A priority Critical patent/JPS6057220B2/en
Publication of JPS57109351A publication Critical patent/JPS57109351A/en
Publication of JPS6057220B2 publication Critical patent/JPS6057220B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • H10W72/07331Connecting techniques
    • H10W72/07336Soldering or alloying
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07551Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • H10W72/351Materials of die-attach connectors
    • H10W72/352Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5449Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/59Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/951Materials of bond pads
    • H10W72/952Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00Subject matter not provided for in other groups of this subclass

Landscapes

  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To improve bonding performance and reliability and to contrive to attain low cost by a method wherein in a semiconductor device on which a semiconductor element is mounted, a gold or gold alloy wire is directly bonded to the base of a substrate for element arrangement. CONSTITUTION:A semiconductor element 104 is mounted by pressure exerted through pressing on an island region 102 of a lead frame 101 composed of a single element of copper or copper alloy. On the upper surface of the semiconductor element 104, Al electrodes 110a, 110b are provided. The end of a gold or gold alloy wire 111a, 111b is bonded to this Al electrode 110a. Another end is directly bonded to lead regions 103a, 103b by full solid solution of Au-Cu. By this method bonding performance is improved.

Description

【発明の詳細な説明】 本発明は半導体装置に関し、特に半導体素子がマウント
され、かつ該素子の電極に接続したワイヤがボンディン
グされる素子配設基材を改良した半導体装置に係る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an improved element mounting base material on which a semiconductor element is mounted and wires connected to electrodes of the element are bonded.

一般に、半導体装置は第1図及び第2図に示す構造のも
のが知られている。
Generally, semiconductor devices having structures shown in FIGS. 1 and 2 are known.

即ち、第1図はシリコン半導体素子(例えばバイポーラ
半導体素子)を素子配設基材(例、えばリードフレーム
)にマウントし、さらにワイヤボンディングした状態を
示す斜視図、第2図は樹脂封止、カッティング加工後の
状態を示す断面図で、図中の1は半導体素子がマウント
されるアイランド部2及びワイヤがボンディングされる
リード部3a、3bを有するリードフレームである。こ
のリードフレーム1のアイランド部2、リード部3a、
3bのボンディング部周囲には銀層4が被覆されている
。また、前記アイランド部2には上面にベース、エミッ
タのN電極5a、5bを有するシリコン半導体素子6が
金を主成分とする層7を介してマウントされている。こ
の半導体素子6のAl電極5a、5bには夫々金ワイヤ
Ba、8bが接続され、かつこれら金ワイヤBa、8b
の他端はベース、エミッタの電極として桟能する内部リ
ード3a、3bに・夫々ポストボンディングされている
。更に図中の9は半導体素子6を含むアイランド部2及
びりード部3a、3bの金ワイヤBa、8b接続部付近
を覆う樹脂封止層である。なお、樹脂封止層9から露出
したリード部3a、3bは半田層10が被フ覆されてい
る。ところで、上述した半導体装置において半導体素子
6上面のN電極5a、5bに一端を接続した金ワイヤ8
a,8bをリードフレーム1のリード部3a,3bに接
続するには、従来、該リード部3a,3bに厚さ2〜1
0μmの銀層4をメッキ等により被覆し、この銀層4部
分に金ワイヤ8a,8bを空気中又はN2中で300℃
程度に加熱してポストボンディングする方法が行なわれ
ている。
That is, FIG. 1 is a perspective view showing a state in which a silicon semiconductor element (for example, a bipolar semiconductor element) is mounted on an element mounting base material (for example, a lead frame) and further wire-bonded, and FIG. This is a cross-sectional view showing the state after cutting, and numeral 1 in the figure is a lead frame having an island portion 2 on which a semiconductor element is mounted and lead portions 3a and 3b to which wires are bonded. The island portion 2 of this lead frame 1, the lead portion 3a,
A silver layer 4 is coated around the bonding portion 3b. Further, a silicon semiconductor element 6 having base and emitter N electrodes 5a and 5b on the upper surface is mounted on the island portion 2 via a layer 7 mainly composed of gold. Gold wires Ba, 8b are connected to the Al electrodes 5a, 5b of this semiconductor element 6, respectively, and these gold wires Ba, 8b
The other ends are post-bonded to internal leads 3a and 3b which function as base and emitter electrodes, respectively. Further, numeral 9 in the figure is a resin sealing layer that covers the island portion 2 including the semiconductor element 6 and the vicinity of the connection portions of the gold wires Ba and 8b of the lead portions 3a and 3b. Note that the lead portions 3a and 3b exposed from the resin sealing layer 9 are covered with a solder layer 10. By the way, in the semiconductor device described above, the gold wire 8 whose one end is connected to the N electrodes 5a and 5b on the upper surface of the semiconductor element 6 is
a, 8b to the lead portions 3a, 3b of the lead frame 1, conventionally, the lead portions 3a, 3b have a thickness of 2 to 1 mm.
A 0 μm silver layer 4 is coated by plating or the like, and gold wires 8a and 8b are attached to the silver layer 4 at 300°C in air or N2.
A method of post-bonding by heating to a certain degree is used.

しかしながら、上記方法にあつては次のような種々の問
題があつた。
However, the above method has various problems as follows.

1 リードフレーム上のリード部(ポストボンディング
部)に銀層をメッキにより被覆するため、リードフレー
ムの製作工数が増え、銀自体も高価であることからリー
ドフレームのコストの高騰化を招く。
1. Since the lead portion (post bonding portion) on the lead frame is coated with a silver layer by plating, the number of man-hours required to manufacture the lead frame increases, and since silver itself is expensive, the cost of the lead frame increases.

2 リードフレームの銀層は、空気中に放置すると硫化
が起こり、簡単な処理による除去も難しいため、金や金
合金のワイヤのボンディング性が悪化する。
2. If the silver layer of the lead frame is left in the air, it will sulfurize, and it is difficult to remove it by simple treatment, which deteriorates the bonding properties of gold or gold alloy wires.

このため、リードフレームに銀層をメッキした後の保管
等に細心の注意を必要とする。3 リードフレーム上の
銀層の厚さが薄いと、下地の金属か酸化し、銀層の膨れ
や剥離を生じ、特に高温高湿になると、更にその膨れや
剥離が生じ易くなり、ワイヤのボンディング性が著しく
低下する。
Therefore, great care must be taken when storing the lead frame after it has been plated with a silver layer. 3 If the thickness of the silver layer on the lead frame is thin, the underlying metal will oxidize, causing the silver layer to swell and peel.Especially in high temperature and high humidity, the bulge and peeling become even more likely to occur, making wire bonding difficult. Sexuality is significantly reduced.

4 リードフレームのリード部に銀層が被覆されている
と、半導体素子上面の電極に金、金合金のワイヤをボン
ディングする際、水素トーチがリード部上の銀層にあた
つた場合、その銀層部分が酸化されるばかりか、下地の
金属も酸化さ,れるため、ワイヤのボンディング性を損
なう。
4. If the lead portion of the lead frame is coated with a silver layer, when bonding gold or gold alloy wire to the electrode on the top surface of the semiconductor element, if a hydrogen torch hits the silver layer on the lead portion, the silver layer will be removed. Not only is the layer portion oxidized, but the underlying metal is also oxidized, impairing the bonding properties of the wire.

5 リードフレームのリード部上の銀層に金ワイヤをポ
ストボンディングした構造の半導体装置を高温雰囲気中
で長時間動作させると、リードフレームの電極(リード
部)に水滴が付着し、このリード部から銀が溶け出す、
いわゆるマイグレーション現象が起こり、銀が他方のリ
ード部に析出して両ソー1゛間を銀で短絡させ、著しく
信頼性を損なう。
5 When a semiconductor device with a structure in which gold wire is post-bonded to the silver layer on the lead part of a lead frame is operated for a long time in a high temperature atmosphere, water droplets will adhere to the electrodes (lead parts) of the lead frame, and water droplets will adhere to the electrodes (lead parts) of the lead frame. silver begins to melt,
A so-called migration phenomenon occurs, and silver is deposited on the other lead portion, causing a short circuit between the two saws 1 with silver, which significantly impairs reliability.

6金属薄片板から製品までの製造工程を自動化クする場
合、銀メッキ工程が必要なため査動化が困難となる。
6 When automating the manufacturing process from thin metal sheets to products, it is difficult to automate the process because a silver plating process is required.

7銀使用量を少なくしてコスト低減を図るためにリード
フレームのリード部等に銀層を部分メッキにより被覆す
ると、リードフレームに方向性が生じる。
7 When the lead portions of a lead frame are coated with a silver layer by partial plating in order to reduce the amount of silver used and reduce costs, directionality occurs in the lead frame.

8金属薄片板からリードフレームをブレス等で製作する
場合、銀層のメッキ不良はブレス中に検出して取出すた
め、ブレスの可動率が低下する。
8. When manufacturing a lead frame from a thin metal plate using a press or the like, defects in the plating of the silver layer are detected and removed during the press, reducing the movability of the press.

なお、上述した問題点は素子配設基材としてリードフレ
ームを用いる代りにステムを用いた場合ても同様である
Note that the above-mentioned problems are the same even when a stem is used instead of a lead frame as the element mounting base material.

本発明は上記種々の問題点を一挙に解消するためになさ
れたもので、素子配設基材のポストボンディング部に銀
層を被覆せず、該基材の素地(銅もしくは銅合金の単体
)に直接金や金合金のワイヤをボンディングた半導体装
置を提供しようとす7るものである。
The present invention was made in order to solve the above various problems all at once, and does not cover the post-bonding part of the element mounting base material with a silver layer, and instead uses the base material of the base material (copper or copper alloy alone). The present invention aims to provide a semiconductor device in which gold or gold alloy wire is directly bonded to the semiconductor device.

次に、本発明の一実施例を第3図及ひ第4図を参照して
説明する。
Next, an embodiment of the present invention will be described with reference to FIGS. 3 and 4.

第3図は例えばバイポーラ半導体素子をリードフレーム
にマウントし、更にワイヤボンディングaを行なつた状
態を示す斜視図、第4図は樹脂封止、カッティング加工
を施した後の半導体装置を示すものである。
Figure 3 is a perspective view showing, for example, a bipolar semiconductor element mounted on a lead frame and wire bonding a performed, and Figure 4 shows the semiconductor device after resin sealing and cutting. be.

図中101は半導体素子がマウントされるアイランド部
102及びワイヤボンディングされるリード部103a
,103bを有する銅単体からなるリードフレームであ
る。また、図中の104は第5図に示す如くマウント面
に厚さ約600入のバナジウム層105,厚さ約200
0Aのニッケル層106,厚さ1.0μmの金・ゲルマ
ニウム(Gll2Wt%)合金層107及び厚さ100
0Aの金層108が順次積層されたバイポーラ型シリコ
ン半導体素子であり、この半導体素子104は第4図に
示す如く前記銅単体からなるリードフレーム101のア
イランド部102に還元性雰囲気(例えばH2−N2の
フォーミングガス)で加熱押圧によつてマウントされて
いる。つまり、半導体素子104はアイランド部102
に半導体素子104のシリコンが含有されないAu−G
−Cuの全率固溶体からなる接合層109を介してマウ
ントされている。また、前記半導体素子104の上面に
はベース、エミッタのA1電極110a,110bが設
けられ、これらN電極110a,110bには例えば金
ワイヤ111a,111bの一端が夫々還元性雰囲気(
例えばH2−N2のフォーミングガス)でボンディング
されている。そして、これら金ワイヤ111a,111
bの他端は前記銅単体からなるリードフレーム101の
ベース、エミッタの電極として機能するリード部103
a,103bに夫々還元性雰囲気(例えばH2−N2の
フォーミングガス)でボンディングされている。つまり
、金ワイヤ111a,111bの他端は銅単体のリード
部103a,103bにAu−Cuの全率固溶体で接合
されている。更に、半導体素子104を含むリードフレ
ーム101のアイランド部102及びリード部103a
,103bの金ワイヤ111a,111b接続付近は樹
脂封止層112て覆われている。また、樹脂封止層11
2から露出したアイランド部のリード(図示せす)及び
リード部103a,103bには半田層113が被覆さ
れている。なお、上述した半導体装置は例えば以下に示
す方法により造ることができる。まず、銅製薄片板をブ
レス加工して銅単体からなるリードフレームを作製する
In the figure, reference numeral 101 denotes an island portion 102 on which a semiconductor element is mounted and a lead portion 103a on which wire bonding is performed.
, 103b is a lead frame made of simple copper. In addition, 104 in the figure is a vanadium layer 105 with a thickness of about 600 mm on the mounting surface, and a vanadium layer 105 with a thickness of about 200 mm, as shown in FIG.
0A nickel layer 106, 1.0 μm thick gold/germanium (Gll2Wt%) alloy layer 107, and 100 μm thick gold/germanium (Gll2Wt%) alloy layer 107.
This semiconductor element 104 is a bipolar silicon semiconductor element in which gold layers 108 of 0A are sequentially laminated, and as shown in FIG. Mounted by heating and pressing with (forming gas). In other words, the semiconductor element 104 is
Au-G containing no silicon of the semiconductor element 104
- It is mounted via a bonding layer 109 made entirely of a solid solution of Cu. Further, base and emitter A1 electrodes 110a and 110b are provided on the upper surface of the semiconductor element 104, and one ends of gold wires 111a and 111b are connected to these N electrodes 110a and 110b, respectively, in a reducing atmosphere (
For example, bonding is performed using H2-N2 forming gas). And these gold wires 111a, 111
The other end of b is a lead portion 103 that functions as the base and emitter electrode of the lead frame 101 made of copper alone.
A and 103b are bonded to each other in a reducing atmosphere (for example, H2-N2 forming gas). In other words, the other ends of the gold wires 111a and 111b are joined to lead portions 103a and 103b made of copper alone using a solid solution of Au-Cu. Furthermore, the island portion 102 and lead portion 103a of the lead frame 101 including the semiconductor element 104
, 103b where the gold wires 111a and 111b are connected are covered with a resin sealing layer 112. In addition, the resin sealing layer 11
A solder layer 113 is coated on the leads (shown in the figure) of the island portion exposed from 2 and the lead portions 103a and 103b. Note that the above-described semiconductor device can be manufactured, for example, by the method shown below. First, a thin copper plate is pressed to produce a lead frame made of copper alone.

つづいて複数個のNpnバイポーラトランジスタが形成
されたシリコン基板のマウント面に厚さ約600Aのバ
ナジウ1、層、厚さ約2000Aのニッケル層、厚さ1
.0μmの金・ゲルマニウム(Gel2Wt%)合金層
及び厚さ1000Aの金層を順次真空蒸着した後、シリ
コン基板をその上面(マウント面と反対側の面)より,
ダイヤモンドスクライブ又はブレードダイサースクライ
ブにより割断して第5図に示す半導体素子104を作成
する。なお、これら半導体素子は塩化ビニール等で被覆
して保管する。次いで、前記リードフレームをH2−N
2のフォーミングガス.(還元性雰囲気)中で370〜
400′Cに加熱した状態で、このリードフレームのア
イランド部に前記半導体素子を振動を与えずに50〜8
0yの加重で押圧してマウントする。その後、マウント
された半導体素子のA1電極に金ワイヤの一端を前記フ
ォーミングガスの雰囲気でボンディングし、更に金ワイ
ヤの他端を銅単体のリードフレームのリード部に還元性
雰囲気中、300〜350゜Cでポストボンディングし
、更に樹脂封止を施した後、延出したリード部等を半田
浴に浸漬し半田処理を施して第4図に示す半導体装置を
造る。しかして、本発明によれば半導体素子104上面
のA1電極110a,110bに一端が接続された金ワ
イヤ111a,111bを銅単体からなるリードフレー
ム101のリード部103a,103bに夫々Au−C
uの全率固溶体を介して良好にボンディングされた半導
体装置を得ることができるため、以下に列挙する種々の
効果を有するものである。
Next, on the mounting surface of the silicon substrate on which a plurality of Npn bipolar transistors were formed, a layer of Vanadium 1 with a thickness of about 600A was added, and a nickel layer with a thickness of about 2000A, and a layer of nickel with a thickness of 1
.. After successively vacuum-depositing a 0 μm gold/germanium (Gel2Wt%) alloy layer and a 1000A thick gold layer, the silicon substrate was deposited from its upper surface (the surface opposite to the mounting surface).
The semiconductor element 104 shown in FIG. 5 is produced by cutting with a diamond scribe or a blade dicer scribe. Note that these semiconductor elements are stored covered with vinyl chloride or the like. Next, the lead frame is H2-N
2 forming gas. 370~ in (reducing atmosphere)
While heated to 400'C, the semiconductor element was heated to 50 to 80°C without applying vibration to the island part of this lead frame.
Mount by pressing with a weight of 0y. After that, one end of the gold wire is bonded to the A1 electrode of the mounted semiconductor element in the above-mentioned forming gas atmosphere, and the other end of the gold wire is bonded to the lead part of the lead frame made of pure copper at an angle of 300 to 350° in a reducing atmosphere. After post-bonding with C and further resin sealing, the extended lead portions and the like are immersed in a solder bath and soldered to produce the semiconductor device shown in FIG. According to the present invention, the gold wires 111a and 111b, one end of which is connected to the A1 electrodes 110a and 110b on the upper surface of the semiconductor element 104, are connected to the lead portions 103a and 103b of the lead frame 101 made of pure copper using Au-C.
Since it is possible to obtain a semiconductor device that is well bonded through the solid solution of u, it has various effects listed below.

(1) リードフレーム上には銀層の被覆が不要となり
、銅(もしくは銅合金)の単体からなるため、銀メッキ
工程を省略できることによる工程の短縮化と、リードフ
レームを安価に製作できる。
(1) There is no need to cover the lead frame with a silver layer, and since it is made of copper (or copper alloy) alone, the process can be shortened by omitting the silver plating process, and the lead frame can be manufactured at low cost.

(2)銀層の被覆が不要となるため、銀の欠点である銀
の硫化によるワイヤの接合強度の低下、銀層下の下地の
酸化を解消でき、リードフレームの保管時、マウント時
に細心の注意をはらうことなく、ワイヤをリードフレー
ムのリード部に強固の接合できる。
(2) Since there is no need to coat the lead frame with a silver layer, it is possible to eliminate the disadvantages of silver, such as a decrease in wire bonding strength due to silver sulfurization and oxidation of the base under the silver layer, and prevent the lead frame from being carefully stored and mounted. The wire can be firmly joined to the lead part of the lead frame without any precautions.

(3) リードフレームのワイヤボンディング部に銀層
が被覆されていないため、半導体装置を高温雰囲気中で
長時間動作させても、銀のマイグレーション現象による
電極リード部間の短絡を解消でき、信頼性を著しく向上
できる。
(3) Since the wire bonding part of the lead frame is not coated with a silver layer, even if the semiconductor device is operated for a long time in a high-temperature atmosphere, short circuits between the electrode lead parts due to silver migration phenomenon can be eliminated, improving reliability. can be significantly improved.

(4)半導体素子上面の電極への金ワイヤのボンディン
グに際して水素トーチがリードフレームのリード部に当
たつても、そのリード部には銀層が被覆されていないた
め、銀層が被覆されることに伴なうリード部の酸化、劣
化を起こすことなくワイヤを良好にボンデ,インクでき
る。
(4) Even if the hydrogen torch hits the lead part of the lead frame when bonding the gold wire to the electrode on the top surface of the semiconductor element, the lead part is not covered with a silver layer, so the silver layer will not cover it. Wire bonding and ink can be bonded and inked well without causing oxidation or deterioration of the lead portion due to oxidation or deterioration.

この金ワイヤのボンディングに際し、還元ガス(例えば
H2が10%程度含むフォーミングガス)を使用すれば
水素トーチが消えにくくなり、リードフレームのリード
部を構成する銅の酸化も還元されボンディング性が良好
となる。(5)銅単体からなるリードフレームのリード
部に金ワイヤをボンディングしたことにより形成された
接合層は金と銅の全率形の固溶体で金属間化合物となら
ない。
When bonding this gold wire, using a reducing gas (for example, a forming gas containing about 10% H2) will prevent the hydrogen torch from extinguishing, and will also reduce the oxidation of the copper that makes up the lead part of the lead frame, resulting in good bonding properties. Become. (5) The bonding layer formed by bonding a gold wire to the lead portion of a lead frame made of simple copper is a solid solution of gold and copper in a total proportion and does not form an intermetallic compound.

このため、ボンディングの接合層に金属間化合物ができ
ないので、電気抵抗が小さく、化学的に安定し、機械的
強度の劣化のない高信頼性の半導体装置を得ることがで
きる。またリードフレームの構成材である銅は酸化され
易いが、接合層は金の拡散もしくは溶融により貴金属化
して酸化されにくくなる。更に、空気中で加熱酸化され
ても、金が拡散して貴金属層が広くなるため、接合層の
酸化は起こらない。(6) リードフレームに銀層を被
覆するためのメッキ工程を省略できるので、銀層の信頼
性試験(銀層の膨れ、剥れ試験、メッキ厚さ、メッキ不
良の試験)が不要となり、かつ半導体装置の製造に際し
ての自動化が容易となり、更にブレス加工後の洗浄が簡
単になると共に、銀層の被覆による方向性の生じない高
精のリードフレームを得ることができる。
Therefore, since no intermetallic compound is formed in the bonding layer, it is possible to obtain a highly reliable semiconductor device with low electrical resistance, chemical stability, and no deterioration in mechanical strength. Further, although copper, which is a constituent material of the lead frame, is easily oxidized, the bonding layer becomes a precious metal by diffusion or melting of gold, and becomes resistant to oxidation. Furthermore, even when heated and oxidized in air, the gold diffuses and the noble metal layer becomes wider, so oxidation of the bonding layer does not occur. (6) Since the plating process for coating the lead frame with a silver layer can be omitted, reliability tests for the silver layer (tests for blistering, peeling, plating thickness, and plating defects) of the silver layer are no longer necessary, and Automation during the manufacture of semiconductor devices becomes easy, cleaning after press processing becomes easy, and a high-precision lead frame without directionality caused by coating with a silver layer can be obtained.

その他、リードフレームの洗浄中に局部電池の発生によ
る酸化が起こらない。なお、本発明に係る半導体装置は
上記実施例の如く銅単体からなるリードフレームを用い
る場合に限定されず、Cu−Sn,Cu−Zn或いはリ
ン青銅などの銅合金単体から構成してもよい。
Additionally, oxidation due to local battery generation does not occur during cleaning of the lead frame. Note that the semiconductor device according to the present invention is not limited to the case where a lead frame made of copper alone is used as in the above embodiment, but may be constructed from a single copper alloy such as Cu-Sn, Cu-Zn, or phosphor bronze.

ワイヤに関しても金ワイヤに代つて金合金ワイヤを用い
てもよい。また、本発明に係る半導体装置は上記実施例
の如く、銅(もしくは銅合金)単体からなるリードフレ
ームに金(もしくは金合金)のワイヤをボンディングし
た構造に限らず、銅もしくは銅単体からなるステムにワ
イヤをボンディングしてもよい。
As for the wire, a gold alloy wire may be used instead of the gold wire. Further, the semiconductor device according to the present invention is not limited to the structure in which a gold (or gold alloy) wire is bonded to a lead frame made of copper (or copper alloy) alone, as in the above embodiment, but also has a structure in which a lead frame made of copper (or copper alloy) alone is bonded. You may also bond wires to the

更に本発明に係る半導体装置は上記実施例に示す如くマ
ウント面にバナジウム、ニッケル、金・ゲルマニウム、
金の4層の金属層を積層した半導体素子を用い、この素
子を銅単体からなるリードフレームのアイランド部にマ
ウントした構造に限らず、半導体素子を金プリフォーム
体などのろう材、金共晶合金を介して銀ベース特が被覆
された、アイランド部にマウントしてもよい。
Further, the semiconductor device according to the present invention has vanadium, nickel, gold/germanium, etc. on the mounting surface as shown in the above embodiment.
The semiconductor element is not limited to a structure in which a semiconductor element made of four metal layers of gold is laminated and mounted on an island part of a lead frame made of simple copper. It may also be mounted on an island portion coated with a silver base material via an alloy.

つまり、本発明の半導体装置は金もしくは金合金のワイ
ヤがボンディングされる素子配設基材が銅もしくは銅合
金の単体からなることが必要で、半導体素子のマウント
部に必要に応じて銀層を被覆してもよい。以上詳述した
如く、本発明によれば素子配設基材のポストボンディン
グ部に銀層を被覆せずに、該基材の素地(銅もしくは銅
合金の単体)に金もしくは金合金のワイヤを直接ボンデ
ィングすることにより、前述の(1)〜(6)に列挙し
たボンディング性能に優れ、安価て高信頼性である等の
効果を有する半導体装置を提供するものである。
In other words, in the semiconductor device of the present invention, the element mounting base material to which the gold or gold alloy wire is bonded must be made of copper or a copper alloy alone, and a silver layer may be applied to the mounting portion of the semiconductor element as necessary. It may be coated. As detailed above, according to the present invention, a gold or gold alloy wire is coated on the base material (single copper or copper alloy) of the base material (copper or copper alloy alone) without coating the post-bonding part of the element mounting base material with a silver layer. Direct bonding provides a semiconductor device that has the effects of excellent bonding performance listed in (1) to (6) above, low cost, and high reliability.

【図面の簡単な説明】 第1図はシリコン半導体素子をリードフレームにマウン
トし、かつ同素子とリードフレームのリード部とを金ワ
イヤで接続した状態を示す斜視図、第2図は第1図のリ
ードフレームを樹脂封止し、カッティングした後の半導
体装置を示す断面図、第3図は本発明の一実施例を示す
シリコン半導体素子をリードフレームにマウント、ボン
ディングした状態の斜視図、第4図は第3図のリードフ
レームを樹脂封止し、カッティング加工した後の半導体
装置を示す断面図、第5図は第3図の半導体素子をマウ
ントする前の状態を示す断面図である。 101・・・・・・銅単体からなるリードフレーム、1
02・・・・アイランド部、103a,103b・・・
・リード部、104・・・・・・バイポーラ型シリコン
半導体素子、109・・・・・・接合層、110a,1
10b・・・・ベース、エミッタのAl電極、111a
,111b・・・・・・金ワイヤ、112・・・・・・
樹脂封止層。
[Brief Description of the Drawings] Figure 1 is a perspective view showing a silicon semiconductor element mounted on a lead frame, and the element and the leads of the lead frame are connected with gold wires, and Figure 2 is the same view as Figure 1. 3 is a cross-sectional view showing a semiconductor device after the lead frame is resin-sealed and cut; FIG. 3 is a perspective view of a silicon semiconductor device according to an embodiment of the present invention mounted and bonded to the lead frame; FIG. This figure is a sectional view showing the semiconductor device after the lead frame shown in FIG. 3 has been sealed with resin and cut, and FIG. 5 is a sectional view showing the semiconductor device shown in FIG. 3 before being mounted. 101...Lead frame made of copper alone, 1
02...Island part, 103a, 103b...
・Lead part, 104... Bipolar silicon semiconductor element, 109... Bonding layer, 110a, 1
10b...Al electrode of base and emitter, 111a
, 111b... Gold wire, 112...
Resin sealing layer.

Claims (1)

【特許請求の範囲】[Claims] 1 銅もしくは銅合金の単体からなる素子配設基材と、
上面に電極を有する半導体素子と、金層、金、ゲルマニ
ウム合金層、ニツグル層及びバナジウム層をこの順序で
積層した四層構造のろう材を用い、前記基材上に前記半
導体素子を前記ろう材をその金層が基材側に、バナジウ
ム層が半導体素子側に位置するように介在させた状態で
還元性雰囲気にてマウントし、かつ前記素子配設基材と
前記半導体素子の電極とを金もしくは金合金のワイヤで
還元性雰囲気にて接続したことを特徴とする半導体装置
1. An element mounting base material made of a single piece of copper or copper alloy;
Using a four-layer brazing material in which a semiconductor element having an electrode on its upper surface, a gold layer, a gold, germanium alloy layer, a Nitzgul layer, and a vanadium layer are laminated in this order, the semiconductor element is placed on the base material. is mounted in a reducing atmosphere with the gold layer on the base material side and the vanadium layer on the semiconductor element side, and the element mounting base material and the electrode of the semiconductor element are mounted on the gold layer. Or a semiconductor device characterized by being connected in a reducing atmosphere using gold alloy wire.
JP55185920A 1980-12-26 1980-12-26 semiconductor equipment Expired JPS6057220B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55185920A JPS6057220B2 (en) 1980-12-26 1980-12-26 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55185920A JPS6057220B2 (en) 1980-12-26 1980-12-26 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS57109351A JPS57109351A (en) 1982-07-07
JPS6057220B2 true JPS6057220B2 (en) 1985-12-13

Family

ID=16179184

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55185920A Expired JPS6057220B2 (en) 1980-12-26 1980-12-26 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS6057220B2 (en)

Also Published As

Publication number Publication date
JPS57109351A (en) 1982-07-07

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