Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JPS6057221B2 - semiconductor equipment - Google Patents
[go: Go Back, main page]

JPS6057221B2 - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS6057221B2
JPS6057221B2 JP55188888A JP18888880A JPS6057221B2 JP S6057221 B2 JPS6057221 B2 JP S6057221B2 JP 55188888 A JP55188888 A JP 55188888A JP 18888880 A JP18888880 A JP 18888880A JP S6057221 B2 JPS6057221 B2 JP S6057221B2
Authority
JP
Japan
Prior art keywords
layer
gold
lead frame
semiconductor element
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55188888A
Other languages
Japanese (ja)
Other versions
JPS57111041A (en
Inventor
欣男 伊藤
三男 小林
俊夫 鉄矢
修 薄田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP55188888A priority Critical patent/JPS6057221B2/en
Publication of JPS57111041A publication Critical patent/JPS57111041A/en
Publication of JPS6057221B2 publication Critical patent/JPS6057221B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • H10W72/07331Connecting techniques
    • H10W72/07336Soldering or alloying
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07551Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • H10W72/351Materials of die-attach connectors
    • H10W72/352Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5449Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/59Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/951Materials of bond pads
    • H10W72/952Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00Subject matter not provided for in other groups of this subclass

Landscapes

  • Die Bonding (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve bonding by mounting a semiconductor element, an upper surface thereof has an Al electrode, to an element disposed base material coated with a Ni or Ni alloy layer, and connecting the Al electrode and the base material by a wire made of Al or an Al alloy. CONSTITUTION:The surface of the lead frame 101 is coated with the Ni or Ni alloy layer 102, the semiconductor element, the upper surface thereof has the Al electrodes 111a, 111b, is mounted to an island section 103 of the lead frame 101, and the lead sections 104a, 104b of the lead frame 101 and the Al electrodes 111a, 111b are connected by the wires 112a, 112b consisting of Al or the Al alloy. Accordingly, both pellet bonding and post bonding can be improved, and the semiconductor device having high reliability can be obtained at low cost.

Description

【発明の詳細な説明】 本発明は半導体装置に関し、特に半導体素子がマウン
トされ、かつ該素子の電極に接続したワイヤがボンディ
ングされる素子配設基材を改良した半導体装置に係る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an improved element mounting base material on which a semiconductor element is mounted and wires connected to electrodes of the element are bonded.

一般に、半導体装置は第1図及び第2図に示す構造の
ものが知られている。即ち、第1図はシリコン半導体素
子(例えばバイポーラ半導体素子)を素子配設基材(例
えばリードフレーム)にマウ ントし、さらにワイヤボ
ンディングした状態を示す斜視図、第2図は樹脂封止、
カッティング加工後の状態を示す断面図で、図中の1は
半導体素子がマウントされるアイランド部2及びワイヤ
がボンディングされるリード部3a、3bを有するリー
ドフレームである。このリードフレーム1のアイランド
部2、リード部3a、3bのボンディング部周囲には銀
層4が被覆されている。また、前記アイランド部2には
上面にベース、エミッタの川電極5a、5bを有するシ
リコン半導体素子6が金を主成分とする層7を介してマ
ウントされている。この半導体素子6のAl電極5a、
5bには夫々金ワイヤBa、8bが接続され、かつこれ
ら金ワイヤBa、8bの他端はベース、エミッタの電極
として機能する内部リード3a、3bに夫々ポストボン
ディングされている。更に図中の9は半導体素子6を含
むアイランド部2及びりード部3a、3bの金ワイヤB
a、8b接続部付近を覆う樹脂封止層である。なお、樹
脂封止層9か’ら露出したアイランド部のリード(図示
せず)やリード部3a、3bは半田層10が被覆されて
いる。また、素子配設基材としてリードフレームの代り
に、第3図に示す如くステムを用いたハーメテイツクシ
ール構造の半導体装置が知られている。
Generally, semiconductor devices having structures shown in FIGS. 1 and 2 are known. That is, FIG. 1 is a perspective view showing a state in which a silicon semiconductor element (for example, a bipolar semiconductor element) is mounted on an element mounting base material (for example, a lead frame) and further wire bonded, and FIG.
This is a cross-sectional view showing the state after cutting, and numeral 1 in the figure is a lead frame having an island portion 2 on which a semiconductor element is mounted and lead portions 3a and 3b to which wires are bonded. A silver layer 4 is coated around the island portion 2 of the lead frame 1 and the bonding portions of the lead portions 3a and 3b. Further, a silicon semiconductor element 6 having base and emitter river electrodes 5a and 5b on its upper surface is mounted on the island portion 2 via a layer 7 mainly composed of gold. Al electrode 5a of this semiconductor element 6,
Gold wires Ba and 8b are connected to 5b, respectively, and the other ends of these gold wires Ba and 8b are post-bonded to internal leads 3a and 3b functioning as base and emitter electrodes, respectively. Further, reference numeral 9 in the figure denotes a gold wire B of the island portion 2 containing the semiconductor element 6 and the lead portions 3a and 3b.
a, 8b A resin sealing layer covering the vicinity of the connection portion. Note that the leads (not shown) of the island portion exposed from the resin sealing layer 9 and the lead portions 3a and 3b are covered with a solder layer 10. Further, a semiconductor device having a hermetically sealed structure is known in which a stem is used as an element mounting base material instead of a lead frame, as shown in FIG.

即ち、第3図中の11は周囲に銀層12が被覆された銅
製のステム本体である。この本体11には2つの貫通孔
13a,(13b)が設けられ、これら貫通孔13a,
(13b)には上端に広幅のヘッド部14a,(14b
)を有する銅製のリード線15a,(15b)がガラス
絶縁体16a,(16b)を介して貫通支持されている
。なお、リード線15a,(15b)のヘッド部14a
,(14b)にも銀層12が被覆されている。また、前
記ステム本体11の銀層12上には金を主成分とする接
合層17を介してバイポーラ型半導体素子18がマウン
トされ、かつ該半導体素子18上面にはベース、エミッ
タのに電極19a,(19b)が設けられている。そし
て、これらAl電極19a,(19b)には金ワイヤ2
0a,(20b)の一端が夫々接続され、かつこれら金
ワイヤ20a,(20b)の他端は前記ベース、エミッ
タ電極として機能するリード線15a,(15b)のヘ
ッド部14a,(14b)上の銀層12にボンディング
されている。更に、半導体素子18がマウントされてい
るステム本体11側には該素子18を気密にシールする
キャップ21が被覆2されている。なお、図中の22は
一端がステム本体11に接続されたコレクタ電極として
機能するリード線である。しかしながら、上述した第2
図、第3図の半導体装置において、金ワイヤが夫々接続
される半導3体素子上面の電極はアルミニウムで、素子
配設基材(リード部など)は銀層が被覆されているため
、銀層のリード部には金ワイヤを良好にポストボンディ
ングできるものの、A1電極に金ワイヤをペレットボン
ディングすると、パープルプレー3グが発生し易く、金
とアルミ−ニウムの金属間化合物が生じ、それらの接合
面にクラックが発生してペレットボンディングの信頼性
が著しく低下する欠点があつた。
That is, 11 in FIG. 3 is a stem body made of copper whose periphery is coated with a silver layer 12. This main body 11 is provided with two through holes 13a, (13b), and these through holes 13a,
(13b) has a wide head portion 14a at the upper end, (14b)
) Copper lead wires 15a, (15b) are supported through glass insulators 16a, (16b). Note that the head portion 14a of the lead wires 15a, (15b)
, (14b) are also coated with the silver layer 12. A bipolar semiconductor element 18 is mounted on the silver layer 12 of the stem body 11 via a bonding layer 17 mainly composed of gold, and on the upper surface of the semiconductor element 18 there are electrodes 19a for the base and emitter. (19b) is provided. Gold wires 2 are attached to these Al electrodes 19a, (19b).
One end of these gold wires 20a, (20b) is connected to the head portions 14a, (14b) of the lead wires 15a, (15b) which function as the base and emitter electrodes. It is bonded to the silver layer 12. Further, the side of the stem body 11 on which the semiconductor element 18 is mounted is covered with a cap 21 for airtightly sealing the element 18. Note that 22 in the figure is a lead wire whose one end is connected to the stem body 11 and functions as a collector electrode. However, the second
In the semiconductor devices shown in Figs. and 3, the electrodes on the top surface of the three-piece semiconductor element to which the gold wires are connected are made of aluminum, and the element mounting base material (lead parts, etc.) is coated with a silver layer. Although gold wire can be post-bonded well to the lead part of the layer, when gold wire is pellet-bonded to the A1 electrode, purple play is likely to occur, and an intermetallic compound of gold and aluminum is formed, resulting in poor bonding between them. The drawback was that cracks occurred on the surface, significantly reducing the reliability of pellet bonding.

このようなことから、ワイヤをアルミニウムで4形成し
、このアルミニウムワイヤを用いて半導体素子上面のア
ルミニウム電極と素子配設基材のリード部等に被覆した
銀層とを接続することが行なわれている。
For this reason, wires are formed from aluminum, and the aluminum wires are used to connect the aluminum electrodes on the top surface of the semiconductor element and the silver layer coated on the leads, etc. of the element mounting base material. There is.

しかしながら、.こうした構造の場合、電極とワイヤと
のペレットボンディングは良好になるものの、アルミニ
ウムワイヤを銀層にボンディングすると、水分付着によ
りアルミニウムと銀間で局部電池が発生して腐蝕が起こ
り、ポストボンディング性が著しく損なわれる。更に、
上述した第3図、第4図の半導体装置及び前記改良した
ワイヤボンディング手段は、いずれもワイヤポストボン
ディングされた素子配設基材上に銀層が被覆されている
ため、次に挙げる種々の問題を生じる。
however,. In such a structure, pellet bonding between the electrode and the wire is good, but when the aluminum wire is bonded to the silver layer, local batteries occur between the aluminum and silver due to moisture adhesion, causing corrosion and significantly reducing post-bonding properties. be damaged. Furthermore,
In both the semiconductor devices shown in FIGS. 3 and 4 and the improved wire bonding means described above, a silver layer is coated on a wire post-bonded element mounting base material, and therefore, there are various problems listed below. occurs.

1素子配設基材のリード部(ポストボンディング部)上
に銀層をメッキにより被覆するため、素子配設基材の製
作工程が増え、銀自体も高価であることからリードフレ
ームのコストの高騰化を招く。
1 Since a silver layer is coated on the lead part (post bonding part) of the element mounting base material by plating, the manufacturing process of the element mounting base material increases, and the cost of the lead frame increases because silver itself is expensive. invites change.

2素子配設基材上の銀層は、空気中に放置すると硫化が
起こり、簡単な処理による除去も難しいため、ワイヤが
金/7)らなる場合でもボンディング性が悪化する。
The silver layer on the two-element substrate will sulfurize if left in the air, and is difficult to remove by simple treatment, resulting in poor bonding properties even when the wire is made of gold/7).

このため、素子配設基材に銀層をメッキした後の保管等
に細心の注意を必要とする。3素子配設基材上の銀層の
厚さが薄いと、下地の金属か酸化し、銀層の膨れや剥離
を生じ、特に高温高湿になると、更にその膨れや剥離が
生じ易くなり、ワイヤのボンディング性が著しく低下す
る。
For this reason, extreme care must be taken during storage after plating the silver layer on the element-arranged substrate. If the thickness of the silver layer on the three-element substrate is thin, the underlying metal will oxidize, causing blistering and peeling of the silver layer. Especially when the temperature is high and humid, the blistering and peeling become even more likely to occur. Wire bonding properties are significantly reduced.

4素子配設基材のリード部等に銀層が被覆されていると
、半導体素子上面の電極に金、金合金のワイヤをボンデ
ィングする際、水素トーチがリード部上の銀層にあつた
場合、その銀層部分か酸化されるばかりか、下地の金属
も酸化されるため、ワイヤのボンディング性を損なう。
If the lead parts of the 4-element mounting base material are coated with a silver layer, if a hydrogen torch hits the silver layer on the lead part when bonding gold or gold alloy wire to the electrode on the top surface of the semiconductor element. Not only is the silver layer oxidized, but the underlying metal is also oxidized, impairing the bonding properties of the wire.

5素子配設基材のリード部等の上の銀層に金ワイヤをポ
ストボンディングした構造の半導体装置を高温雰囲気中
で長時間動作させると、素子配設基材の電極(リード部
)に水滴が付着し、このリード部から銀が溶け出す、い
わゆるマイグレーション現象が起こり、銀が他方のリー
ド部に析出して両リード間を銀て短絡させ、著しく信頼
性を損なう。6金属薄片板から製品までの製造工程を自
動化する場合、銀メッキ工程が必要なため自動化が困難
となる。
5 When a semiconductor device with a structure in which gold wires are post-bonded to the silver layer on the lead parts of the element-arranged base material is operated in a high-temperature atmosphere for a long time, water droplets may form on the electrodes (lead parts) of the element-arranged base material. A so-called migration phenomenon occurs in which silver adheres and dissolves from this lead portion, and silver is deposited on the other lead portion, causing a short circuit between the two leads, significantly impairing reliability. 6 When automating the manufacturing process from thin metal sheets to products, it is difficult to automate the process because a silver plating process is required.

7銀使用量を少なくしてコスト低減を図るために素子配
設基材のリード部等に銀層を部分メッキにより被覆する
と、素子配設基材に方向性が生じる。
7 In order to reduce the amount of silver used and reduce costs, if a silver layer is partially coated on the lead portions of the element-arranged substrate by partial plating, directionality occurs in the element-arranged substrate.

8金属薄片板から素子配設基材をブレス等で製作する場
合、銀層のメッキ不良はブレス中に検−査して取出すた
め、ブレスの可動率が低下する。
8. When manufacturing an element mounting base material from a thin metal plate using a press or the like, defects in the plating of the silver layer are inspected and removed during the press, which reduces the movability of the press.

本発明は上記様々の問題点を一挙に解消するためになさ
れたもので、少なくとも主面にニッケルもしくはニッケ
ル合金層が被覆された素子配設基材を用い、この基材に
に電極を有する半導体素子をマウントすると共に該N電
極と前記基材主面のニッケルもしくはニッケル合金層と
をアルミニウムもしくはその合金からなるワイヤで接続
することによりペレットボンディング、ポストボンディ
ングが共に良好で高信頼性の半導体装置を提供しようと
するものてある。
The present invention has been made to solve the above various problems all at once, and uses an element mounting base material whose main surface is coated with a nickel or nickel alloy layer, and a semiconductor device having electrodes on the base material. By mounting the element and connecting the N electrode and the nickel or nickel alloy layer on the main surface of the base material with a wire made of aluminum or its alloy, a highly reliable semiconductor device with good pellet bonding and post bonding can be obtained. There is something we are trying to offer.

以下、本発明の一実施例を第4図及ひ第5図を参照して
説明する。
Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 4 and 5.

第4図は例えばバイポーラ型半導体素子をりーードフレ
ームにマウントし、更にワイヤボンディングを行なつた
状態を示す斜視図、第5図は樹脂封止、カッティング加
工を施した後の半導体装置を示すものである。
Figure 4 is a perspective view showing, for example, a bipolar semiconductor device mounted on a lead frame and wire bonded, and Figure 5 shows the semiconductor device after resin sealing and cutting. be.

図中101は主面にニッケル層102が被覆された鉄素
材からなるリードフレームで、このリードフレーム10
1には半導体素子がマウントされるアイランド部103
及びウイヤボンデイングされるリード部104a,10
4bが形成されている。また、図中の105は第6図に
示す如くマウント面に厚さ約600Aのバナジウム層1
06,厚さ約2000Aのニッケル層107,厚さ1.
0μmの金・ゲルマニウム(Ge]2wt%)合金層1
08及ひ厚さ1000Aの金層109が順次積層された
バイポーラ型シリコ半導体素子であり、この半導体素子
105は第5図に示す如く前記ニッケル層102が被覆
されたリードフレーム101のアイランド部103に還
元性雰囲気(例えば山−N2のフォーミングガス)で加
熱押圧によつてマウントされている。つまり、半導体素
子105はアイランド部103に半導体素子105のシ
リコンが含有されないAu−e−Niの全率固溶体から
なる接合層110を介してマウントされている。また、
前記半導体素子105の上面にはベース、エミッタのA
1電極111a,111bが設けられ、これらA1電極
111a,111bには例えばA1ワイヤ112a,1
12bの一端が夫々還元性雰囲気(例えばH2−N2の
フォーミングガス)でボンディングされている。そして
、これらA1ワイヤ112a,112bの他端は前記ニ
ッケル層102が被覆されたリードフレーム101のベ
ース、エミッタの電極として機能するリード部104a
,104bに夫々還元性雰囲気(例えばH2−N2のフ
ォーミングガス)でボンディングされている。つまり、
AIワイヤ112a,112bの他端はリード部104
a,104bのニッケル層102にAu−Niの二元合
金層で接合されている。更に、半導体素子105を含む
リードフレーム101のアイランド部103及びリード
部104a,104bCf)Alワイヤ112a,11
2b接続付近は樹脂封止層113で覆われている。また
、樹脂封止層113から露出したアイランド部のリード
(図示せず)及びリード部104a,104bには半田
層114が被覆されている。なお、上述した半導体装置
は例えば以下に示す方法により造ることができる。
In the figure, 101 is a lead frame made of iron material whose main surface is coated with a nickel layer 102.
1 has an island portion 103 on which a semiconductor element is mounted;
and the lead parts 104a and 10 to be wire bonded.
4b is formed. 105 in the figure is a vanadium layer 1 with a thickness of about 600A on the mounting surface as shown in FIG.
06, nickel layer 107 with a thickness of about 2000A, thickness 1.
0μm gold/germanium (Ge) 2wt% alloy layer 1
This is a bipolar silicon semiconductor device in which a gold layer 109 with a thickness of 1000 A and 0.08 mm is sequentially laminated, and as shown in FIG. Mounted by heating and pressing in a reducing atmosphere (for example, Yama-N2 forming gas). That is, the semiconductor element 105 is mounted on the island portion 103 via the bonding layer 110 that is made of an all-solid solution of Au-e-Ni that does not contain silicon. Also,
The upper surface of the semiconductor element 105 has a base and an emitter A.
1 electrodes 111a, 111b are provided, and these A1 electrodes 111a, 111b are provided with, for example, A1 wires 112a, 1
One end of each of the electrodes 12b is bonded in a reducing atmosphere (for example, H2-N2 forming gas). The other end of these A1 wires 112a and 112b is a lead portion 104a that functions as the base and emitter electrode of the lead frame 101 covered with the nickel layer 102.
, 104b in a reducing atmosphere (for example, H2-N2 forming gas). In other words,
The other ends of the AI wires 112a and 112b are the lead portions 104
It is joined to the nickel layer 102 of a and 104b by an Au-Ni binary alloy layer. Furthermore, the island portion 103 and lead portions 104a, 104bCf) of the lead frame 101 including the semiconductor element 105) Al wires 112a, 11
The vicinity of the connection 2b is covered with a resin sealing layer 113. Furthermore, the leads (not shown) in the island portion exposed from the resin sealing layer 113 and the lead portions 104a and 104b are covered with a solder layer 114. Note that the above-described semiconductor device can be manufactured, for example, by the method shown below.

まず、ニッケル層が被覆された鉄製薄片板をブレス加工
してニッケル層が被覆されたリードフレームを作製する
First, a thin iron plate coated with a nickel layer is pressed to produce a lead frame coated with a nickel layer.

つづいて複数個のNpnバイポーラトランジスタが形成
されたシリコン基板のマウント面に厚さ約600Aのバ
ナジウム層、厚さ約2000Aのニッケル層、厚さ1.
0μmの金●ゲルマニウム(Gel2wt%)合金層及
び厚さ1000Aの金・層を順次真空蒸着して積層した
後、シリコン基板をその上面(マウント面と反対側の面
)よりダイヤモンドスクライブ又はブレードダイサース
クライブにより割断して第6図に示す半導体素子105
を作製する。なお、これら半導体素子は塩化ビニール等
で被覆して保管する。次いで、前記リードフレームを不
活性ガス雰囲気、好ましくはH2−N2のフォーミング
ガス(還元性雰囲気)中で370〜4000Cに加熱し
た状態で、このリードフレームのアイランド部に前記半
導体素子を振動を与え)ずに50〜80yの加重で押圧
してマウントする。その後、マウントされた半導体素子
のAl電極にA1ワイヤーの一端を前記フォーミングガ
スの雰囲気でボンディングし更にNワイヤの他端をニッ
ケル層が被覆されたリードフレームのリード部に還元性
雰囲気中、300〜350℃下でポストボンデインク几
、更に樹脂封止を施した後、延出したリード部等を半田
浴に浸漬し半田処理を施して第5図に示す半導体装置を
造る。しかして、本発明によればA1ワイヤ11−2a
,112bを用い、この一端を半導体素子105上面の
Al電極111a,111bにペレットボンディングを
行なうため、従来のAl′Ri.極、A1ワイヤのボン
ディングのようなパーブルブレーグやAl,Auの金属
間化合物を生じることなく、良好に接続できる。
Next, on the mounting surface of the silicon substrate on which a plurality of Npn bipolar transistors were formed, a vanadium layer with a thickness of about 600A, a nickel layer with a thickness of about 2000A, and a nickel layer with a thickness of 1.
After successively vacuum-depositing and laminating a 0μm gold/germanium (Gel2wt%) alloy layer and a 1000A thick gold layer, the silicon substrate is diamond scribed or blade dicer scribed from its upper surface (the surface opposite to the mounting surface). The semiconductor element 105 shown in FIG.
Create. Note that these semiconductor elements are stored covered with vinyl chloride or the like. Next, while the lead frame is heated to 370 to 4000 C in an inert gas atmosphere, preferably a H2-N2 forming gas (reducing atmosphere), the semiconductor element is vibrated on the island portion of the lead frame. Mount it by pressing with a load of 50 to 80 y. After that, one end of the A1 wire was bonded to the Al electrode of the mounted semiconductor element in the above-mentioned forming gas atmosphere, and the other end of the N wire was bonded to the lead part of the lead frame coated with a nickel layer in a reducing atmosphere for 30 to 30 minutes. After post-bonding and resin sealing at 350° C., the extended leads and the like are immersed in a solder bath and soldered to produce the semiconductor device shown in FIG. According to the present invention, the A1 wire 11-2a
, 112b, and one end thereof is pellet-bonded to the Al electrodes 111a, 111b on the upper surface of the semiconductor element 105 using conventional Al'Ri. A good connection can be made without producing purple brags or intermetallic compounds of Al and Au, as in the case of A1 wire bonding.

また、AIワイヤ112a,112bの他端はニッケル
層102が被覆されたリ7ドフレーム101のリード部
104a,104bに夫々AI−Niの二元合金層を介
してポストボンディングされているため、従来のA1ワ
イヤ、銀層のボンディングのように水分付着による局部
電池の発生、腐蝕を招くことなく極めて良好に接続でき
る。したがつて、A1ワイヤによりペレットボンディン
グ、ポストボンディングが共に良好となるため、金ワイ
ヤを使用する場合に比べて著2しく安価てかつ高信頼性
の半導体装置を得ることができる。また、リードフレー
ム101のリード部104a,104bに銀層を被覆せ
ずにワイヤを良好にボンディングできるため、以下に列
挙する種々の2効果を発揮できる。
In addition, the other ends of the AI wires 112a and 112b are post-bonded to the lead parts 104a and 104b of the lead frame 101 coated with the nickel layer 102, respectively, via the AI-Ni binary alloy layer, so that The A1 wire can be connected very well without causing local batteries or corrosion due to moisture adhesion, unlike bonding with a silver layer. Therefore, since the A1 wire makes both pellet bonding and post bonding good, it is possible to obtain a semiconductor device that is significantly cheaper and more reliable than when gold wire is used. Further, since wires can be bonded well without coating the lead parts 104a and 104b of the lead frame 101 with a silver layer, two various effects listed below can be achieved.

(1) リードフレーム上には銀層の被覆が不要となる
ため、銀メッキ工程を省略することによる工程の短縮化
と、リードフレームを安価に製作できる。
3(2)銀層の被覆が
不要となるため、銀の欠点である銀の流化によるワイヤ
の接合強度の低下、銀層下の下地の酸化を解消でき、リ
ードフレームの保管時、マウント時に細心の注意をはら
うことなく、ワイヤをリードフレームのリード部に3.
強固の接合てきる。(3) リードフレームのワイヤボ
ンディング部に銀層が被覆されていないため、半導体装
置を高温雰囲気中で長時間動作させても、銀のマイグレ
ーション現象による電極リード部間の短縮を解4/消で
き、信頼性を著しく向上できる。
(1) Since it is not necessary to cover the lead frame with a silver layer, the process can be shortened by omitting the silver plating process, and the lead frame can be manufactured at low cost.
3 (2) Since there is no need to cover the silver layer, it is possible to eliminate the disadvantages of silver, such as the decrease in bonding strength of the wire due to silver flow and the oxidation of the base under the silver layer, making it easier to store and mount the lead frame. 3. Carefully insert the wire into the lead section of the lead frame.
Creates a strong bond. (3) Since the wire bonding part of the lead frame is not coated with a silver layer, even if the semiconductor device is operated for a long time in a high-temperature atmosphere, the shortening between the electrode lead parts due to the silver migration phenomenon cannot be eliminated. , reliability can be significantly improved.

(4)半導体素子上面の電極へのNワイヤのボンディン
グに際して水素トーチがリードフレームのリード部に当
たつても、そのリード部には銀層が被覆されていないた
め、銀層が被覆されることに伴なうリード部の酸化、劣
化を起こすことなくワイヤを良好にボンディングできる
(4) Even if the hydrogen torch hits the lead part of the lead frame when bonding the N wire to the electrode on the top surface of the semiconductor element, the lead part is not covered with a silver layer, so the silver layer will not cover it. Wires can be bonded well without causing oxidation or deterioration of the lead portion due to oxidation or deterioration.

このA1ワイヤのボンディングに際し、還元ガス(例え
ばH2が10%程度含むフォーミングガス)を使用すれ
ば水素トーチが消えにくくなり、リードフレームのリー
ド部を構成する銅の酸化も還元されボンディング性が良
好となる。(5) リードフレームに銀層を被覆するた
めのメッキ工程を省略できるので、銀層の信頼性試験(
銀層の膨れ、剥れ試験、メッキ厚さ、メッキ不良の試験
)が不要となり、かつ半導体装置の製造に際しての自動
化が容易となり、更にブレス加工後の洗浄が簡単になる
と共に、銀層の被覆による方向性の生じない高精のリー
ドフレームを得ることができる。
When bonding this A1 wire, if a reducing gas (for example, a forming gas containing about 10% H2) is used, the hydrogen torch will not easily disappear, and the oxidation of the copper that makes up the lead part of the lead frame will be reduced, resulting in good bonding performance. Become. (5) Since the plating process for coating the lead frame with a silver layer can be omitted, reliability testing of the silver layer (
This eliminates the need for testing for silver layer blistering, peeling, plating thickness, and plating defects, making it easier to automate the manufacturing of semiconductor devices, simplifying cleaning after press processing, and reducing the need for silver layer coating. It is possible to obtain a high-precision lead frame with no directionality.

その他、リードフレームの洗浄中に局部電池の発生によ
る酸化が起こらない。また、マウント面にバリア金属層
(バナジウム、ニッケル層)、金、ゲルマニウム合金層
を順次積層した半導体素子を用いれば、該半導体素子を
ニッケル層(もしくはニッケル合金層)が被覆されたリ
ードフレームのアイランド部に良好にマウントできるた
め、以下に列挙する如く種々の効果を発揮できる。
Additionally, oxidation due to local battery generation does not occur during cleaning of the lead frame. Furthermore, if a semiconductor element is used in which a barrier metal layer (vanadium or nickel layer), gold, or germanium alloy layer is sequentially laminated on the mounting surface, the semiconductor element can be attached to an island of a lead frame covered with a nickel layer (or nickel alloy layer). Since it can be mounted well on the body, various effects can be exhibited as listed below.

6)金プリフォーム体を用いることなく、最低必要限の
金・ゲルマニウム合金層をろう材としてマウントするた
め、マウント時における位置決め精度が良好で後工程で
のワイヤボンディングの不良発生を軽減てきる。
6) Since the minimum necessary gold/germanium alloy layer is mounted as a brazing material without using a gold preform, the positioning accuracy during mounting is good and the occurrence of wire bonding defects in the post-process is reduced.

7)金プリフォーム体を用いないため、金プリフォーム
体をリードフレーム(素子配設基材)に載置するための
装置が不要となり、工程も短縮できる。
7) Since no gold preform is used, a device for mounting the gold preform on a lead frame (element mounting base material) is not required, and the process can be shortened.

3)高価な金は、金、ゲルマニウム合金として最少必要
限しか用いないため、大幅なコストダウンを図ることが
できる。
3) Since only the minimum amount of expensive gold is used in the gold/germanium alloy, it is possible to significantly reduce costs.

))シリコンの半導体素子と金・ゲルマニウム合金層の
間のバリア金属層を介在させているため、リードフレー
ムに対して半導体素子を強固にマウントでき、しかもバ
リア金属層としてバナジウム層とニッケル層との二層構
造とすれば半導体素子と金・ゲルマニウム合金層の接着
強度を著しく向上てきる。
)) Since the barrier metal layer is interposed between the silicon semiconductor element and the gold/germanium alloy layer, the semiconductor element can be firmly mounted on the lead frame. A two-layer structure can significantly improve the adhesive strength between the semiconductor element and the gold/germanium alloy layer.

(10接合に関与する層が金・ゲルマニウム合金からな
り、従来構造のマウント面に被覆された金・シリコン共
晶層に比べてクラツキング性が良好なため、シリコン基
板の割断に際し、従来の如く金・シリコン共晶層側から
切断せずに、!通常の方法に従つてシリコン基板上面(
マウント面と反対側の面から)ダイシングラインに沿つ
て行なうことができ、高精度の割断が可能となる。
(10) The layer involved in bonding is made of a gold-germanium alloy, which has better cracking properties than the gold-silicon eutectic layer coated on the mounting surface of the conventional structure.・Do not cut from the silicon eutectic layer side! Cut the top surface of the silicon substrate (
The cutting can be performed along the dicing line (from the surface opposite to the mounting surface), making it possible to perform highly accurate cutting.

即ち、金・シリコン共晶(シリコが2.85Wt%)と
金・ゲルマニウム共晶(ゲルマニ1ウムが12Wt%)
とのクラツキング性を比較すると、各成分の密度は金1
9.3,シリコン2.42,ゲルマニウム5.46で金
・シリコン共晶中に占めるシリコンの体積は19%,金
・ゲルマニウム共晶中に占めるゲルマニウム体積は33
%となり、1金●ゲルマニウム共晶はゲルマニウムの占
める体積が相当大で、金の占める比率が低いため、金・
シリコン共晶に比べてクラツキングが容易となり、上述
の如くシリコン基板の上面側からの割断が可能となる。
That is, gold-silicon eutectic (2.85 Wt% silico) and gold-germanium eutectic (12 Wt% germanium).
Comparing the cracking properties with gold, the density of each component is 1
9.3, silicon 2.42, germanium 5.46, the volume of silicon in the gold-silicon eutectic is 19%, and the volume of germanium in the gold-germanium eutectic is 33.
%, and in the 1 gold/germanium eutectic, the volume occupied by germanium is quite large, and the ratio occupied by gold is low.
Cracking is easier than with silicon eutectic, and the silicon substrate can be cut from the upper surface side as described above.

(11)金とゲルマニウムの蒸気圧は10−1トール付
近で近似しているため、金・シリコンまたは金・アンチ
モンのような分別蒸発を招くことなく、真空蒸着法によ
り所定組成の金・ゲルマニウム合金層を形成できる。
(11) Since the vapor pressures of gold and germanium are similar at around 10-1 Torr, gold-germanium alloys of a given composition can be made by vacuum evaporation without causing fractional evaporation like gold-silicon or gold-antimony. Can form layers.

(12)金・ゲルマニウム合金層に更に金属を被覆すれ
ば、半導体素子をマウントする以前1′−おける金・ゲ
ルマニウム合金層の酸化を防止でき、マウントの強度が
極めて良好となり、信頼性の高い半導体装置を得ること
ができる。
(12) If the gold/germanium alloy layer is further coated with metal, it is possible to prevent the oxidation of the gold/germanium alloy layer 1' before mounting the semiconductor element, and the strength of the mount is extremely good, resulting in a highly reliable semiconductor. You can get the equipment.

(13)マウントに際し、370〜400℃の加熱温度
で半導体素子をニッケル層(もしくはニッケル合金層)
が被覆されたリードフレームに接触させ軽い圧力で振動
を与えることなくAu−Ge−Cuの三元合金層を形成
できるため、半導体素子への熱影響が少なく電気特定も
安定し、更に安定したマウントがなされた半導体装置を
得ることができる。
(13) When mounting, the semiconductor element is coated with a nickel layer (or nickel alloy layer) at a heating temperature of 370 to 400°C.
A ternary alloy layer of Au-Ge-Cu can be formed by contacting the lead frame coated with light pressure without vibration, so there is less thermal influence on the semiconductor element, electrical identification is stable, and the mount is more stable. A semiconductor device can be obtained.

(14)銀層の被覆が不要となるため、銀の欠点である
銀の硫化によるマウント接合強度の低下、銀層下の下地
の酸化を解消てき、リードフレームの保管時、マウント
時において細心の注意をはらうことなく、半導体素子を
リードフレームに強固に接合できる。
(14) Since there is no need to coat the lead frame with a silver layer, it eliminates the drawbacks of silver, such as the decrease in mount bonding strength due to silver sulfurization and the oxidation of the base under the silver layer. Semiconductor elements can be firmly bonded to lead frames without any precautions.

(15)金・ゲルマニウム合金層とリードフレームとの
マウントにより形成された接合層は金、ゲルマニウム、
銅の全率形の固溶体で、金属間化合物とならない。
(15) The bonding layer formed by mounting the gold/germanium alloy layer and the lead frame contains gold, germanium,
A solid solution of copper that does not form an intermetallic compound.

このため、接合層に金属間化合物ができないので、電気
抵抗が小さく、化学的に安定し、機械的強度の劣化のな
い高信頼性の半導体装置を得ることができる。また、リ
ードフレーム主面のニッケル層(もしくはニッケル合金
層)は酸化され易いが、接合層は金の拡散もしくは溶融
により貴金属化して酸化されにくくなる。更に空気中で
加熱酸化されても、金が拡散して貴金属層が広くなるた
め、酸化がマウント接合部には起こらない。なお、本発
明に係る半導体装置は、上記実施例の如くニッケル層が
主面に被覆された鉄素材からなるリードフレームを用い
る場合に限定されず、主面の層に関してはコパールなど
のニッケル合金層で形成し、素材については銅、銅合金
、コバルトなどで形成してもよい。
Therefore, since no intermetallic compound is formed in the bonding layer, a highly reliable semiconductor device with low electrical resistance, chemical stability, and no deterioration in mechanical strength can be obtained. Furthermore, although the nickel layer (or nickel alloy layer) on the main surface of the lead frame is easily oxidized, the bonding layer becomes a precious metal through diffusion or melting of gold and becomes less likely to be oxidized. Furthermore, even when heated and oxidized in air, oxidation does not occur at the mount joint because the gold diffuses and the noble metal layer becomes wider. Note that the semiconductor device according to the present invention is not limited to the case where a lead frame made of iron material whose main surface is coated with a nickel layer as in the above embodiment is used, and the main surface layer is a nickel alloy layer such as copal. The material may be copper, copper alloy, cobalt, etc.

また、ニッケル層もしくはニッケル合金層をリードフレ
ームの素材の主面のみならず全面に被覆してもよい。更
にリードフレームの素材は単層に限らず、積層構造でも
よい。本発明に係る半導体装置は上記実施例の如くNワ
イヤを用いる場合に限定されず、A1−Cuなどの合金
ワイヤを使用してもよい。
Further, the nickel layer or nickel alloy layer may be coated not only on the main surface but also on the entire surface of the lead frame material. Furthermore, the material of the lead frame is not limited to a single layer, and may have a laminated structure. The semiconductor device according to the present invention is not limited to using N wires as in the above embodiments, but may also use alloy wires such as A1-Cu.

本発明に係る半導体装置は上記実施例に示す如く、マウ
ント面にバナジウム、ニッケル、金・ゲルマニウム、金
の4層の金属層を積層した半導体素子を用い、この素子
をニッケル層が被覆されたリードフレームのアイランド
部にマウントした構造に限らず、半導体素子を金プリフ
ォーム体などのろう材、金共晶合金を介して銀ベース等
が被覆されたアイランド部にマウントしてもよい。
As shown in the above embodiment, the semiconductor device according to the present invention uses a semiconductor element in which four metal layers of vanadium, nickel, gold/germanium, and gold are laminated on the mounting surface, and this element is connected to a lead coated with a nickel layer. The semiconductor element is not limited to the structure in which it is mounted on the island part of the frame, but may be mounted on an island part covered with a silver base or the like via a brazing material such as a gold preform or a gold eutectic alloy.

つまり、本発明の半導体装置は金もしくは金合金のワイ
ヤがボンディングされる素子配設基材の主面がニッケル
層もしくはニッケル合金層で被覆されていることが必要
で、半導体素子のマウント部に必要に応じて群層を被覆
してもよい。本発明に係る半導体装置は上記実施例の如
く、素子配設基材としてリードフレームを用いた構造に
限らず、前述した第3図に示すハメテイツクシール構造
ものにも同様に適用できる。
In other words, in the semiconductor device of the present invention, it is necessary that the main surface of the element mounting base material to which the gold or gold alloy wire is bonded is coated with a nickel layer or a nickel alloy layer, which is necessary for the mounting part of the semiconductor element. Depending on the situation, a group layer may be applied. The semiconductor device according to the present invention is not limited to the structure using a lead frame as the element mounting base material as in the above-mentioned embodiments, but can be similarly applied to the above-described structure with a fit seal shown in FIG.

即ち、ベース、”エミッタ取出し電極となるステムのリ
ード線を、ヘッド部上面にニッケル層(もしくはニッケ
ル合金層)を被覆した構造にし、これにA1もしくはA
l合金のワイヤをボンディングし半導体装置を構成して
もよい。この場合、ステムの本体主面もニッケル層(も
しくはニッケル合金層)を被覆し、マウント面にバリア
金属層、金・ゲルマニウム合金層を順次積層した半導体
素子を用い、前記ステム本体にマウントしてもよい。以
上詳述した如く、本発明によれば主面にニッケルもしく
はニッケル合金層が被覆された素子配設基材を用い、こ
の場合にN電極を有する半導体素子をマウントすると共
に、該Al電極と前記基材主面のニッケルもしくはニッ
ケル合金層とをNもしくはAl合金のワイヤて接続する
ことにより、ペレットボンディング、ポストボンデ,イ
ンクが共に良好て、前述の(1)〜(5)に列挙した種
々の効果を有する安価て高信頼性の半導体装置を提供で
きるものである。
In other words, the lead wire of the stem, which serves as the base and emitter extraction electrode, is coated with a nickel layer (or nickel alloy layer) on the top surface of the head, and this is covered with A1 or A.
A semiconductor device may be constructed by bonding L alloy wires. In this case, the main body surface of the stem may also be coated with a nickel layer (or nickel alloy layer), and a semiconductor element may be mounted on the stem body using a semiconductor element in which a barrier metal layer and a gold/germanium alloy layer are successively laminated on the mounting surface. good. As described in detail above, according to the present invention, an element mounting base material whose main surface is coated with a nickel or nickel alloy layer is used, and in this case, a semiconductor element having an N electrode is mounted, and the Al electrode and the By connecting the nickel or nickel alloy layer on the main surface of the base material with N or Al alloy wire, pellet bonding, post bonding, and ink are all good, and the various effects listed in (1) to (5) above can be achieved. Accordingly, it is possible to provide an inexpensive and highly reliable semiconductor device having the following characteristics.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はシリコン半導体素子をリードフレーム2にマウ
ントし、かつ同素子とリードフレームのリード部とを金
ワイヤで接続した状態を示す斜視図、第2図は第1図の
リードフレームを樹脂封止し、カッティングした後の半
導体装置を示す断面図、第3図はハーメテイツクシール
構造の半導体装置を示す断面図、第4図は本発明の一実
施例を示すシリコン半導体素子をリードフレームにマウ
ントし、かつ同素子とリードフレームのリード部とをA
lワイヤで接続した状態を示す斜視図、第5図は第4図
のリードフレームを樹脂封止し、カッティング加工した
後の半導体装置を示す断面図、第6図は第4図の半導体
素子をマウントする前の状態を示す断面図である。 101・・・・・・リードフレーム、102・・・・ニ
ッケル層、103・・・・・アイランド部、104a,
104b・・・・・リード部、105・・・・・・バイ
ポーラ型シリコン半導体素子、110・・・・・・接合
層、111a,111b・・・・・・ベース、エミッタ
のA1電極、112a,112b・・・・A1ワイヤ、
113・・・・・・樹脂封止層。
Figure 1 is a perspective view showing a state in which a silicon semiconductor element is mounted on a lead frame 2 and the element and the lead portion of the lead frame are connected with gold wire, and Figure 2 is a perspective view of the lead frame shown in Figure 1 sealed with resin. 3 is a sectional view showing a semiconductor device with a hermetically sealed structure; FIG. 4 is a sectional view showing a semiconductor device having a hermetically sealed structure; and FIG. Mount the same element and the lead part of the lead frame at A.
FIG. 5 is a cross-sectional view showing the semiconductor device after the lead frame shown in FIG. 4 has been sealed with resin and cut, and FIG. 6 is a cross-sectional view showing the semiconductor device shown in FIG. 4. FIG. 3 is a sectional view showing a state before mounting. 101...Lead frame, 102...Nickel layer, 103...Island part, 104a,
104b... Lead portion, 105... Bipolar silicon semiconductor element, 110... Bonding layer, 111a, 111b... Base, emitter A1 electrode, 112a, 112b...A1 wire,
113...Resin sealing layer.

Claims (1)

【特許請求の範囲】[Claims] 1 少なくとも主面にニッケルもしくはニッケル合金の
層が被覆された金属素材からなる素子配設基材と、上面
に電極を有する半導体素子と、金属、金、ゲルマニウム
合金層、ニッケル層及びバナジウム層をこの順序で積層
した四層構造のろう材を用い、前記基材上に前記半導体
素子を前記ろう材をその金層が基材側に、バナジウム層
が半導体素子側に位置するように介在させた状態で還元
性雰囲気にてマウントし、かつ前記素子配設基材と前記
半導体素子の電極とをアルミニウムもしくはその合金の
ワイヤで還元性雰囲気にて接続したことを特徴とする半
導体装置。
1. An element mounting base material made of a metal material whose main surface is coated with a layer of nickel or nickel alloy, a semiconductor element having an electrode on the upper surface, and a metal, gold, germanium alloy layer, nickel layer, and vanadium layer. Using a four-layered brazing material laminated in sequence, the semiconductor element is interposed on the base material such that the gold layer is on the base material side and the vanadium layer is on the semiconductor element side. 1. A semiconductor device, wherein the semiconductor device is mounted in a reducing atmosphere, and the element mounting substrate and the electrode of the semiconductor element are connected with a wire made of aluminum or an alloy thereof in a reducing atmosphere.
JP55188888A 1980-12-26 1980-12-26 semiconductor equipment Expired JPS6057221B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55188888A JPS6057221B2 (en) 1980-12-26 1980-12-26 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55188888A JPS6057221B2 (en) 1980-12-26 1980-12-26 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS57111041A JPS57111041A (en) 1982-07-10
JPS6057221B2 true JPS6057221B2 (en) 1985-12-13

Family

ID=16231632

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55188888A Expired JPS6057221B2 (en) 1980-12-26 1980-12-26 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS6057221B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63192727U (en) * 1987-05-29 1988-12-12

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5877238A (en) * 1981-11-02 1983-05-10 Hitachi Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63192727U (en) * 1987-05-29 1988-12-12

Also Published As

Publication number Publication date
JPS57111041A (en) 1982-07-10

Similar Documents

Publication Publication Date Title
US5675177A (en) Ultra-thin noble metal coatings for electronic packaging
US7788800B2 (en) Method for fabricating a leadframe
US4675243A (en) Ceramic package for semiconductor devices
JPH07169901A (en) Integrated circuit package and lead frame
JPS632358A (en) Lead frame and plating of the same
JPH034030Y2 (en)
JPS6050343B2 (en) Lead frame for semiconductor device manufacturing
JPS6057221B2 (en) semiconductor equipment
JPS6074539A (en) Submount for optical semiconductor element
JPS6057219B2 (en) semiconductor equipment
JPS5936425B2 (en) Lead frame structure with intermediate layer
JPS5916353A (en) Lead frame
JP3733708B2 (en) Method for joining silicon wafers using aluminum
JPS6232622B2 (en)
JP2000068396A (en) Hermetic seal cover
JPS6124820B2 (en)
JPS6129142B2 (en)
JPS592175B2 (en) semiconductor equipment
JPS6143461A (en) Thin film multilayer interconnection substrate
JPS6057220B2 (en) semiconductor equipment
JPS60206054A (en) lead frame
JPS60218863A (en) Semiconductor lead frame
JPS5815252A (en) Bump structure
JPS6129139A (en) Semiconductor device
JPH06260577A (en) Coating structure of wiring electrode