JPS6059610B2 - Instruction processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an instruction processing method, and particularly to an instruction processing method that executes a given instruction by using in parallel a plurality of local memories each having a control memory and storing the same data. In the processing method, a control program routine that determines the usage pattern of the local memory as a whole is set in the control memory in advance, and a response is taken according to errors and check results for the read data of each local memory. The present invention relates to an instruction processing method configured to execute a control program routine to re-execute the above-mentioned instructions.

Generally, in a data processing system, when executing a given instruction, a plurality of local memories are prepared in which the same data is stored, and the data read from each local memory is processed and executed to execute the above instruction. There is an instruction processing method that executes the following.

In this type of instruction processing system, parity check processing is performed on data sequentially read from individual local memories, and when a parity error is detected, the instruction is re-executed. In other words, the local memory in which the parity error occurred is invalidated, and the data that should originally be read from the local memory in which the error occurred is read instead from the same location in another normal local memory, and the instruction is re-executed. will be carried out. Conventionally, when re-executing such an instruction, if a parity error as described above is detected, the program corresponding to the parity check result is rotated into the control memory addressed by the operation code section of the instruction. Then, the usage pattern of the local memory as a whole is determined by the load program, that is, a replacement memory for the local memory where the error has occurred is selected, and the instruction is re-executed.

Due to this program rotation, etc., a relatively large amount of time is consumed in the transition time from the point of error occurrence to the start of re-execution, which not only increases the overall instruction execution time but also increases the burden. The present invention aims to solve the above problems, and aims to sufficiently shorten the transition time with a simple configuration. Therefore, the instruction processing method of the present invention is equipped with a control memory, a plurality of memories in which the same data is stored, and an error check means for each memory. In an instruction processing method that re-executes the instruction based on the changed usage pattern, the instruction register in which the instruction is set and the instruction register that stores the same data as each other are usually accessed in parallel and their output is A first local memory and a second local memory in which arithmetic processing is performed, an error checking means for the first local memory, an error checking means for the second local memory, and the control memory. address input means into which an address is input, and a control memory in which a control program corresponding to the state of each of the above local memories is stored in advance; local
accessing the memory and the second local memory in parallel, and controlling the address set in the address input means based on the output of each error checking means of each local memory, The control memory is accessed in accordance with the check result by the error checking means to read a corresponding control program, and control is performed accordingly. An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

Figure 1A shows the configuration of an embodiment of the present invention;
3 and 3 are explanatory diagrams of the operating state of the present invention.

In the figure, 1 is the instruction register, and 2-1 is the first local register.
Memo I8 2-2 is the second local memory, 3-1 and 3-2 are the first local memories 2-1, respectively.
and a local memory address register (hereinafter referred to as LSA register) corresponding to the second local memory 2-2, 4 is a control memory, 5 is a control memory address register (hereinafter referred to as CSA register), and 6 is a Arithmetic circuits, 6-1 and 6-2 are output registers, 7
8 is a control circuit, 8 is a selection circuit, 9-1 and 9-2 are parity check circuits, 10-1 and 10-
2 are error flags, 11 is a +1 circuit, 12 is an OR gate, 13 and 14 are AND gates with negative inputs, respectively.
Gate, 15 represents a knot gate, respectively.

In FIG. 1, the instruction set in instruction register 1 is an operation code section (hereinafter referred to as 0PC section) 1-
1, a first local memory address section (hereinafter referred to as the first LSA section) 1-2, and a second local memory address section (hereinafter referred to as the second LSA section) 1-3, The 0PC section 1-1 constitutes a part of the specified address information for the control memory 4, and the first LSA section 1-2 and the second LSA section 1-3 constitute the first local memory 2-1.
and configures designated address information for the second local memory 2-2.

First local memory 2-1 and second local memory 2-1
The memories 2-2 store the same data. The control memory 4 is preset with a plurality of control program routines corresponding to error occurrence patterns as will be described later. The selection circuit 8 selects the first field A register 3-1 to which the first LSA section 1-2 and second LSA section 1-3 in the instruction are to be set based on the control signal from the control circuit 7. and/or select the second LSA register 3-2.
Error flags 10-1 and 10-2 are flip-flopped, respectively.
Consists of flops. The AND gate 13 with negative input outputs a write enable signal corresponding to the first local memory 2-1, and the other AND gate 14 with negative input corresponds to the second local memory 2-2. Outputs write enable signal. knot●gate 15
controls the instruction set operation for instruction register 1.
The processing operations in this embodiment are described below depending on whether or not there is an error as a result of the parity check: [1] Normal operation and [■]
This will be explained in order by dividing it roughly into when an abnormal operation occurs. [1] During normal operation (1) The 0PC section 1-1 in the instruction set in the instruction register 1 receives detection signals indicating a non-error state from the error flags 10-1 and 10-2, that is, ROJ and R.
Combined with OJ, address information ROpcOO is generated, and the address information ROpcOOJ is set in the CSA register 5 and the control memory 4 is accessed.

The control memory 4 stores a plurality of control program routines.
A normal operation control program routine corresponding to the address information ROpcOO, that is, a control program routine to be used during normal operation is read out from the control memory 4. (2) On the other hand, the first
of? The at[/s] signals input to the A section 1-2 and the second LSA section 1-3 are sent to the first LSA via the selection circuit 8, respectively.
Data set in register 3-1 and second LSA register 3-2 and accessed from first local memory 2-1 and second local memory 2-2 is read.

(3) The first question above? Read data (hereinafter abbreviated as first read data) read out based on the address signal input to the A section 1-2.

) and the read data (hereinafter abbreviated as second read data) read based on the address signal input to the second LSA section 1-3 are sent to the first parity check circuit 9-1 and the second parity check circuit 9-1, respectively. parity check circuit 9
-2, error checking is performed. (4) First
If both the parity check circuit 9-1 and the second parity check circuit 9-2 detect a non-error state, the second parity check circuit 9-1 and the second parity check circuit 9-1
Both output signals of parity check circuit 9-2 are still maintained at the logic ROJ level.

Therefore, the output signal of the NOT gate 15 via the OR gate 12 is still maintained at the logic RlJ level, which allows the next instruction to be set in the instruction register 1, and also the first error flag 10. Both the output signals of the second error flag 10-1 and the second error flag 10-2 are still maintained at the logical ROO level, and the lower two bits of the control memory 4 address information corresponding to the next instruction are ROOJ.
Set to . ]) If the results of these parity checks are both normal, the first read data is set to the output register 6-1 shown at the beginning of FIG. set to 6-2,
It is used as data to be operated on in the arithmetic circuit 6.

Here, the arithmetic circuit 6 performs arithmetic processing based on the normal operation control program routine read out from the control memory 4. The arithmetic result of the arithmetic processing is applied to the AND gate 13 with negative input and other AND gates with negative input.
Each logical RlJ write enable signal from gate 14 writes to the first local memory 2-1 and the second local memory 2-2. Old During abnormal operation 1) On the other hand, a parity error is detected by the first parity check circuit 9-1, and the second parity check circuit 9-1 detects a parity error.
If the check circuit 9-2 does not detect an error condition, the logic RlJ is output from the first parity check circuit 9-1.
is output.

This output signal inverts the output signal of the OR gate 12 to the logic RlJ level, inverts and maintains the output signal of the NOT gate 15 to the logic ROJ level, and inverts the output signal of the AND gate 13 with a negative input and other negative inputs. Each output signal of AND gate 14, ie, the write enable signal, is maintained at a logic level. Therefore, the next instruction is not set in the instruction register 1, that is, the instruction update process is prohibited, and the first readout from the first local memory 2-1 and the second local memory 2-2, respectively. The arithmetic results obtained by arithmetic processing on the data and the second read data are not written to the first local memory 2-1 and the second local memory 2-2. (2) Parity check circuit 9-
Logic from 1 01. The first error flag 1 is set by the J signal.
The 0-1 output signal is inverted to a logic RlJ level.

On the other hand, the output signal of the second error flag 10-2 is still the logic RO. ．． maintained at the level. The logic RlJ output signal of the first Eranipkegu 10--1 and the second
The logical ROJ output signal of the error flag 10-2 is added to the 0PC section 1-1 among the instructions still set in the instruction register 1 due to the above instruction update/update processing prohibition, and is added to the control memory ROpclOJ. Access address information is generated. This address information ROpcl
The corresponding first abnormal operation control program routine in the control memory 4 is read by OJ. The selection circuit 8 first selects the first ? in the instruction register 1 based on the first abnormal operation control program routine. A department doctor 1-
The address signal input to 2 is input to the second ? A register 3-2 is set to the second local memory 2-2.
The corresponding data, that is, the first read data is read from the output register 6-1 and set in the output register 6-1. Next, the selection circuit 8 converts the address signal input to the second LSA section 1-3 of the instruction register 1 into the second ? The second read data is read from the second local memory 2-2 and set in the output register 6-2. In this way, the output register 6-1
And when the first read data and the second read data set in 6-2 are in a non-error state, the arithmetic circuit 6 detects the first abnormal movement 3 for the first and second read data. Arithmetic processing is performed based on the action control program routine, and the result of the arithmetic operation is based on each logic r'1orite enable signal of the AND gate 13 with negative input and the other AND gate 14 with negative input. The first local memory 24-1 and the second local memory 24-1
is written to the local memory 2-2. When the first abnormal operation control program routine is thus completed, the control circuit 7 resets the error flag 10-1. As a result, setting processing corresponding to the next instruction to instruction register l, that is, instruction update processing, is permitted, and the first
, each logical RO of the second error flag 10-1, 10-2
In the command processing corresponding to the next command mentioned above, the control program for normal operation is read from the control memory 4.
The routine will be read. In this way, normal operation is automatically restored. 3) Also, the first parity check circuit 9-1 does not detect a parity error;
If a parity error is detected by the second parity check circuit 9-2, processing operations similar to those described above in (1) and (2) are performed.

That is, the correct first memory from the first local memory 2-1
The operation result based on the read data and the erroneous second read data from the second local memory 2-2 is input to each of the AND gate 13 with negative input and the other AND gate 4 with negative input. A write operation to the first and second local memories 2-1 and 2-2 is prohibited by the logical ROJ write enable signal. Further, the access address information for the control memory 4 is set as ROpcOlJ, and the second abnormal operation control program routine is read out from the control memory 4, and based on the program routine, the first
The first read data is first read out from the first local memory 2-1 and set in the output register 6-1, and then the second read data is set in the output register 6-1.
The read data is read out and set in the output register 6-2, and arithmetic processing is performed on these first and second read data. If these first and second read data are correct, the results of the arithmetic processing described above are written to the first and second local memories 2-1 and 2-2, and this second abnormal operation After the error flag 10-2 is reset at the end of the normal operation control program routine, the normal operation control program routine in the control memory 4 is read from the next instruction. ) If both the first parity check circuit 9-1 and the second parity check circuit 9-2 detect a parity error, the AND gate 13 with negative input and the other AND gate with negative input Each write enable signal on gate 14 is connected to logic RO. J level, and the calculation results for the erroneous first read data and the erroneous second read data are prohibited from being written to the first and second local memories 2-1 and 2-2. .

Further, the instruction update process is prohibited by the logic ROJ output signal of the NOT gate 15, and the 0PC part 1-1 and the first and second
The logic RlJ output signals of the error flags 10-1 and 10-2 cause 4 accesses to the control memory 10PC11J.
Address information is generated and error information is stored in the control memory 4.
A processing routine is read and the error processing routine is executed. Therefore, according to the present invention, in normal operation, as shown in FIG. 3A, arithmetic processing is performed in two data processing cycles, that is, τ. At , data is read from each local memory, and τ,
When an operation and its result are written in, even if there is an abnormality in one of the memories, the operation can be performed in three data processing cycles, as shown at the beginning of FIG. Note that the case shown in FIG. 3 indicates a case where an abnormal state exists in the data read from the second local memory 2-2, and the data read from the first local memory 2-1 at τ0 and τ1, respectively. It is shown that data is read and calculation and writing are performed at τ2. As explained above, the present invention provides a first local memory 2-1
and the second local memory 2-2 in parallel, and prepares in advance a plurality of control program routines (including an error handling routine) in the control memory 4 according to the pattern of the parity check results. Then, when a parity error occurs, the control program ●routine corresponding to the error pattern is switched to continue instruction processing.

For this reason, it is normally possible to access the first local memory 2-1 and the second local memory 2-2 in parallel and read different data from each in parallel, thereby increasing the processing speed of instructions. In addition, there is no need to consider the time and overhead of loading an alternative program into the control memory 1J4 from the time the error occurs, and instruction processing can be continued quickly. Although the above-mentioned embodiment represents the case where two local memories are used, the present invention is not limited to this and can be applied to an instruction processing method using three or more local memories. Be free.

[Brief explanation of the drawing]

Fig. 1A shows the configuration of an embodiment of the present invention, Fig. 1 shows the connection state of the output register in the arithmetic circuit, and Figs. In the figure, 1 is an instruction register, 2-1 is a first local memory, 2-2 is a second local memory, and 3-1 and 3-2 are the first local memory and the first local memory, respectively. The local ● memory ● address ● register corresponding to the local memory 2, 4 is the control memory, and 5 is the control memory.
Address Register, 6 is an arithmetic circuit, 6-1 and 6-2 are each an output register, 7 is a control circuit, 8 is a selection L circuit, 9-1 and 9-2 are each a parity check circuit,
10-1 and 10-2 are error flags, 11 is +
One circuit is shown respectively.

Claims (1)

[Claims] 1. A control memory, a plurality of memories in which the same data is stored, and an error check means for each memory, and a usage pattern of the entire memory can be determined based on the correctness of the read data of each memory. In an instruction processing method that re-executes an instruction based on the usage pattern after the change, the instruction register in which the instruction is set and the instruction register each store the same data and are usually accessed in parallel and perform operations based on their outputs. A first local memory and a second local memory in which processing is performed, an error check means for the first local memory, an error check means for the second local memory, and a first local memory for the control memory. An address input means into which an address is input, and a control memory in which a control program corresponding to the state of each of the above local memories is stored in advance are provided. Local memory and second
while accessing the local memory of
The address set in the address input means is controlled based on the output of each of the error checking means of each of the local memories, and the control memory is accessed according to the check result by the error checking means. An instruction processing method characterized in that a corresponding control program is read and control is performed accordingly.