JPS605985B2 - Input/Output Interface Control Method - Google Patents

Description

Description: The present invention relates to a channel unit for controlling an input/output interface in a data processing device.

In a data processing device, when signals are sent and received over an input/output interface between a channel device and an input/output control device, if the control sequence of the interface malfunctions, it is difficult to detect all of the malfunctions due to the large number of combinations involved.

Furthermore, there are drawbacks in that it is difficult to set the time period during which asynchronous signals such as interrupt signals are permitted to be accepted, and that the channel response time for asynchronous signals is too long. At the same time, there is also a drawback in that the logic for determining the priority of signals sent to the interface is fixed. The object of the present invention is to solve the drawbacks of the prior art described above by coding the interface control signal and the check signal, and to perform detailed checks for sequence malfunctions, particularly for the case where a signal (OUT signal) is sent from the channel device to the control device, but the W signal (signal from the control device to the channel device) corresponding to the OUT signal has already been sent at the time the signal was sent, the case where an asynchronous IN signal is sent in the middle of the sequence even though it should not be sent, and the case where an expected signal is sent from the control device, but at the same time another unexpected signal is sent.

A further object of the present invention is to facilitate the control of an input/output interface having many branches.

In order to achieve the above object, in this invention, a sequence word is defined as a coded input/output interface control signal and a check signal, and the sequence word is prepared in a sequence stack in accordance with the order of the interface sequence before a channel starts the input/output control device.

After the channel is started, the sequence word indicated by the sequence counter is read into the sequence register to control and check the input/output interface signals in sequence. Also, the sequence counter is updated every 10 seconds.
In principle, when an asynchronous signal or multiple signals are raised at the same time, a sequence counter is updated according to the bit position of the sequence register in order to perform branch control, and subsequent processing is performed according to the instructions of the sequence word of the branch destination. The contents of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an example of the bit structure of a sequence word used in the present invention.

In this example, bit positions 0 to 4 of the 12-bit bit configuration indicate either an OUT signal or an m signal. Bit position 5 is an OUT/IN control bit, and when this bit is "0", it means that the signals corresponding to bit positions 0 to 4 are calm signals (SIo to SL), and when this bit is "1", the signals corresponding to bit positions 0 to 4 are OUT signals (S0o to S04).
The BR bit in bit position 6 means
When it is unclear from which bit position the IN signal comes, the type of W signal is used to determine whether or not to give permission to update the sequence counter (described later). Bit positions 7 to 11 specify the check signal, and each of C4 to Co is S04.
2 shows a configuration in which asynchronous signals are not handled in one embodiment of the present invention.

In the channel program, before an input/output operation instruction is issued from the program and the input/output control device is actually started, a series of interface control OUT signals,
The sequence words, which are the coded signals and the check signals and which are explained in FIG. 1, are transferred from the main memory or the control memory into the sequence stack 1 in a predetermined order.
Thereafter, when the input/output control device is actually started, the sequence word corresponding to the stack address indicated by the sequence counter 2 is read from the sequence stack 1 and set in the sequence register 3. In the example of FIG.
Since the OUT/IN control bit at bit position 5 of the sequence register 3 is "0", it specifies waiting for the IN signal.
Since bit position 0 is "1", it specifies waiting for the SI signal. Also, since bit positions 8 and 9 are both "1", when the channel specifies waiting for the SL signal, S
If the SI or SI2 signal rises improperly or if the SI or SI2 signal rises improperly while waiting for the SI signal, an error flip-flop 7 is performed at the timing of T2.
By setting the , you can check for sequence malfunctions. The check signals in bit positions 7 to 11 can be specified arbitrarily, allowing for detailed checking.
When the RROR-P signal 6 is generated, the error flip-flop 7 is frozen, which makes it easier to analyze the error. When the SL signal is normally sent from the control device,
At the timing T, the ADDI-P signal 5 is output, and the adder circuit 10 increments the sequence counter 2, and the sequence word stored in the next stack address is set from the sequence stack 1 to the sequence register 3.
The process proceeds to the next interface control. When bit position 5 is "1", that is, when an OUT signal is specified, the control method is as follows:
According to the designation of SO. to SQ, any signal from SO. to SQ is sent, and at the timing of T., the ADDI-P signal is output and the process proceeds to the next sequence. In this case, it is also possible to test the state of the IN signal by using a check code. 4 is an OUT/IN control gate, and 11 is a timing generation circuit that creates the timing signals T, and T2. Figure 3 shows another embodiment of the present invention, in which the wait designation of the m signal in Figure 2 is expanded so that it can be applied to multiple signals.

Circuits related to check codes are omitted. For the sake of convenience, in order to simplify the following explanation, it is assumed that even if there are multiple wait specifications, only one signal is actually sent from the control device. As in the case of FIG. 2, a series of sequence words are stored in the sequence stack 12, and when the input/output control device is actually started, the sequence word corresponding to the stack address indicated by the sequence counter 13 is set in the sequence register 14. In the example of FIG. 3, bit position 5 of the sequence word set in the sequence register 14 is "0" and bit positions 2, 3, and 4 are "1", so SI2, SI3, SL
Since bit position 6 is "1", the branch control gate 16 operates to send one of the three signals SI1, SI2, and SI3.
When any of the SI3 and SI4 signals is sent, the ADD4-P signal 19, the ADD8-P signal 18, and the A
The DD 16-P signal 17 is generated at the timing of T3.
When any of the above signals occurs, the adder circuit 20 updates the sequence counter 13. The updated sequence counter matches the address of the sequence word that the channel program prepared in the sequence stack 12 before performing an I/O operation.
The timing signals T, T2, and T3 are generated by a timing generation circuit 22. Although the time-over monitoring of the interface signal is omitted in FIG. 3, a group of sequence words instructing the processing after a time-out is prepared at a predetermined sequence stack address, and when the I/O signal times out, the sequence counter 13 is incremented by a predetermined count, and the sequence stack 1 is reset in advance.
It is clear that processing can continue by accessing the sequence word stored in .2.

In addition, in the embodiment, whether or not to stop timing when an error occurs can be determined by an external switch or by providing a control bit corresponding to the external switch in the sequence word, but details will be omitted.

As is clear from the above description, according to the present invention, the checking of signals in the transmission and reception of signals in an input/output interface can be performed in a detailed manner by specifying the expected signals and the expected signals on a signal-by-signal basis.

Additionally, asynchronous signals can be easily masked out or enabled for any period of time.

[Brief description of the drawings]

Fig. 1 shows the bit structure of a sequence word used in the input/output interface control method of the present invention, Fig. 2 shows an embodiment of the present invention when asynchronous signals are not handled, and Fig. 3 shows an embodiment of the present invention when asynchronous signals are handled. In Fig. 2: 1... sequence stack, 2... sequence counter, 3... sequence register, 4...
OUT/IN control gate, 7: error flip-flop, 10: adder circuit, 11:
Timing generation circuit, in FIG. 3: 12... sequence stack, 13... sequence counter, 14...
. . sequence register, 15 . . . OUT//IN control gate, 16 . . . branch control gate, 20
. . . adder circuit, 21 . . . timing generation circuit.

Claims (1)

[Claims] 1. In a channel device which controls an input/output control device, sequence words consisting of control signals and check signals of an input/output interface between said channel device and said input/output control device are stored in a memory means in accordance with the order of the input/output interface control sequence, and the sequence words in said memory means are read out sequentially by an address means;
An input/output interface control system as claimed in claim 1, characterized in that, while sending the control signal to said input/output interface, the check signal in said sequence word is compared with the signal sent from the input/output control device to check the operation of the input/output interface. 2. An input/output interface control system as claimed in claim 1, characterized in that a match is found between the control signal line in said sequence word and the signal sent from the input/output control device, thereby controlling the updating of said address means.