JPS605986B2 - Input/output control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input/output control method that allows maintenance and diagnosis of a standby system to be easily performed.

In a system in which the central processing unit, main memory, and input/output control unit are connected by a common bus, and multiple input/output devices are connected to the input/output control unit, the central processing unit and its central processing unit are Between the device register provided in the input/output control device to control the input/output control layer, and between the central processing unit and the input/output device to control the input/output device provided in the input/output control device. a control route according to a program mode between a subchannel control memory having an area of
It is common to have a program mode and direct memory access mode control route between the main memory and the subchannel control memory. In such a system, if the input/output control device is configured in a redundant configuration, the active system and the backup system generally use the same address, so the input/output control unit that has become the backup system will The device could not be accessed from the central processing unit.

In this case, by making the addresses of the input/output control devices in the active system and the backup system different, it becomes possible to access the input/output control device that has become the backup system. However, since the number of addresses is doubled, this becomes impractical when a large number of input/output devices are accommodated. The present invention has a simple configuration, and
The purpose of this system is to allow the central processing unit to access the subchannel control memory via the device register of the input/output control unit, thereby making it possible to perform maintenance and diagnosis of the backup input/output control unit. be.

Examples will be described in detail below. FIG. 1 is a block diagram of an embodiment of the present invention, in which a central processing unit CPU, a main memory device MM, and an input/output control device CC are connected to a common bus CB.
The input/output control device CC connected by US is provided with a device register UR for storing a device control word and a subchannel control memory SCM having an area corresponding to the input/output devices, and includes input/output devices #0 to #n. 1/0 is the central processing unit CPU
It is controlled in a time-division manner by the input/output control device CC.

The control routes shown by dashed lines are generally shown by ■ to ■, where the control route (■) is between the central processing unit CPU and the device register UR, and the control route (■) is between the central processing unit CPU and the subchannel control memory SCM. The control route (3) is between the main memory device MM and the subchannel control memory SCM, and the present invention further provides a control route A indicated by a dotted line, that is, the central processing unit CPU and the subchannel control memory SC.
This allows a route between the device and the device M via the device register UR.

The device register UR that stores device control words usually includes a program key register section PK and a control register section C.
It consists of TR and an interruption register section mR.

FIG. 2 shows the configuration of the device register UR in the embodiment of the present invention. In addition to PK, CTR, and INR, a maintenance register section DR is provided, and a program key register section PK is also provided for maintenance purposes. It is also used as a memory address storage unit. A unit activation bit UA is formed in the control register CTR as an indicator indicating whether the program key register PK is valid as a maintenance memory address storage. Normal control consists of a program key register section PK, a control register section CTR, and an interrupt register section m.
This is done by R.

Furthermore, as mentioned above, the unit activation bit UA constitutes a display unit that displays the validity/invalidity of the maintenance memory address storage unit, and for example, it is valid when it is “0” and invalid when it is “1”. If so, the program key register section PK is used as a memory address storage section for maintenance, and stores the address of the subchannel control memory SCM to be accessed by the central processing unit CPU during maintenance operations. be. Negotiation of the subchannel control memory SCM by control route A is performed as follows.

That is, during maintenance operation, the central processing unit CPU writes the address of the subchannel control memory SCM to be taken as a maintenance address to the program key register PK of the installed register UR via the control route (2), and then the central processing An export command is executed from the device CPU to the maintenance register section DR of the device register UR through the control route (2). At this time, if the unit activation bit UA is "0", it is valid as a maintenance memory address storage section, so the subchannel control memory SCM is accessed by the maintenance address set in the program key register section PK. Read the contents to the maintenance register PR
The data is transferred to the central processing unit CPU. For writing to the subchannel control memory SCM via control route A, the address of the subchannel control memory SCM to be written is sent from the central processing unit CPU to the program key register section FK of the device register UR as a maintenance address.
Then, a write command is executed from the central processing unit CPU to the maintenance register section DR of the device register UR using the control route (2).

At this time, the unit activation pit UA is “0”
If so, since it is effective as a maintenance memory address storage section, the subchannel control memory SCM is accessed and written using the maintenance address set in the program key register section PK. By using the control route A as described above, maintenance diagnosis of the standby system becomes easy.

For example, as shown in FIG. 3, input/output control devices CCo, CC. In the device register URo,U
R, have the same address, and one input/output control device CC
When o becomes the active system and the other input/output control device CC becomes the standby system, the unit activate bit UA of the device register URo is set to "1", and the unit activate bit UA of the device register UR is set to "0". ”, and the first
As explained with reference to the figure, data transfer is performed on the control routes (1) to (2). Also, for the backup input/output control device CC, the address of the subchannel control memory SCM, is the same as the address of the subchannel control memory SCMo of the active input/output control device CCo, so the active input/output control device CC, The central processing unit CPU that controls the control device tCo is
The hardware configuration does not allow data transfer between the subchannel control memory SCM of the backup input/output controller CC, and normally the subchannel of the central processing unit CPU and the backup input/output controller CC. Control memory S
Although it is impossible to transfer data between the CM and the CM, the data transfer becomes possible by using the control route A described above. That is, the standby device register UR.
By setting the address of the subchannel control memory SCM of the program key register part PK as a maintenance address and executing a read command or a write command to the maintenance register part DR, the unit of the device register UR is activated. Since bit UA is "0", data transfer is possible via control route A.

By using this control route A as a diagnostic route, maintenance diagnosis of the standby input/output control device can be performed by the online central processing unit. FIG. 4 is a block diagram of the aforementioned input/output control device, where the same reference numerals as in FIG. Department,
DBUS is data bus, ABUS is address bus, WR
is a working register that extracts and sets data in the subchannel control memory SCM required during control, BR is a buffer register that temporarily stores data between input/output devices 1/0, and DET detects a maintenance address. AC is an address counter for time-division control of each subchannel, ADC is an address control unit, AD is an address decoder, M is a multiplexer, and WAD is a divider. The interrupt address and MAT are interrupt data.

The device register UR is composed of a program key register part PK, a control register part CTR, an interruption register part R, and a maintenance register part DR. There is no substance as such. The unit activation bit UA in the control register section CTR is set when the control route A is not required as described above.
For example, it is rewritten to "1" in the case of the active system, and "0" if the control route A is required, for example, in the case of the backup system.

When the unit activation bit UA is "0", the program key register section PK becomes effective as a maintenance address storage section. When data is transferred via control route A, the address of the program key register section PK and the address of the subchannel control memory SCM as data are sent and written as maintenance addresses from the central processing unit CPU, and are used for the next maintenance. A read command or a write command is executed to the address of the register unit DR.

When the maintenance address detection unit PET detects the address of the maintenance register unit DR, it opens the root gate of the program key register unit PK of the address bus ABUS and reads the maintenance address written in the program key register PK. In addition to the subchannel control memory SCM, data is written from the central processing unit CPU to the subchannel control memory SCM via the data bus DBUS, or data read from the subchannel control memory SCM is transferred to the central processing unit CPU. When data is transferred using the normal route as the active system, the subchannel control memory SCM is accessed via the address bus ABUS by the address from the common bus CBUS, and the subchannel control memory SCM is accessed via the address bus ABUS, and the subchannel control memory SCM is transferred to the central processing unit CPU or main memory MM. Common bus CBUS and data bus DBU with memory SCM
Data transfer takes place via S.

On the other hand, in the case of internal processing in the input/output control device CC, the subchannel control memory SCM is accessed by the address from the address counter AC, and the subchannel control memory SCM is accessed by the address from the address counter AC.
Data is transferred between the decoded and designated input/output device 1/0 via the buffer register BR and the multiplexer MX. As explained above, the present invention provides an input/output control device CC with a maintenance memory address storage section including a program key register section PK for storing maintenance addresses, a maintenance register section DR, and a maintenance memory address storage section. The input/output device 1 of the input/output control device CC from the central processing unit CPU is provided with a display unit such as a unit activation pit UA that displays the validity/invalidity of the storage unit.
Subchannel control memory SCM with area corresponding to /0
When direct access to central processing unit C is disabled,
The maintenance memory address storage section is enabled from the PU and displayed on the display section consisting of the unit activation bit UA, etc., and the address of the subchannel control memory SCM is set as the maintenance address in the maintenance memory address storage section. It executes a write command or a write command using the address as the address, and transfers data between the subchannel control memory SCM and the central processing unit CPU. In a system provided with a standby system, the input/output control device that has become a standby system can be maintained and diagnosed from the online central processing unit CPU.

In addition, the configuration for performing such control only requires a memory address storage section for maintenance and a display section to display its validity/invalidity, so the configuration does not become complicated.
The practical effects are very large.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is an explanatory diagram of the device register, Fig. 3 is an explanatory diagram of maintenance diagnosis of the standby system,
FIG. 4 is a block diagram of main parts of an input/output control device according to an embodiment of the present invention. CPU is the central processing unit, MM is the main memory, CBUS is the common bus, CC is the input/output control device, UR is the device register, SCM is the subchannel control memory, 1/0 is the input/output device, PK is the program key register section , CTR is the control register section, UA is the unit activation bit, INR is the interaction register section, DR is the maintenance register section, and DET is the maintenance address detection section "ADC".
is an address control section, AC is an address counter, WR is a working register, BR is a buffer register, CTL is a channel control section, and AD is an address decoder. Figure O Figure O 2 Figure O 3 Figure O 4

Claims (1)

[Claims] 1. In an input/output control method in which a central processing unit, a main storage device, and an input/output control device are connected via a common bus, and the input/output devices connected to the input/output control device are controlled, The device is provided with a maintenance memory address storage unit that stores maintenance addresses, a maintenance register unit that stores data during maintenance operations, and a display unit that displays validity/invalidity of the maintenance memory address storage unit, When direct access from the central processing unit to a subchannel control memory having an area corresponding to an input/output device of the input/output control device is disabled, the maintenance memory address storage unit is enabled from the central processing unit and the display unit and setting the address of the subchannel control memory as a maintenance address in the maintenance memory address storage section;
An input/output control method characterized in that a read command or a write command is executed using the maintenance address as an address, and data is transferred between the subchannel control memory and the central processing unit.