JPS6114692B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention counts and digitally displays the number of pulses of an input signal included within the time range of a reference pulse, and also automatically changes the unit of the number of digital display digits during measurement. This is a simple counter that can be used to

With conventional devices of this type, it is difficult to provide counting digits over the entire frequency band used, so when measuring an unknown input signal in any range, overflow or pulse counting digits may be insufficient. In this case, it is necessary to switch to the required range and perform the measurement again, and if the number of pulses in the input signal is unpredictable, the pulse counting operation becomes very complicated. Some devices switch to the required range, but if the counting circuit overflows, it will count again at the next gate time, so if the frequency stability of the input signal is poor, the display will not be constant, making it difficult to identify the input signal. The drawback was that it was difficult to do.

In order to eliminate the above-mentioned drawbacks, the present invention provides a device for counting and digitally displaying the number of pulses of an input signal, which includes a frequency dividing circuit that divides the number of pulses of the input signal and an output of an input gate. a counting display circuit that counts and displays the counting result on a display circuit; a switching circuit that switches the frequency dividing circuit to the one with a higher frequency division ratio due to an overflow of the final stage of the counting circuit of the counting display circuit; By using the device according to the present invention, it is characterized by comprising an adding circuit for setting the minimum number of units in the stage counting circuit, and a digit shifting circuit for changing the units in the counting circuit. , there is an advantage that the operation of counting the number of pulses of the input signal included within the time range of the reference pulse is facilitated.

The present invention will be explained in detail below. The figure is a block diagram of an embodiment according to the present invention. In the figure, 1 is a reference pulse generation circuit, 2 is an AND gate, 3, 4, and 5 are counting circuits, 6 is a display circuit, 7 is a differential circuit, and 8 is a differential circuit. 10 is a switching circuit, 11 is a digit shift circuit, 12 is an input terminal to which an input signal is applied, 13, 14 and 15 are frequency dividing circuits, and 16 is an automatic reset circuit. The output of the reference pulse generation circuit 1 is connected to one input of the AND gate 2 and also to the automatic reset circuit 16, and since the reference pulse is generated by the input signal applied to the input terminal 12, the rising edge of the reference pulse is Then, the counting circuits 3, 4, 5 and the memory circuit 9 are reset. On the other hand, the output of the switching circuit 10 is applied to the other input of the AND gate circuit 2. The output of the AND gate circuit 2 is sequentially applied to counting circuits 3, 4, and 5, and the contents of the counting circuits 3, 4, and 5 are displayed by a display circuit 6 in three decimal digits. When the final stage counting circuit 5 overflows, the overflow signal is differentiated by the differentiating circuit 7, one of the differentiated signals is applied to the adding circuit 8, and the output of the adding circuit 8 is applied to the final stage counting circuit 5. and causes the display circuit 6 to display the minimum unit number (numerical value "1"). At the same time, the output of the differentiating circuit 7 is applied to a memory circuit 9, the output of this memory circuit 9 is commonly connected to the switching circuit 10 and the digit shift circuit 11, and the output of the digit shift circuit 11 is applied to the digital display digit of the display circuit 6. Change the units of numbers. The input signal applied to the input terminal is sequentially frequency-divided by the frequency dividing circuits 13, 14, and 15, and the output of each frequency dividing circuit is applied to the switching circuit 10, respectively. The output of the switching circuit 10 switches the outputs of the three-stage frequency dividing circuits 13, 14, and 15 from the one with a lower frequency division ratio to the one with a higher frequency division ratio according to the output of the memory circuit 9.
It is applied to the other input of the AND gate 2, and is led to the first stage counting circuit 3 only when there is time width information.
Therefore, the number of input signal pulses included within the time width of the reference pulse can be counted and digitally displayed using the minimum number of digits, and the unit of the number of digital display digits can be automatically changed during measurement. Therefore, there is an effect that measurement and operation of the measuring device are extremely simple.

[Brief explanation of the drawing]

The figure is a block diagram of one embodiment of the present invention. 1... Reference pulse generation circuit, 2... AND gate, 3, 4, 5... Counting circuit, 6... Display circuit,
10...Switching circuit, 12...Input terminal, 13,1
4, 15... Frequency dividing circuit.

Claims (1)

[Claims] In a device that gates an input signal with a reference pulse and counts the number of pulses of the input signal included within the time range of the reference pulse, the device includes a frequency dividing circuit that divides the frequency of the input signal pulse, and a frequency division circuit that divides the frequency of the input signal pulse; A counting display circuit including a multi-stage counting circuit that counts the number of pulses of the included input signal and a display circuit that displays the counting result, and an overflow signal of the final stage counting circuit of the counting display circuit, the frequency dividing circuit a switching circuit that switches to the one with a higher frequency division ratio;
A counter comprising: an adder circuit that sets a minimum unit number in the final stage counting circuit based on the overflow signal; and a digit shift circuit that changes units in the plurality of counting circuits based on the overflow signal. .