JPS6116082B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control circuit using memories such as ROM and RAM.

Generally, as shown in Fig. 1, a data output terminal _D0 of a memory M' such as ROM or RAM is connected to an address input terminal _A0 to form a so-called feedback loop, and a holding circuit as shown in Fig. 2 is connected. When configuring a memory card, data may be written in advance to each address as shown in FIG. That is, in this case, if address input A ₁ becomes H level, data outputs D ₀ and D ₁ become H level, and even if address input A ₁ returns to L level, address input A ₀ is at H level, so the address The output state, that is, both data outputs D ₀ and D ₁ maintain the H level state until the input A ₂ becomes H level. This operating state is determined by inputting the open/close signal of the a contact X ₀ to the address input A ₁ , the open/close signal of the b contact X ₁ to the address input A ₂ , and the operation of the exciting coil Y ₀ to the data output D ₁ in the holding circuit shown in FIG. This corresponds to the operation of this holding circuit when replaced, and more specifically, H is applied to contact X ₀ .
When a level signal is applied, the a contact X ₀ closes, the excitation coil Y ₀ is excited (H level), and at the same time the other a contact Y ₀ ', which is a self-holding contact, closes (H level). Therefore, even if the a contact X ₀ is open (L level), the b
Unless the contact X ₁ is opened (unless it becomes H level), the states of the exciting coil Y ₀ and its a contact Y ₀ ' do not change.

In this way, a control circuit such as the holding circuit can be realized by the configuration shown in FIG. 1 having a feedback loop, but a control circuit such as the one shown in _FIG . ₁ , a feedback loop is not required in a circuit in which excitation coils Y ₀ are connected in series, so if the configuration shown in Figure 1 is used as is, address input A ₀ and data output D ₀ will not be used, and memory M The disadvantage is that the usage efficiency of ' is poor.

The present invention has been proposed in view of the above points, and its purpose is to provide data output in an open collector format when a memory such as ROM or RAM is used as a logic circuit to control various devices. Create a feedback loop between an appropriate number of data output terminals and address input terminals using memory such as ROM or RAM, and store data in advance so that the data output is always at the H level when the feedback signal is not required. By writing the address input into the memory, the address input containing the feedback signal can be used as an external input, increasing the efficiency of address input use, and making it easier to configure various control circuits depending on the content of the data written to the memory. An object of the present invention is to provide a control circuit using a memory that can be configured as follows.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 5 constitutes a control circuit according to the present invention.
A memory M such as ROM or RAM is shown, and its data output terminal D ₀ is connected to an address input terminal A ₀ to form a feedback loop. This address input terminal _A0 is different from the conventional example shown in FIG. 1, and allows address input. Further, the data output terminal _D0 is connected to a power supply via a pull-up resistor R. Note that the number and position of the feedback loops and pull-up resistors R are not limited to those in this embodiment; for example, a plurality of data output terminals D ₀ , D ₁ , D ₂ . . . Address input terminals A ₀ , A ₁ , A ₂ ……………
By forming a feedback loop between each address input terminal A ₀ , A , and connecting a pull-up resistor R to each data output terminal D ₀ , D ₁ , D ₂ . ₁ , A _{2 .} . . , so that address input from the outside can also be applied. Furthermore, the data output of the memory M needs to be in an open collector format.

In order to operate the holding circuit shown in FIG. 2 in the memory M according to the present invention, the signal applied to the address input A ₁ as in the conventional example is changed to the opening/closing signal of the a contact X ₀ and the address input A Let the signal applied to ₂ be the opening/closing signal of the b contact X ₁ , and
The data shown in FIG. 3 can be written into the memory M in the same way as in the conventional example, using the data output D ₁ as an operating signal for _the exciting coil Y ₀ and as an opening/closing signal for its a-contact Y 0 '.

Furthermore, in order to operate _the control circuit shown in FIG _.
The signal applied to address input A ₁ is the opening/closing signal of contact B contact X ₁ , and the data output D ₁
The data shown in FIG. 6 is written as the operation signal for the exciting coil _Y0 .

Here, since the data output of the memory M is in an open collector format, if an H level is written to the data output D ₀ in advance by opening the final stage transistor that provides the data output D ₀ , the address Input A ₀ is simply data output D ₀
It is the same as if the pull-up resistor R on the side is connected, and the address input A ₀ goes to H level according to the applied address signal, regardless of the level (H level) of the data output D ₀ in the feedback loop. Or it becomes L level. Therefore, data output D ₁ depending on the input level of address inputs A ₀ and A ₁
changes as shown in FIG _. 6, and the data output D1 becomes H level only when address input _A0 is at H level and address input _A1 is at L level. This operation is a
The circuit operation of FIG. 4 is shown in which the excitation coil _Y0 is energized (H level) only when the contact _X0 is closed (H level) and the b contact _X1 is closed (L level).

In addition, in the present invention, data output for feedback
Although D ₀ becomes unusable, the number of outputs in a control circuit is generally much smaller than the number of inputs, so even if data output D ₀ becomes unusable, other data outputs D ₁ , D ₂ …………… There are almost no problems as it can be used.

As described above, according to the present invention, a feedback loop is formed by connecting an appropriate number of data output terminals of an open collector type memory to an appropriate number of address input terminals capable of inputting an address from the outside. At the same time, since the data output terminal constituting the feedback loop is connected to the power supply via a pull-up resistor, the address input of the memory can be used both as a feedback input and as an external signal input. , the number of address inputs is not reduced depending on the type of control circuit to be configured, and the efficiency of address input usage can be increased, and various control circuits can be easily configured by changing the data written to the memory. It has effects such as being able to be configured as follows.

[Brief explanation of the drawing]

Figure 1 is a connection diagram of a memory that constitutes a conventional control circuit, Figure 2 is a circuit diagram of a holding circuit, and Figure 3 is a diagram of a memory that constitutes a conventional control circuit.
4 is a circuit diagram of the control circuit, FIG. 5 is a connection diagram of the memory constituting the control circuit according to the present invention, and FIG. 6 is a truth table in FIGS. 4 and 5. It is a truth table. M...Memory, R...Pull-up resistor, X ₀ ...
...A contact, X ₁ ...B contact, Y ₀ ...excitation coil,
Y ₀ ′...A contact.

Claims (1)

[Claims] 1. A memory is regarded as a logic circuit, and an address input terminal of the memory is an input terminal of the logic circuit,
The data output terminal of the memory is used as an output terminal of the logic circuit, a desired signal stored in advance is generated at the output terminal according to the state of a signal applied to the input terminal, and the device is controlled by this signal. In the control circuit, the data output terminal of the memory is an open collector type, and a feedback loop is provided between the data output terminal and the address input terminal for self-holding operation.The data output terminal is connected to the power supply via a pull-up resistor. When connected and the feedback loop is applied, the corresponding address input terminal is not used in an open state, and when the feedback loop is not used, the data is written so that the corresponding data output terminal is always at a high level. A control circuit using a memory characterized in that a corresponding address input terminal is used as a normal input terminal.