JPS6116998B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an improvement in an electronic musical instrument that utilizes digital technology and is equipped with a coupler control circuit, and particularly relates to an electronic musical instrument that achieves a desired coupler effect while shortening one scanning period of a key switch. This applicant previously provided an electronic musical instrument of the invention described in the specification of Japanese Patent Application No. 52-150895 (Japanese Unexamined Patent Publication No. 54-83419) entitled "Electronic Musical Instrument." To summarize the invention, the key switches of a plurality of keys are sequentially scanned at a predetermined speed to generate a time division multiplexed signal indicating the key depression state of each key at each time slot corresponding to each key within one scanning period, In addition, in synchronization with this key switch scanning, a waveform signal corresponding to each key is generated in a time-division manner for each of the time slots, and the above-mentioned time-division multiplexed signal and this time-division multiplexed signal are further delayed by a predetermined time by a coupler control circuit. The electronic device is characterized in that the obtained signals are outputted as weighted signals that are weighted according to the set positions of the corresponding controls, and the weighted signals and the waveform signals are multiplied to obtain musical tone signals. It's a musical instrument. With such a simple configuration, this electronic musical instrument has the excellent feature of being able to simultaneously generate a large number of musical tones in response to all pressed keys. By the way, in the case of this electronic musical instrument, there are 61 keys C ₁ ~
C ₆ is provided, and the key switch is sequentially scanned starting with the key C ₁ with a low pitch to detect the key press state. Also 1
The scanning period is set for 120 bit times (120 time slots), and the time-division multiplexed signal of 61 keys (this signal is output as a "1" signal if the key is pressed; otherwise, it is output as a "1" signal). (eg, output as a "0" signal) is output in 61 time slots in the first half of this one scanning period. Furthermore, the coupler control circuit includes a plurality of delay circuits that are directly connected to each other (the total capacity of these delay circuits is 48 stages/1 bit), and weighting circuits that are respectively connected to these delay circuits and the operator. is provided. The time-division multiplexed signal is input to the first delay circuit, then sequentially sent to the rear delay circuits, output from each delay circuit, and then input to the weighting circuit. Further, the total delay time during which the time division multiplexed signal ("1" signal) for a certain pressed key is delayed by the delay circuit is 48 bit times. In other words, in the case of the electronic musical instrument of the prior invention, the total delay time of the delay circuit is set to 48 bit times in order to be able to produce as a coupler tone a musical tone up to a pitch four octaves higher than the pitch of each key. ing. Also, since the time required for key switch scanning is 61 bit times, the actual required period of the one scanning period (120 bit times) is
This is 61 bit time plus 48 bit time, which is 109 bit time, and the latter 11 bit time (the remaining period after subtracting 109 bit time from 120 bit time) is idle time that is unrelated to the operation of this electronic musical instrument. But like this 1
If the scanning period is made too long, the detection of the key state (key pressed state and key released state) will be delayed, so there is a risk that optimal operation control for performance cannot be performed. For this reason 1
Although it is desirable to shorten the scanning period, if one scanning period is shortened too much, it becomes impossible to produce a musical tone with a pitch four octaves higher as described above, for example, as a coupler tone. Also, the pitch of the coupler sounds that can be produced remains the same (for example, up to a coupler sound with a pitch 4 octaves higher), and one scanning period is simply shortened (for example, one scanning period is 96 bit times). Then, an inconvenience occurs in that unnecessary musical tones are generated due to the following reasons. That is, when keys C ₅ to _{C 6} with high pitches that are scanned slowly within one scanning period are pressed, a time division multiplexed signal (“1” signal) is generated by the pressed keys C ₅ to _{C 6} . The time slots to be output are the 48th time slot to the 61st time slot, respectively, and the time slots at which these time division multiplexed signals are delayed by a maximum of 4 octaves (48 time slots) and output are the following time slots: 1st time slot to 1st time slot in the first half within one scanning period
There will be 13 time slots. In the 1st to 13th time slots within this one scanning period, the waveform signals for the keys C ₁ to _{C 2} with low pitches are output. If the output of delayed signals is not prohibited, the musical tones of keys C ₁ to _{C 2} of low pitches that are not pressed will be unnecessarily produced for pressed keys C ₅ to C ₆ of high pitches. , musically undesirable. Of course, a similar problem occurs when the order of key scanning is changed. Further, the above-mentioned disadvantages may similarly occur in the case of electronic musical instruments having a plurality of keyboards or other keyboard instruments equipped with a coupler control circuit as described above. This invention has been made in consideration of the above-mentioned circumstances, and its purpose is to provide an electronic musical instrument that can shorten one scanning period of key switch scanning while reliably achieving the desired coupler effect. It is to provide. To achieve this objective, the invention provides an inhibit circuit that disables the signal delayed by the coupler control circuit if the signal is generated in the next scanning period. This results in
Compared to the electronic musical instrument previously proposed by the applicant, one scanning period of the key switch is shortened, and the desired coupler effect can be reliably obtained. According to the present invention, some of the coupler tones for keys with high pitches (for example, 4 octaves above) are not produced, but in this case, the coupler tones that are not produced have very high frequencies ( For example, the frequency of a musical tone with a pitch of C ₁₀ is 1677Hz), there is no problem. The desired coupler sound can be reliably obtained for keys in the low and middle ranges. Embodiments of the electronic musical instrument according to the present invention will be described below with reference to the drawings. First, the overall configuration of the electronic musical instrument will be explained with reference to FIG. This electronic musical instrument can be roughly divided into two types: one that generates a timing signal such as SY95 that controls the operation of the entire electronic musical instrument, and one that generates a signal OCT1.
The timing signal generation circuit 1 that generates ~OCT8, the upper keyboard circuit 15, the lower keyboard circuit 25, and the pedal keyboard circuit 30, which will be described later, each pitch at the same time as key switch scanning to detect the pressed state of each key. a time-division waveform generation circuit 2 that time-divisionally generates a waveform signal S of a musical sound waveform or a sound source waveform with a period corresponding to , in a corresponding time slot within one scanning period;
It is comprised of an upper keyboard circuit 15, an upper keyboard musical tone generation circuit 3, a lower keyboard musical tone generation circuit 4, a pedal keyboard circuit 30, a pedal keyboard musical tone generation circuit 5, and a sound system 6. The timing signal generation circuit 1 includes an oscillator 7 that generates a clock pulse φ with a predetermined period, a 4-bit hexadecimal counter 8 driven by the clock pulse φ, and the most significant bit (fourth bit) of the hexadecimal counter 8. a 3-bit octal counter 9 driven by the MSB bit output signal _N4 ;
The bit output signals B ₁ , B ₂ ,
input B ₃ to decode these signals B ₁ to _{B 3} ,
Output signals OCT1 to OCT8 (signals OCT6 and OCT7 are not used in this embodiment)
The decoder 10 is further inputted with the bit output signals N ₁ -N ₄ of the hexadecimal counter 8, the 9-bit output signals B ₁ -B ₃ of the octal counter, and the clock pulse φ, and these signals N ₁ -N ₄ , B ₁ -B are input. ₃ and φ, various timing signals SY0, SY95, SY12/12,
It is composed of a logic circuit 11 that outputs SY0-12, SY0-4, and SY0-16. The clock pulse φ generated by the timing signal generating circuit 1 is used for driving various shift registers, delay circuits, etc. included in each of the circuits 3, 4, and 5 described above. In addition, bit output signals N ₁ to _{N 4} , B ₁ to
_B3 is used as an address signal for the frequency number memory 12 in the time division waveform generation circuit 2. Furthermore, the signals OCT1 to OCT5 and OCT8 are used in the respective keyboard circuits 15, 25 and 30 for key switch scanning. Signals OCT1 to OCT output from the decoder 10 within one scanning period, which will be described later.
5. As shown in Figure 3, OCT8 has the contents of the 96-decimal counter, which will be described later, from 0 to 11 and 12, respectively.
-23, 24-35, 36-47, 48-59, 84-95 are output as "1" signals. Also, the timing signal SY12/1 output from the logic circuit 11
2, the contents of the 96-decimal counter are 11, 23, 35, respectively.
Output when 47, 59, 71, 83 and 95. Furthermore, various timing signals SYO, SYO95, SY12/12, SY0~1 are circuited from the logic circuit 11.
2. The output states of SY0-4 and SY0-16 are as shown in the operating waveform diagram of FIG. These timing signals SY0, SY95, SY12/12,
SY0-2, SY0-4, and SY0-16 are sent to the circuits 3, 4, and 5. Here, one scanning period of the "key switch scanning" will be explained with reference to the operational waveform diagrams of FIGS. 2 and 3. In the case of the electronic musical instrument of this embodiment, an upper keyboard circuit 15 and a lower keyboard circuit 25 each having 61 key switches (both the upper and lower keyboards have 61 keys), and a pedal keyboard having 25 key switches. The key switch scanning of the circuit 30 (the pedal keyboard consists of 25 keys) is performed simultaneously and in parallel for each keyboard circuit. The "scanning period" required to scan all the key switches in each keyboard circuit 15, 25, 30 is defined by the contents of the 96-decimal counter constituted by the decimal counter 8 and the octal counter 9. . That is, the bit output signals _N1 to _N4 of the hexadecimal counter 8 and the bit output signals _B1 to _B3 of the octal counter 9 are output as shown in FIG. Also, each of these bit output signals N ₁
The relationship between the output states of ~N ₄ , B ₁ ~ _{B 3} and the contents of the 96-decimal counter is as shown in FIG. In this way, the content of the 96-decimal counter is 0 (displayed in decimal)
The period during which the value changes from 95 to 95 (in decimal notation) is one scanning period of the key switch scan defined by this embodiment. The contents of the 96-decimal counter are 0-11, 12-23, 24-35, 36-47, 48-59, respectively.
60 to 71, signals representing the above scanning results are transmitted from serial/parallel converters 16, 26, and 31 (described later) to time division multiplexed signals UXO, LKO, and PKO.
The signal is output in a time-division manner in synchronization with the clock pulse φ. By the way, the upper keyboard circuit 15 and the lower keyboard circuit 25
Both have 61 key switches, and the pedal keyboard circuit 30 has 25 key switches, so the period during which each key switch of the upper keyboard circuit 15 and the lower keyboard circuit 25 is actually scanned ( In other words, the period during which the time division multiplexed signals UKO and LKO are output from the parallel/serial converters 16 and 26)
In this case, the content of the 96-decimal counter is between 0 and 60, and the actual key switch scan is not executed during the remaining period of one scanning period, that is, the period when the content of the 96-decimal counter is 61 to 95. Furthermore, in the case of the pedal keyboard circuit 30, since this keyboard circuit 30 has 25 key switches, the period during which key scanning is actually executed (that is, the period during which the time division multiplexed signal PKO is output) is as follows. The content of the 96-decimal counter is a period from 0 to 24, and the key switch scan is not executed during the remaining period from 25 to 95. In this way, the upper keyboard circuit 15 and the lower keyboard circuit 2
5. The key switch scan of the pedal keyboard circuit 30 is executed, but as mentioned above, during one scan period of the key switch scan, the key switch scan is not actually performed (when the content of the 96-decimal counter is between 61 and 95). period)
The reason why is provided is as follows. That is, the musical tone generating circuits 3, 4, and 5 connected to each keyboard circuit 15, 25, and 30, respectively, simultaneously generate musical tones of keys having a predetermined pitch relationship with the pressed key for one pressed key. Although coupler control circuits are provided for this purpose, the above-mentioned period must be provided in order for these coupler control circuits to operate reliably. The reason for this will be discussed in detail later. Next, the relationship between the decoder 10, the upper keyboard circuit 15, the lower keyboard circuit 25, and the pedal keyboard circuit 30 will be specifically explained. FIG. 4 shows the key switch circuits 43 and 44 of the upper keyboard circuit 15 or the lower keyboard circuit 25,
FIG. 5 also shows a key switch circuit 45 of the pedal keyboard circuit 30. As we all know, there are 12 octaves in one octave.
consists of the pitch names C, C#, D, ......B, but in the following explanation, the 12 keys of the first octave or their key switches will be indicated by symbols C ₁ to B ₁ , and the notes of the second octave to The keys of the 8th octave or their key switches are designated by the symbols C ₂ - _{B 2} , C ₃ - _{B 3} , . . .
..., shall be displayed in C ₈ to B ₈ . In FIG. 4, 61 of the upper keyboard circuit 15 and the lower keyboard circuit 25
The 61 key switches C ₁ to _{C 6} corresponding to the keys are:
As shown in the figure, key switch circuits 43 and 44 are arranged in a matrix for each octave and each pitch name. That is, the key switch circuit 4
3 and 44 column lines l ₁ to l ₆ are the 1st to 6th column lines, respectively.
The row lines L ₁ to L ₁₂ correspond to the pitch names C, C#, . . . , B, respectively. For example, on the intersection of the column line _l1 and the row line _L5 , a key switch _E1 for a key of the first octave and a note name E is disposed. Note that the circles marked on the intersections of column lines l ₁ to _{l 6} and row lines L ₁ to _{L 12} in the figure indicate the column lines and row lines to which each key switch (C ₁ to C ₆ ) corresponds. It is shown that they are connected in the forward direction via a diode. The signal OCT8 output from the decoder 10 mentioned above
and signals OCT1-OCT5 are input to column lines _l1 - _l6 , respectively. Also, key switch circuit 4
Parallel/serial converters 16, 26 are connected to the output sides (row lines _L1 to _L12 side) of the lines 3, 44. The signals OCT1 to OCT8 are signals that are sequentially output as "1" signals from the signal OCT1 while the contents of the octal counter 9 change from 0 to 7 (decimal number) (FIG. 3). . Therefore, the key switches C ₁ to B ₁ of the first octave are scanned by the signal OCT8 which is output during the period when the content of the octal counter 9 is 7 (that is, the content of the 96-decimal counter is 84 to 95). In addition, the second octave key switches C ₂ to B ₂ output signals while the content of the octal counter 9 is 0 (the content of the 96-decimal counter is 0 to 11).
Scanned by OCT1. Similarly, the key switches C ₃ to B ₃ for the third to sixth octaves,
For C ₄ to _{B 4} , C ₅ to B ₅ , and C ₆ , the contents of the octal counter 9 are 1, 2, 3, and 4, respectively (the contents of the 96-decimal counter are 12 to 23, 24 to 35, and 36 to 47, respectively) , 48 to 59) signals OCT3, OCT4, OCT5 output during each period
scanned by Each scan result is then sent to the parallel/serial converter 16 (26) as 12-bit parallel data. The structure of the key switch circuit 45 of the pedal keyboard circuit 30 shown in FIG. 4 is as follows: Each key switch circuit 43 (44) shown in FIG.
Since they are exactly the same except for the number of key switches, their explanation will be omitted. Note that the parallel/serial converter 31 is connected to the output side of the circuit 45. Decoder 10 and each keyboard circuit 15, 25, 3
Since the 0 key switch circuits 43-45 are configured as described above, the "1" signals OCT8, OCT1-
The OCT 5 is sequentially output from the decoder 10, and the corresponding column lines l ₁ to 1 of each keyboard circuit 15, 25, 30
l When each keyboard circuit 15, 25, 30 is simultaneously input to ₆ , the 12 key switches of the corresponding octave are simultaneously scanned, and as a result, 12-bit data representing the key depression state in that octave is transmitted to each key switch circuit. Output from 43 to 45, as described later.
The contents of the 96-decimal counter are 95, 11, 23, 35, respectively.
47 and 59, the signals are taken into the corresponding parallel/serial converters 16, 26, and 31. Next, the detailed configuration of the parallel/serial converter 16 will be explained. The configuration of this converter 16 is as follows:
Other parallel/serial converters 26, 3 mentioned above
It has the same configuration as 1. Therefore other parallels/
A detailed description of the configuration of the serial converters 26 and 31 will be omitted. Key switch circuit 43 in the upper keyboard circuit 15
AND gate 5 to which each row line L ₁ to L ₁₂ corresponds
It is connected to each of the first input terminals of 0 to 61, and is also connected to a power supply terminal (not shown) that supplies a binary logic level "0" signal via each of the corresponding resistors _R1 to _R12 . . In addition, the AND gates 50 to 6
The timing signal SY1 is connected to each second input terminal of SY1.
2/12 are both input, and this signal SY12/
AND gate 5 when outputting 12 (at “1” signal)
0 to 61 can be operated simultaneously. Each output terminal of the AND gates 50-60 is connected via a corresponding OR gate 62-72 to each input terminal of a delay flip-flop (hereinafter abbreviated as DFF) 73-83 driven by a clock pulse φ. Further, the output terminal of the AND gate 61 is directly connected to the input terminal of the DFF 84. Furthermore
The output terminal of DFF84 is connected via OR gate 72.
It is connected to the input end of DFF83, and the output end of DFF83 is connected to the input end of DFF82 via OR gate 71. Below, in the same way, the above
The output terminals of each DFF 82 to 74 are connected to the subsequent DFF 82 through each OR gate 70 to 62 so that the DFFs 82 to 73 are connected in series with each other as shown in the figure.
~73 is connected to the input terminal. and said
The output signal of DFF73 is the time division multiplexed signal UKO.
is extracted as. In this way the DFF84
73 are connected in series to form a 12-stage shift register. The time division multiplexed signal UKO indicates the key depression state of the upper keyboard circuit 15 and is sent to the first and second upper keyboard tone generation control circuits 17 and 19. The operation of the parallel/serial converter 16 configured as described above will be described next. As mentioned above, the signals OCT1 to OCT8 from the decoder 10 are
After the start of the scanning period, the signals are sequentially output as "1" signals and input to the corresponding column lines _l1 to _l6 of the key switch circuit 43 of the upper keyboard circuit 15. In addition, as shown in the operating waveform diagram in Figure 3, the timing signal
SY12/12 is output when the contents of the 96-decimal counter are respectively 11, 23, 35, 47, 59, 71, 83, and 95. Therefore, when the content of the 96-decimal counter is 95 just before the start of one scanning period, the timing signal SY12/12 ("1" signal) is outputted and sent to the AND gates 50 to 61, and these AND gates 50 to 61 becomes operational. At this time, since the signal OCT8 (“1” signal) has already been input to the column line _l1 of the key switch circuit 43 (FIG. The pressed state of the 12 keys C ₁ to B ₁ (i.e. the open/closed state of the key switches C ₁ to B ₁ )
Signals representing the row lines L ₁ to _{L 12} are output in parallel and input to the corresponding AND gates 50 to 61, and further simultaneously input to the DFFs 73 to 84 via the AND gates 50 to 61 and the OR gates 62 to 72. Ru. Next, when the content of the 96-decimal counter becomes 0, a signal indicating the pressed state of key C ₁ stored in the DFF 73 (i.e., if key C ₁ is pressed, it is a "1 _" signal; If the button is not pressed, a signal that is output as a "0" signal) is output as the time division multiplexed signal UKO. At the same time, the output signal of DFF74 is input to DFF73 via OR gate 62, and
75 output signal passes through OR gate 63 to DFF
DFF84-7 is input in the same way.
6 output signals are input to DFFs 83-75 via OR gates 72-64, respectively. In this way, when the content of the 96-decimal counter is 0, the time-division multiplex signal UKO indicating the pressed state of key _C1 is transmitted to DFF73.
At the same time, the contents of DFFs 84 to 74 are shifted to the next stage DFFs 83 to 73. Similarly, when the contents of the 96-decimal counter sequentially change from 1 to 11, a signal representing the pressed state of keys C# ₁ to B ₁ is output from the DFF 73 as a signal synchronized with the clock pulse φ, and the time division multiplex signal UKO is output. As the DFFs 82 to 74 are created, the contents of the DFFs 82 to 74 are shifted to the next DFF each time. When the content of the 96-decimal counter reaches 11, the first octave key C ₁
~ _B1 All signals indicating the key press state are extracted as a time division multiplexed signal UKO, and as a result, DFF73
All contents of ~84 are cleared. At the same time, a timing signal SY12/12 is output to enable the AND gates 50 to 61 to operate simultaneously, and each AND gate 50 to 61 is connected to the key C of the second octave via the row lines _L1 to _L12 . ₂ ～ _B2
A signal representing the key depression state is input at the same time. Therefore, DFF73 to DFF84 store signals representing the key depression states of the keys _C2 to _B2 of the second octave. Therefore, during the next period when the contents of the 96-decimal counter change from 12 to 23, the DFF 73 outputs a signal representing the pressed state of keys C ₂ to B ₂ of the second octave as a time division multiplexed signal UKO. As described above, the operation of transferring the contents of DFF84 to DFF73 to the next stage DFF is performed. In this way, during the period until the contents of the 96-decimal counter change from 0 to 60, the 61 keys of the upper keyboard circuit 15 are
Time-division multiplexed signal UKO representing key press status of C ₁ to C ₆
will be output. The contents of the 96-decimal counter are
During the remaining period of one scanning period from 61 to 95, the signal
UKO is “0”. Further, the time division multiplexed signal UKO is sent to the first and second upper keyboard tone generation control circuits 17 and 19 for processing. Table 1 shows the parallel/serial converter 1
6 shows the correspondence between the pitch to which the time division multiplexed signal UKO outputted from 6 and the content of the 96-decimal counter is shown.

[Table] In the above explanation, only the operation of the parallel/serial converter 16 of the upper keyboard circuit 15 was explained, but the output signals OCT8 and OCT of the decoder 10
1 to OCT5 are the column lines l ₁ to l ₆ of the key switch circuits 43, 44, and 45 of each keyboard circuit 15, 25, and 30.
For example, upper keyboard circuit 1
When the keys C ₁ to _{B 1} of the first octave of No. 5 are being scanned, the lower keyboard circuit 25 and the pedal keyboard circuit 3 are scanned.
The scanning of keys C ₁ to B ₁ of the first octave of 0 is performed simultaneously in parallel, resulting in a time division multiplexed signal from each parallel/serial converter 26, 31.
LKO and PKO are output in parallel with the time division multiplexed signal UKO. Next, the time division waveform generation circuit 2 will be explained. As shown in FIG. 1, the time-division waveform generation circuit 2 generates a frequency number (proportional to the frequency of the musical tone to be generated) corresponding to each content (0 to 95) of the 96-decimal counter of the timing signal generation circuit 1. bit output signals N ₁ to _{N 4} , B ₁ which store the numerical value) R and are generated from the timing signal generation circuit 1;
A frequency number memory 12 that inputs ~ _B3 as an address signal and outputs the corresponding frequency number R.
, an accumulator 13 that independently accumulates each frequency number R sequentially and time-divisionally outputted from the frequency number memory 12, and a desired musical tone 1 waveform (in the following explanation, it is assumed to be a sine waveform, but of course other types of waveforms can be used). (may be a waveform of
(q=1, 2, 3...) is input as an address signal and a sine table 14 outputs a sine amplitude value S corresponding to the accumulated value qF. More specifically, the accumulator 13
is connected to an adder that inputs the frequency number R to a first addition input terminal, and an output terminal of this adder,
It also includes a shift register consisting of 96 stages driven by a clock pulse φ. Furthermore, the output of this shift register is input to the second addition input terminal of the adder, so that this adder adds the data at both addition input terminals and outputs the added value to the shift register, and also The added value input to the shift register is sequentially shifted to the subsequent stage side. In this way, the accumulator 13 independently and sequentially adds up the frequency numbers R corresponding to each pitch, and the cumulative value qF
are sequentially output to the sign table 14. The frequency number memory 12 also stores frequency number numbers R corresponding to keys C# ₆ to B ₈ (35 keys in total) that are not actually provided in each keyboard circuit 15, 25, 30. This is because, as mentioned above, each tone generation circuit 3, 4, 5 is provided with a coupler control circuit, and the frequency number corresponding to the time division multiplexed signal delayed and outputted by this coupler control circuit is This is because it is necessary to give R and generate the corresponding sine amplitude value S from the sine table 14. Further, since the bit output signals N ₁ to N ₄ and B ₁ to B ₃ are inputted to the frequency number memory 12 as address signals, it is obvious that the contents of the frequency number R read from the memory 12 are as follows. The time-division multiplexed signals UKO, LKO, PKO and these circuits UKO, LKO, PKO are associated with each of the signals delayed by the corresponding coupler control circuit in terms of pitch. It is something that we have. Furthermore, the sine amplitude value S output from the sine table 14 is
In this embodiment, the data is represented by 13-bit sign-logarithm display data (minus log display). This minus log display means that when the amplitude value (sine amplitude value S) of a waveform signal is displayed as an absolute value,
The maximum amplitude value is defined as 0 dB, and amplitude values below that are expressed by the amount of attenuation relative to the maximum amplitude value (0 dB). For example, -0.75 dB, -1.5 dB, - with respect to the maximum amplitude value (0 dB). 3dB, −6dB, −12dB, −
Each amplitude value of 24 dB, . The remaining 1 bit is used as a sign bit representing the positive or negative polarity of the 12-bit data. In other words, -0.75dB is expressed as the least significant bit (LSB), and -1.5dB is expressed as the second
-3 dB is represented by the 9th bit, and so on, and the amplitude value is represented by the sum of the values of the bits whose binary logic level is "1". Therefore, when all the bits (12 bits) are "1", the amplitude value (absolute value display) being output is the minimum, and on the other hand, when all the bits are "0", the amplitude value is the maximum. The sign bit (1 bit) is displayed as "0" when the amplitude value being output is on the plus side with respect to the reference value, and as "1" when it is on the minus side. In this way, from the time division waveform generation circuit 2,
The sine amplitude value S at a certain sample point corresponding to each pitch C ₁ to B ₈ and expressed logarithmically is sequentially output in a time-division manner according to the contents of the 96-decimal counter. Furthermore, this sine amplitude value S is the same as the signal outputted at the same time.
UKO, LKC, and PKO are associated with each other in terms of pitch, so at a certain point within one scanning period, for example,
The sine amplitude value S and the signals UKO, LKO, and PKO that are output when the content of the 96-decimal counter is 0 have the content for the key _C1 of the same pitch.
The sine amplitude value S is determined by each musical tone generating circuit 3,
4 and 5 are supplied to adders 37 ₁ to 37 ₄ , respectively. Next, the schematic configurations of the upper keyboard musical tone generating circuit 3, the lower keyboard musical tone generating circuit 4, and the pedal keyboard musical tone generating circuit 5 will be explained. First, upper keyboard musical tone generation circuit 3
is each key switch in the key switch circuit 43
A time-division multiplex signal UKO indicating the pressed states of keys C ₁ to _{C 6} is input, and this signal UKO is delayed by a predetermined time, and each of the delayed signals is weighted according to each setting state of the nine drawbars 18. a first upper keyboard tone generation control circuit 17 that outputs a weighted signal UKO1, and a weighted signal UXO1;
and an adder ₃₇₁ which receives and adds the sine amplitude values S sequentially output from the time-division waveform generation circuit 2, and a logarithm which converts the output data (logarithm display data) of the adder ₃₇₁ into linear data. Data/linear data converter (hereinafter abbreviated as log-Lin converter) 38 ₁ and this log-Lin converter 38
An accumulator ₃₉₁ that adds the output data of ₁ during one scanning period and outputs the total added value at the end of one scanning period, and latches the total added value output from this accumulator ₃₉₁ at the end of one scanning period. Latch circuit 40 ₁ and latch circuit 40 ₁
Digital-analog converter (hereinafter abbreviated as DA converter) 41 ₁ , DA converter 41 that converts the output data (digital data) of
Variable resistor to adjust the size of output data of ₁
When VR ₁ and the signal UKO are input, 5
The signal UKO is subjected to predetermined processing according to the respective settings of the drawbars 20, the legato percussion switch 21, and the percussion length changeover switch 22, and a signal UKO2 with various envelope waveforms is output. Second upper keyboard tone generation control circuit 19, adder ₃₇₂ , log-Lin converter ₃₈₂ , accumulator ₃₉₂ , latch circuit ₄₀₂ , DA converter ₄₁₂ , and variable resistor
It consists of VR ₂ . In the figure, both the first upper keyboard musical tone forming circuit 23 and the second upper keyboard musical tone forming circuit 24, which are surrounded by a dashed line, have the same configuration. The lower keyboard musical tone generation circuit 4 receives the time division multiplexed signal LKO indicating the pressed state outputted from the key switch circuit 44, delays this signal LKO by a predetermined time, and divides each of the delayed signals into nine signals. a lower keyboard musical tone generation control circuit 27 (this circuit 27 has the same configuration as the circuit 1) that outputs a weighted signal LKO1 weighted according to each setting state of the drawbar 28; an adder ₃₇₃ ;
log-Lin converter 38 ₃ and accumulator 39 ₂
, a latch circuit ₄₀₃ , a DA converter ₄₁₃ ,
Consists of variable resistor VR ₃ . Note that the lower keyboard musical tone forming circuit 29 surrounded by a dashed line in the figure has the same structure as the first and second upper keyboard musical tone forming circuits 23 and 24. The pedal keyboard musical tone generating circuit 5 receives the time division multiplexed signal PKO outputted from the key switch circuit 45 and indicating the pressed state of the key, and uses this signal PKO to determine which of the keys of the pedal keyboard circuit 30 was previously pressed. one pulse signal corresponding to a single pressed key among the signal PKO on the condition that there is no other pressed key; When multiple keys are pressed at the same time, only the pulse signal corresponding to the bass key is given priority) and delayed by a predetermined time, and each of the delayed signals is sent to the seven drawbars 3.
3. Perform predetermined processing on the signal PKO (i.e., one pulse signal corresponding to the pressed key) according to the settings of the pedal percussion switch 34 and the pedal suspension switch 35 to generate various envelope waveforms. A pedal keyboard musical tone generation circuit 32 that outputs the applied signal PKO1, and an adder ₃₇₄
, log-Lin converter 38 ₄ , and accumulator 3
9 ₄ , latch circuit 40 ₄ , and DA converter 41 ₄
and a variable resistor VR ₄ . In addition, the pedal keyboard musical tone forming circuit 36 is surrounded by a dashed line in the figure.
has the same structure as the musical tone forming circuits 23, 24, and 29 of each keyboard. The musical tone signals individually generated by the musical tone generating circuits 3, 4, and 5 for each of the above-mentioned keyboard circuits 15, 25, and 30 are sent to a sound system 6 consisting of an amplifier and a speaker, mixed, and simultaneously emitted. Next, the configuration of each part of the above-mentioned upper keyboard tone generating circuit 3 will be explained in more detail. First, the detailed structure of the first upper keyboard tone generation control circuit 17 and the drawbars 18 will be explained with reference to FIGS. 7 to 10. The first one shown in Figure 7
The upper keyboard musical tone generation control circuit 17 receives the time division multiplexed signal UKO and sequentially delays it through eight series-connected delay circuits (shift registers) 87 to 94 to form signals DUKO1 to DUKO8. and the signal that delayed this signal UKO
Weighting circuit 100-1 for DUKO1-DUKO8
08 and drawbar 1, which will be described later.
The weighting signals K1 _to K9 are output as 3-bit weighted signals K1 to _K9 , which are respectively weighted according to the setting states of ₈₁ to ₁₈₈ , and these weighted signals _K1 to _K9 are sent to the adder 1
It consists of a coupler control circuit which outputs addition in addition to 09. In this embodiment, the adder (6-bit data) of the adder 109 is converted into a logarithmically expressed signal UKO1 by a linear data/logarithmic data converter (hereinafter abbreviated as Lin-log converter 110). and is sent to the adder ₃₇₁ . The time division multiplex signal UKO has a capacity of 12 stages,
It consists of one bit and is input to a shift register 87 driven by a clock pulse φ. The output side of the shift register 87 has capacitances of 7 stages/1 bit, 5 stages/5 stages/1 bit, 7 stages/1 bit, 5 stages/1 bit, 4 stages/1 bit, 3 stages/1 bit, 5-stage, 1-bit shift register 8
8 to 94 are connected in series. These shift registers 88 to 94 are also driven by the clock pulse φ, and are configured to sequentially shift the time division multiplexed signal UKO inputted to the first shift register 87 to the subsequent shift register. Therefore, a certain bit time (in the following description of this embodiment, one scanning period is divided into 96 bit times depending on the contents of the 96-decimal counter)
The time-division multiplexed signal UKO input to the first stage of the shift register 87 at each divided time domain is called a bit time or time slot, corresponds to a period of 12 bit times (that is, a period during which 12 clock pulses φ are output). ) is later outputted from the 12th stage of this shift register 87 (this output signal is named DUKO1), inputted to the first stage of the next stage shift register 88, and further inputted to this shift register 88. The signal DUKO1 is output from the seventh stage after 7 bit times (this signal is named DUKO2) and input to the first stage of the shift register 89 in the next stage. In this way, the time-division multiplexed signal UKO is input to the first upper keyboard musical tone generation control circuit 17, and then is inputted into the shift registers 87 to 94 for each predetermined time, that is, 12 bit time, 7 bit time, 5 bit time, 7 bit time, and 7 bit time.
The signals from each shift register 87 to 94 are delayed by bit time, 5 bit time, 4 bit time, 3 bit time, and 5 bit time.
Output as DUKO1~DUKOS. Here, the input terminal of the shift register 87 is set to A point, and each output terminal of shift registers 87 to 94 is set to B, C, D, E, F,
Name them G, H, and I points. This A, B, C,
Points D and E are respectively 16 feet (hereinafter, feet are expressed as dashi and abbreviated as 16') 8', 51'/
3, 4', 22'/3 foot weighting circuits 10
0, 101, 102, 103, and 104. In addition, the F, G, H, and I points are connected through AND gates 96, 97, 98, and 99, respectively.
2', 13'/5, 11'/3, and 1' are connected to respective foot weighting circuits 105, 106, 107, and 108. Signals 0 to 12 obtained by inverting the timing signals SY0 to SY12 by an inverter 95 are input to the AND gates 96 to 99 as control signals for reasons described later. Each of the weighting circuits 100 to 108 has the same configuration, and the signals UKO, DUKO1 to DUKO
3 AND gates 10 each input with 8
0 ₁ ~ 100 ₃ , 101 ₁ ~ 101 ₃ , 102 ₁
~102 ₃ ,103 ₁ ~103 ₃ ,104 ₁ ~1
04 ₃ , 105 ₁ ~ 105 ₃ , 106 ₁ ~ 106
_{3,1071 to 1073,1081 to 1083} . In the case of the 16 weighting circuit 100, the AND gates 100 ₁ , 100 ₂ , 100 ₃ each receive each bit D ₁ (the least significant bit) of the 3-bit data output from the drawbar 18 ₁ (FIGS. 1 and 8). ; LSB), D ₂ , D ₃ (largest bit;
MSB) is input. and each and gate 1
The 3-bit weighting signal _K1 output from ₀₀₁ to ₁₀₀₃ is applied to the 16' weighting circuit 100.
16', this signal K ₁ is sent to adder 109 . AND gates 101 ₁ to 1 in weighting circuits 101 to 108 of other feet
01 ₃ , 102 ₁ ~ 102 ₃ , 103 ₁ ~ 103
_{3,104 1} ~104 _{3,105 1} ~105 ₃ ,
106 ₁ ~ 106 ₃ , 107 ₁ ~ 107 ₃ , 10
Similarly, each bit D ₁ , D ₂ , D ₃ of the 3-bit data output from the corresponding drawbars 18 ₂ to 18 ₃ is inputted to the draw bars 8 ₁ to 108 ₃ respectively. and each foot weighting circuit 101 to 10
8 output weighting signals K ₂ to K ₃ (3-bit data), respectively, and send them to an adder 109. The adder 109 adds the weighting signals K ₁ to K ₉ at each bit time and outputs the added value as 6-bit data K, and the Lin-log converter 11
Send to 0. Therefore, this converter 110 converts logarithmic display output data (10-bit signal) according to the size of input data at each bit time.
It is designed to output 1. Here, the specific structure of the draw bars 18 ₁ to 18 ₉ will be explained with reference to FIGS. 8 and 9.
The drawbars 18 ₁ to 18 ₉ have the same configuration, so only the configuration of the drawbar 18 ₁ will be described. The drawbar ₁₈₁ consists of three interlocking changeover switches 115, 116, 117, and each changeover switch 115, 116, 117 is
Fixed contacts 115a, 116a, 117a each having eight switching positions (numbers 0 to 7 indicate the weight of each switching position) and a movable contact 115b provided corresponding to the fixed contacts 115a, 116a, 117a. , 116b, 117
It has b. Fixed installation point 115a of switch 115
Among them, the switching positions marked with numbers 0, 2, 4, and 6 are connected in common to a power supply terminal (not shown) that supplies a "0" signal. Of the fixed contacts 116a of the switch 116, the switching positions marked with numbers 0, 1, 4, and 5 are connected in common to the power supply terminal that supplies the "0" signal. Furthermore, among the fixed contacts 117a of the switch 117, numbers 0, 1,
The switching positions marked 2 and 3 are commonly connected to a power supply terminal that supplies a "0" signal. On the other hand, each movable contact 115 of the switches 115 to 117
b to 117b are the corresponding resistances R ₁₅ , R ₁₆ ,
It is connected to a power supply terminal (not shown) that supplies a "1" signal via _R17 , and each movable contact 115
The signals ("0" signal or "1" signal) from b to 117b are configured to be output as data D ₁ , D ₂ , D ₃ of each bit of the 3-bit data. Also, the movable contact 115 of the drawbar ₁₈₁
b to 117b are driven by operators (not shown), and these operators are arranged near the keyboard (not shown) of the upper keyboard circuit 15. Since _the drawbars 18 ₁ to 18 ₉ are configured as described above, when the movable contacts 115b to 117b are set to arbitrary positions, for example, the position shown in _FIG. Data output from D ₃ , D ₂ , D ₁
are respectively "0", "1", and "1", that is, data 3 (decimal number) is taken out from the drawbar ₁₈₁ . In this way, the movable contacts 115b to 117b of the drawbar ₁₈₁ are set to the switching positions indicated by the numbers 0, 1, 2, 3, 4, 5, 6, and 7, respectively, as shown in the drawing. , the data D ₁ to _{D 3} output from the drawbar 18 ₁ are 0, 1, 2, 3, 4, respectively.
5, 6, 7 (both are decimal numbers). Data D ₃ to _{D 1} (binary number 011) retrieved by setting the drawbar 18 ₁ to the position shown in FIG. 9 described above
are input to AND gates 100 ₁ , 100 ₂ , 100 ₃ in 16′ weighting circuit 100 (FIG. 7). As a result, the AND gate 100 _1,100
A "1" signal is input to the AND gate 1003, making it in an operable state, and a "0" signal is input to the AND gate ₁₀₀₃ , making it in an inoperable state. In this state, when the time-division multiplexed signal UKO (a signal representing a key press pulse) of the "1" signal is output from the parallel/serial converter 16, the 16' weighted signal 10
Weighted signal representing content 3 (decimal number) from 0
K ₁ (011) is output, and this signal K ₁ is sent to the adder 10
Sent to 9th. If the other drawbars 18 ₂ to 18 ₉ are similarly set at desired positions,
When the signals DUKO1 to DUKO8 become "1" signals, the weighting circuits 101 to 108 output weighting signals _K2 to _K9 corresponding to the set positions of the respective drawbars ₁₈₂ to ₁₈₉ , and these signals
K ₂ to K ₉ are sent to adder 109. In this way, the player can freely select the weighting of each foot by appropriately selecting the set position of each of the drawbars 18 ₁ to 18 ₉ by operating the operator. As explained above, since the first upper keyboard musical tone generation control circuit 17 and the drawbars 18 are configured,
When one key is pressed in the upper keyboard circuit 15, the key switch of this key is scanned, and the time division multiplex signal UKO (“1” signal) is output from the parallel/serial converter 26, this time division multiplex signal is output. Signal UKO
is input to the first upper keyboard musical tone generation control circuit 17 which constitutes the coupler control circuit. The signal DUKO is then sequentially delayed by each shift register 87 to 94.
1 to DUKO8, and input to each weighting circuit 100 to 108. As a result, nine types of weighting signals K ₁ to _{K 9} are output from each weighting circuit 100 to 108 at the corresponding time slot within one scanning period to the time division multiplexed signal UKO of one key, and are outputted to the adder 109. is input to the adder 37 via the Lin-log converter 110.
It will be sent to ₁ . Note that the signals DUKO5 to DUKO8 are input to each weighting circuit 105 to 108 via AND gates 96 to 99 to which signals 0 to 12, which are obtained by inverting the timing signals SY0 to SY12 by an inverter 95, are input as control signals. Reason,
This is to prevent musical tones of the keys C ₁ -C ₂ of low pitch from being generated when keys C ₅ -C ₆ (13 keys) of high pitch are pressed. That is, as described above, in this embodiment, one scanning period is a period of 96 bit times defined by the contents of the 96-decimal counter. The total capacity of the shift registers 87 to 94 is 48 stages, and the time division multiplexed signal UKO (“1” signal) representing the pressed key input to the first stage of the shift register 87 is transmitted to the shift register 87.
The time required for output from the fifth stage of 4 is 48 bit time. Therefore, for example, when key C ₅ is pressed, the time division multiplexed signal UKO for this pressed key C ₅ is generated when the content of the 96-decimal counter is 48, and therefore this signal UKO ( “1” signal) is the shift register 94
When output from the fifth stage, the content of the 96-decimal counter is 0 for the next one scanning period. When the content of the 96-decimal counter is 0, the sine amplitude value S simultaneously output from the time-division waveform generation circuit 2 corresponds to the key _C1 , so that the signal output from the 1' weighting circuit 108 at this time If K ₉ is not prohibited, keys with high pitches will be pressed as described above.
This is because an inconvenience occurs in that a musical tone with a lower pitch _C1 is emitted compared to _C5 . The same thing can be said about the other keys C# ₅ to _C6 . Therefore, the signals generated by pressing these keys C# ₅ to C ₆
For DUKO5 to DUKO8, the content of the 96-decimal counter is 0.
In order to prevent the signal from being input to each weighting circuit 105-108 during the period .about.12, a prohibition circuit formed by AND gates 96-99 whose operation is controlled by signals SY0-12 is provided. Next, the structure of the first upper keyboard musical tone forming circuit 23 in the upper keyboard musical tone generating circuit 3 will be explained in detail with reference to FIG. The sine amplitude value S(13
Of the bit sign/logarithm display data), the data of the sign bit SB (1 bit) is converted to the sign/absolute value display data/2' complement display data converter (hereinafter referred to as S&M-2'C) in the accumulator ₃₉₁ .
(also referred to as a converter or first converter) 136 is input to a control input terminal C. Also, of the remaining 12 bits of data of the sine amplitude value S, the lower 2 bits are
In other words, the data of the first bit (LSB) and the second bit are sent to the OR gate 123 or the OR gate 1.
24 to the log-Lin converter ₃₈₁ ,
Further, each data of the 3rd bit to the 12th bit (MSB) is input to the first input terminals A ₁ to A ₁₀ of the adder ₃₇₁ . The second input terminal B ₁ to B ₁₀ of this adder ₃₇₁
In the first upper keyboard musical tone generation control circuit 17,
Signal UKO output from Lin-log converter 110
1 (10-bit logarithmic display data) is input.
Adder 37 ₁ is the first input line A ₁ to _{A 10} and the second input terminal
The data input to _B1 to _B10 are added, and the lower 6 bits of the adder (10 bits) are sent to the log-Lin converter ₃₈₁ via the OR gates 125 to 130, and the upper 4 It is configured to send bit data to input terminals a, b, c, and d of the shifter 135 in the accumulator ₃₉₁ , respectively. Note that when a carry signal is generated from the adder ₃₇₁ , this carry signal (“1” signal) is sent to log-Idn via the OR gates 123 to 130.
input to converter 38 ₁ and OR gate 1
31 to 134 to the respective input terminals a, b, c, and d of the shifter 135, and as a result, the inputs of the OR gates 123 to 134 all become "1" signals, and the generated musical tone immediately disappears. ing. The log-Lin converter 38 converts the input 8-bit logarithmic display data into 10-bit linear display data (absolute value display data) and sends it to the shifter 135. When the output of the OR gate 131 is a "1" signal, the data input to the shifter 135 is shifted to the higher order side by 1 bit and the size is increased.
The data reduced to 1/2 is output from the shifter 135 and sent to the first converter 136. Similarly,
When the outputs of the OR gates 132, 133, and 134 are "1" signals, the data input to the shifter 135 is 2 bits, 3 bits, and 4 bits, respectively.
Bits are shifted to the upper side and the size is 1/4, 1/8,
The data reduced to 1/16 is output from the shifter 135 and sent to the first converter 136. This first
The converter 136 converts the 10-bit data sent from the shifter 135 in sign/absolute value display (this display method will be described later) to 2' complement display (2's complement display, this display method will also be described later). ) to 14-bit data. For this reason, the control input terminal C of the first converter 136
When the sign bit SB input to the input data is a “1” signal, all the bits of the input data are inverted and then “1” is added to the least significant bit (LSB) and outputted. On the other hand, when the sign bit SB is “0” When it is a signal, the input data is output as is, and this converted data is sent to the first input terminal A of the adder 139. The added value (14-bit data) of the adder 139 is input to the second input terminal B of the adder 139 via the gate circuit 138. Gate circuit 1
38, the timing signal SY95 is inputted via the inverter 137. Therefore, when the timing signal SY95 is a "1" signal (the above 96
The gate circuit 138 is activated only when the content of the advance counter is 95 (that is, the last bit time of one scanning period).
is rendered inoperable. As a result, within one scanning period, when the contents of the 96-decimal counter are between 0 and 94, the adder 139 outputs the output data of the first converter 136 and the added value of the adder 139 one bit time before (this The value is held in a one-stage shift register (not shown) provided on the output side of the adder 139), and when the content of the 96-decimal counter reaches 95, the final addition operation is performed. It is intended to carry out the following. Adder 139
The added value (2′ complement display data) is also
2' complement data/sign/absolute value display data converter 140 (This converter 140 is a converter that converts 2' complement display data into sign/absolute value display data. In the following explanation, 2'C- S&
The signal is also sent to an M converter (also called a second converter) and output as 1-bit sign bit SB and 12-bit absolute value display data. Said sign bit
SB is input to the latch circuit ₄₀₁ directly or via the inverter 141, and absolute value display data is input directly to the latch circuit ₄₀₁ . The latch circuit ₄₀₁ inputs the timing signal SY95 as a control signal. Therefore, at the end of one scanning period, the latch circuit ₄₀₁ receives the final cumulative value accumulated by the adder 139 during this one scanning period. The second converter 140 latches the data that is expressed in sign and absolute value. Furthermore, the latch circuit ₄₀₁ outputs the latched data from output terminal A, and when the input sign bit is a "0" signal, it outputs "1" and "0" signals from output terminals B and C, respectively. However, when the sign bit is a "1" signal, the output terminals B and C are configured to output a "0" signal and a "1" signal, respectively. The data output from the output terminal A is input to the DA converter ₄₁₁ , and the output signal from the output terminal B is input to the switch 143.
The output signal of the output terminal C controls the opening and closing of the switch 142. switch 14
2,143 closes when the opening/closing control signal is “1”;
It is designed to open when it is "0". The input sides of switches 142 and 143 are both DA converters 41
It is connected to the output end of _switch 14.
The output side of switch 143 is connected to the negative input terminal of operational amplifier 144, and the output side of switch 143 is connected to the positive input terminal of operational amplifier 144.
In addition, the positive input terminal of the operational amplifier 144 is connected to a resistor _R26.
is grounded through the terminal, and the negative input terminal is connected to the resistor.
It is connected to its output terminal via R ₂₇ . The output terminal of the operational amplifier 144 is further connected to the variable resistor.
Connected to sound system 6 via VR ₁ . Here, the 2' complement representation method and the sign absolute value representation method will be briefly explained. In the sign/absolute value display method, the same amplitude values on the plus and minus sides of the reference value of the waveform signal (in this example, the 12-bit data output from the second converter 140) are exactly the same value. expressed. On the positive side of the amplitude, the sign bit SB is defined as a "0" signal, and on the other hand, on the negative side of the amplitude, the sign bit SB is defined as a "0" signal.
is defined as a “1” signal. On the other hand, in the 2′ complement notation, the positive value of the amplitude is expressed exactly the same as the positive side of the sign/magnitude notation, while the negative value of the amplitude is expressed as the complement of the positive value. The value on the negative side is expressed by the sign and
This value is different from the value on the negative side of the absolute value display method. Therefore, in the first converter 136, the sign bit SB input to the control input terminal C is "1".
In this case, it has the function of inverting all bits of data D _- on the negative side of the amplitude and adding +1 to its LSB. In addition, when the input data (14 bits) is data D ₊ having a value on the positive side, the second converter 140 outputs the sign bit SB as a "0" signal and passes the data part as it is to 12 Output as bit data. On the other hand, the second converter 14
If the input data of 0 has a value on the negative side, the sign bit is output as a "1" signal, and the data part is converted to LSB by inverting all bits.
It has the function of adding +1 to Furthermore, latch circuit 4
If the data latched by ₀₁ is positive data, the data (12 bits) is output from the output terminal A of the latch circuit ₄₀₁ , and the data (12 bits) is output from the output terminals B and C.
A “1” signal and a “0” signal are respectively outputted from the DA converter 411, and the data is input to the DA converter ₄₁₁ .
Further, a signal "1" causes the switch 143 to close, and a signal "0" causes the switch 142 to open. At this time, the output data from the DA converter ₄₁₁ is inputted to the plus input terminal of the operational amplifier 144 via the switch 143. If the data latched by the latch circuit ₄₀₁ is negative data, the data (12 bits) is similarly output from the output terminal A of the latch circuit ₄₀₁ , and a "0" signal and a "0" signal are output from the output terminals B and C. A “1” signal is output, and the data is input to the DA converter 41,
Further, a "0" signal causes switch 143 to open, and a "1" signal causes switch 142 to close. At this time, the output data (analog signal) of the DA converter ₄₁₁ is sent to the operational amplifier 144 via the switch 142.
is input to the negative input terminal of Since the first upper keyboard musical tone forming circuit 23 is configured as described above, when one scanning period starts (the content of the 96-decimal counter is 0), the sine table 14 of the time-division broken shape generating circuit 2 outputs Of the sine amplitude value S (13-bit sign logarithm display data), the sign bit SB is sent to the control input terminal C of the first converter 136, and the content of the sign bit (“1”) is sent to the first converter 163. ” signal or “0” signal). The data of the upper 10 bits of the sine amplitude value S is sent to the adder 37 together with the 10 bit signal UKO1 outputted from the Lin to log converter 110 in the first upper keyboard tone forming circuit 17.
₁ to input terminals A ₁ to A ₁₀ and B ₁ to B ₁₀ and added. The data of the lower 6 bits of the added value of the adder ₃₇₁ is sent to the log-lin converter ₃₈₁ together with the data of the lower 2 bits of the sine amplitude value S, and the data is converted from logarithmic display data to linear display data (absolute value display). data) and then input to the shifter 135. Also, the top 4 of the added value of adder 37 ₁
Bit data (7th to 10th bits) are input to corresponding input terminals a, b, and cd of the shifter 135, respectively. The log-Lin converter 38 ₁ is composed of ROM (read only memory), and the OR gate 12
The lower 8 bits of the 12-bit logarithmic display data outputted from 3 to 134 are input as address signals. That is, the converter 38 ₁
, the 12-bit logarithmic display data is converted into the logarithmic display data of the relatively larger value among the logarithmic display data (the part where the amplitude value of the sine amplitude value S is large).
Only converted values for "00000000" to "11111111" are stored. Of the 12-bit logarithmic display data, data for which a "1" signal is output to any of the upper four bits is data with a small value (because the adder 37 (The output data of ₁ is data in sign/logarithm representation) Therefore, such small value data is 1 bit to 4 bits depending on the input state of the "1" signal at the input terminals a to d of the shifter 135. is shifted to. In this way, the log-Lin converter 38 ₁
By configuring the shifter 135 as
The storage capacity of the ₈₁ can be reduced. The output of the first converter 136 is accumulated by an adder 139 during the one scanning period, and the final accumulated value at the end of the scanning period is converted into sign/absolute value display data by a second converter 140, and the latch circuit 40 is latched to. Among the data latched by the latch circuit 40, the data representing the amplitude value is converted from digital data to analog data by the DA converter ₄₁₁ . Here, if the data is on the plus side than the reference value, switch 14
3 is closed, the analog output of the DA converter ₄₁₁ is sent to the plus input terminal of the operational amplifier 144.
On the other hand, if the latch data is negative than the reference value, the switch 142 closes.
The analog output of DA converter 41 ₁ is operational amplifier 1
44 and is inverted. In this way, the analog output of the DA converter ₄₁₁ is output as is or inverted depending on whether it is positive or negative at the operational amplifier 144. The signal is then sent to the sound system 6 via the variable resistor VR ₁ , mixed with data generated by the tone generation circuits 4 and 5 of other keyboards, and emitted as a sound. The second upper keyboard musical tone generation control circuit 19, the lower keyboard musical tone generation control circuit 27, and the pedal keyboard musical tone generation control circuit 32 are each provided with a coupler control circuit, and these coupler control circuits also have a prohibition having the above-mentioned effect. A circuit is provided. The configuration of these inhibition circuits is as follows: the inverter 95, the AND gate 96
Although it is constructed in the same manner as the prohibition circuit formed by 99, a detailed description of its construction will be omitted. Furthermore, explanations of other specific structures within the upper keyboard musical tone generating circuit 3 and the specific structures of the musical tone generating circuits 4 and 5 of the lower keyboard and pedal keyboard will be omitted since they are not directly related to the gist of the present invention. Next, the specific operations of the circuits 1, 2, 6, 15 to 18, and 23 in the electronic musical instrument of the above embodiment are as follows.
This will be explained with reference to the operational waveform diagram shown in FIG.
Within one scanning period in the keyless state,
Assume that three keys C ₁ , D ₂ , and G# ₅ on the upper keyboard 15 are pressed at the same time. a decimal counter 8 of the timing signal generation circuit 1;
Due to the operation of the octal counter 9, the one scanning period starts when the content of the 96-decimal counter is 0. At this time, according to the above-described operations of the decoder 10 and the parallel/serial converter 16,
The key switch scanning circuit 43 of the upper keyboard circuit 15 operates, and the parallel/serial converter 16 outputs a time division multiplexed signal UKO indicating the pressed state of each key from the first octave key _C1 . Since key C ₁ is currently pressed, at the start of the next scanning period following the scanning period in which key C ₁ was actually pressed (the contents of the 96-decimal counter; see Figure 11), key pressed
The time-division multiplexed signal UKO of "1" signal for _C1 is output, and is input to the input terminal (point A) of the shift register 87 (FIG. 7) in the first upper keyboard tone generation control circuit 17.
is input. Continuing with this point A,
When the contents of the 96-decimal counter are 14 and 56, respectively, the time division multiplex signal UKO of the "1" signal for the pressed keys D ₂ and G# ₅ is output. shift register 87
Time division multiplex signal UKO of “1” signal input to
are sequentially shifted to the subsequent shift registers 88 to 94, and the "1" signals DUKO1 to DUKO1 to each output terminal (point B to point I) of the shift registers 87 to 94 are sequentially shifted.
Output as DUKO8. FIG. 11 shows the relationship between the output states of the signals UKO and DUKO1 to DUKO8 output to the points A to I and the contents of the 96-decimal counter within this one scanning period. Note that the delayed signals DUKO6 to DUKO8 of the time division multiplexed signal UKO for the pressed key G# ₅ are blocked by the action of the inhibiting circuit consisting of AND gates 96 to 99 controlled by the inverted signals 0 to 12 of the timing signals SY0 to SY12. The inconvenience that musical tones of low pitches (C ₁ , D# ₁ , G# ₁ ) are generated in response to the depressed key G# ₅ is reliably prevented. Note that in this example, key _C1 is actually pressed. Each point A above
~UKO with “1” signal on I, DUKO1 ~ DUKO8
When outputting, the corresponding weighting circuits 100 to 10
At the same time from 8, each drawbar 18 ₁ ~
18 3-bit data according to the setting status of ₉ K ₁
~ _K9 is output and input to adder 109.
Adder 109 adds input data K ₁ to _{K 9} for each bit time (time slot), and uses the addition result as 6-bit data K.
It is sent to a Lin-log converter 110. converter 110
It also logarithmically transforms the input data K for each bit time and outputs it as a 10-bit signal UKO1. This signal UKO1 is sent to the adder ₃₇₁ (FIG. 10) of the first upper keyboard tone forming circuit 23. In parallel with the above operation, the frequency number memory 12 in the time-division waveform generation circuit 2 uses the bit output signals N ₁ to _{N 4} and B ₁ to B ₃ of the counters 8 and 9 to set each tone pitch C ₁ to B ₈ . The addresses corresponding to are specified sequentially. As a result, frequency numbers R corresponding to pitches C ₁ to B ₈ are sequentially output and input to the accumulator 13 . The accumulator 13 has each pitch C ₁ to _{C 8} .
Since the frequency numbers R corresponding to , are independently and repeatedly added in sequence, and each cumulative value qR is sent to the sine table 14, the sine table 14 outputs the sine amplitude of each pitch, which is logarithmic table data. The value S is sequentially outputted in a time-sharing manner to the adder 37 ₁ of the first upper keyboard musical tone forming circuit 23 (FIG. 11).
sent to. Adder 37 ₁ receives the signal
Since UKO1 (10 bits) and data of the upper 10 bits of the sine amplitude value S are input, both input data are added at the adder ₃₇₁ . During the one scanning period, for example, when the content of the 96-decimal counter is 0, the content of the signal UKO1 is equal to the drawbar 1.
Since the value corresponds to the setting value of ₈₁ , and the content of the sine amplitude value S is a value corresponding to the key _C1 , the data from both signals is added to the adder _371.
is added by This addition data is input to the accumulator ₃₉₁ , undergoes the above-described processing, and is stored. The adder ₃₇₁ receives signals UKO, DUKO1 to DUKO1 shown in FIG. 11 within this one scanning period.
A plurality of signals UKO1 based on DUKO8 are input sequentially, and the corresponding sine amplitude values S output at the same time are also input sequentially, so both input signals are added each time and the added data is sent to the accumulator 39.
Send to ₁ . Therefore, the accumulator ₃₉₁ adds up the input addition data and stores it. When the signal SY95 is output at the end of one scanning period, the final cumulative value held in the accumulator ₃₉₁ is latched in the latch circuit ₄₀₁ , the data in the accumulator ₃₉₁ is cleared, and the latch circuit The data latched at ₄₀₁ is sent to the sound system 6. If data is simultaneously sent to the sound system 6 from the lower keyboard musical tone generating circuit 4 or the pedal keyboard musical tone generating circuit 5, the data from the circuit 3 is mixed with the data from the other circuits 4 and 5 to generate musical sounds. pronounced as The above-mentioned operation is similarly repeated for each scanning period while the keys C ₁ , D ₂ , and G# ₅ are pressed, and musical tones continue to be produced. Also, when any key is released, the signal UKO, DUKO1 to DUKO8 is generated by that key.
are no longer output, and therefore the musical tones based on these signals disappear. In the above embodiment, one scanning period was 96 bit times, and the total delay time of the delay circuit constituting the coupler control circuit was 48 bit times, but these values can be set to arbitrary values. In this case, the configuration of the inhibiting circuit can be modified accordingly. Further, in the above description, the present invention is applied to an electronic musical instrument having multiple keyboards, but the present invention can also be applied to an electronic musical instrument having one keyboard. As explained above, the present invention has a simple configuration in which a prohibition circuit is added to an electronic musical instrument having a coupler control circuit previously proposed by the present applicant, thereby shortening one scanning period of key switch scanning and changing the key state ( This is extremely convenient for performance since the detection of the key pressed state and key released state can be detected without delay, and therefore the performance state of the player can be reliably followed. Furthermore, since it is possible to reliably prevent undesired musical tones from being emitted by the signal obtained by delaying the time division multiplexed signal by the coupler control circuit, it is possible to provide an electronic musical instrument that can reliably obtain the desired coupler effect.

[Brief explanation of the drawing]

The drawings show an embodiment of the electronic musical instrument of the present invention.
Figure 1 is a block diagram showing the overall configuration of the electronic musical instrument of the same example, Figures 2 and 3 are waveform diagrams of various signals that control the basic operations of the electronic musical instrument of the same example, and Figure 4 is the same example. Figure 5 is a diagram of the key switch circuit for the upper or lower keyboard of an electronic musical instrument, Figure 5 is a diagram of the key switch circuit for the pedal keyboard of the same example, and Figure 6 is a circuit diagram of the parallel/serial converter of the same example. , FIG. 7 is a configuration diagram of the first upper keyboard tone generation control circuit in the upper keyboard tone generation circuit of the same example, FIGS. 8 and 9 are specific configuration diagrams of the drawbars of the same example, and FIG. FIG. 11 is a diagram illustrating the operation waveforms of the first upper keyboard tone generation control circuit. 1... Timing signal generation circuit, 2... Time division waveform generation circuit, 3... Upper keyboard tone generation circuit, 4...
... Lower keyboard musical tone generation circuit, 5 ... Pedal keyboard musical tone generation circuit, 6 ... Sound system, 7 ... Decoder, 8 ... Oscillator, 9, 10 ... Counter, 11
...Decoder, 12 ...Frequency number memory, 1
3...Accumulator, 14...Sine table, 15...Upper keyboard, 16...Parallel/serial converter, 17...First upper keyboard tone generation control circuit, 18,18 ₁ to 18...Drawbar (controller) ), 19...Second upper keyboard musical tone generation control circuit, 2
0,20 ₁ to 20... Drawbar (operator), 3
7 ₁ to 37 ₂ ... Adder (multiplier), 39 ₁ , 3
9 ₂ ... Accumulator, 40 ₁ , 40 ₂ ... Latch circuit, 41 ₁ , 41 ₂ ... DA converter, 25
...Lower keyboard, 26...Parallel/serial converter, 27...Lower keyboard musical tone generation control circuit, 28,2
8 ₁ ~ 28 ₂ ... Drawbar (operator), 30...
...Pedal keyboard, 31...Parallel/serial converter, 32...Pedal keyboard musical tone generation control circuit, 3
3,33 ₁ to 33 ₇ ... Drawbar (operator),
37 ₃ , 37 ₄ ... Adder (multiplier), 39 ₃ ,
39 ₄ ... Accumulator, 40 ₃ , 40 ₄ ...
Latch circuit, 41 ₃ , 41 ₄ ...DA converter, 4
3, 44, 45...Key switch circuit, 87-94
...Delay circuit, 95-99 ...Prohibition circuit, 100
~108...Weighting circuit, 109...Adder.

Claims (1)

[Claims] 1 A plurality of key switches provided corresponding to each of a plurality of keys are sequentially scanned at a predetermined speed, and a time division multiplexed signal indicating the key press state of each key is sent to each key within one scanning period. a key switch scanning circuit that generates signals for each corresponding time slot; a time-division waveform generation circuit that generates a waveform signal corresponding to the pitch of each key in a time-division manner in synchronization with the key switch scanning; A coupler control circuit that inputs a signal and outputs the signal after a predetermined time delay, an output signal of the waveform signal generated from the time division waveform generation circuit, the time division multiplexed signal, and the coupler control circuit. In an electronic musical instrument, the electronic musical instrument is provided with a multiplier circuit for multiplying an output signal by a multiplier circuit, and a musical tone signal is obtained from the output signal of the multiplier circuit, in which the signal delayed by the coupler control circuit is generated in the next scanning period. An electronic musical instrument is provided with a prohibition circuit that invalidates the delayed signal when the signal is delayed.