JPS6117175B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an on-delay operation in which an output signal is turned on a certain period of time after an input signal is turned on, an off-delay operation in which an output signal is turned off a certain period of time after an input signal is turned off, and The present invention relates to a timer circuit that can arbitrarily switch between three types of operation modes: a one-shot multivibrator operation that outputs a square wave signal with a constant width in response to a change in a signal.

Conventionally, this type of timer circuit has been shown in FIG. As shown in the figure, three types of circuits are built in: a timer circuit 1 for on-delay operation, a timer circuit 2 for off-delay operation, and a timer circuit 3 for one-shot multivibrator operation. , 2, and 3 are selectively operated by interlocking changeover switches S1 and S2. In such a configuration, each of the three timer circuits 1, 2, and 3 is provided with overlapping time-limiting elements such as delay circuits, waveform shaping circuits, etc., resulting in a large number of circuit elements as a whole, which is expensive. It has no choice but to become a thing.

This invention was made in view of the above-mentioned conventional problems, and its purpose is to achieve the on-delay, off-delay, and one-shot multivibrator operations described above with a minimum number of circuit elements by sharing most of the circuit elements. An object of the present invention is to provide a timer circuit that can perform the following operations.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows a first embodiment of a timer circuit according to the present invention. This timer circuit has an input terminal IN to which a square wave input signal is applied, and an input terminal
a differentiating circuit 4 that outputs a pulse signal of a constant width in response to the rise of an input signal applied to IN;
a first exclusive OR circuit 5; a switching circuit for switching between inputting the input signal directly to one input terminal of the exclusive OR circuit 5 and inputting the output signal of the differentiating circuit 4; , an integrating circuit 6 that performs a delay operation in response to the fall of the square wave signal output from the exclusive OR circuit 5, and a second exclusive circuit to which the output signal of the integrating circuit 6 is applied to one input terminal. an exclusive OR circuit 7, an inverter 8 for inverting the output of this circuit 7, and a switching circuit for switching the logic of the signal applied to the other input terminal of both exclusive OR circuits 5 and 7, Depending on the switching state of the switching circuit, the exclusive OR circuit 7 and the inverter 8 are configured to obtain any one of an on-delay output, an off-delay output, and a one-shot multivibrator output signal.

Both switching circuits are comprised of switches S3, S4 and diodes D1, D2. As shown in the figure, the differentiating circuit 4 includes a capacitor C1, a resistor R1,
consisting of resistor R2, and when switch S3 is closed,
It operates only when the connection point side of resistors R1 and R2 is connected to ground line G via diode D1 and switch S3. When the switch S3 is open, the differentiating circuit 4 does not function and the input terminal IN is directly connected to one input terminal of the exclusive OR circuit 5 via the resistors R1 and R2.

Further, when the switch S3 is closed, the other input terminals (lower inputs in the figure) of both exclusive OR circuits 5 and 7 are connected to the ground line G via the diode D2, and the input logic becomes L level.Furthermore, when switch S3 is opened and switch S4 is closed, the logic at the other input ends of exclusive OR circuits 5 and 7 becomes L level via switch S4. Further, when both switches S3 and S4 are open, the other input terminals of exclusive OR circuits 5 and 7 are connected to power supply line +V via resistor R3, and the input logic becomes H level.

The integrator circuit 6 includes a transistor Q1 which is turned on via a resistor R4 when the output b of the exclusive OR circuit 5 is at H level, and a transistor Q1 which is driven to conduction through a resistor R4.
It consists of a resistor R5 and a resistor R6 connected in series between the collector of 1 and the power supply line +V, and a capacitor C2 connected in parallel with this resistor R6, and performs a delay operation by the discharging operation of this capacitor C2. It's getting old. Note that the resistor R6 is a variable resistor, and the delay time can be adjusted by adjusting the resistance value.

Next, a third explanation will be given for each of the on-delay operation, off-delay operation, and one-shot multivibrator operation of the timer circuit configured as described above.
The explanation will be given in order according to the waveform diagram in the figure.

First, the on-delay operation will be explained. In this case, the switch S3 is turned off to disable the differentiating circuit 4, and the switch S4 is also turned off to apply an H level input signal to the other input terminal of each of the exclusive OR circuits 5 and 7. As a result, exclusive OR circuits 5 and 7 each function as an inverter. In this state, as shown in the on-delay part of FIG. Direct input, therefore exclusive OR circuit 5
A signal obtained by inverting the input signal IN is generated at the output terminal b of the input signal IN. The transistor Q1 of the integrating circuit 6 receives the signal b
is conductive when is at H level, and its output signal c is at L level. From that state, signal b becomes L.
When the output signal falls to the high level, the transistor Q1 is turned off and the output signal c becomes the high level, but at that time, the capacitor C2 is discharged, so the operation in which the output signal c rises from the low level to the high level follows an exponential curve. It will be delayed. Shown in Figure 3
SL is the threshold level of the exclusive OR circuit 7, and the output signal c of the integrating circuit 6 is binarized and inverted at this threshold level SL in the exclusive OR circuit 7, Further, the signal is inverted by the inverter 8 and appears at the output terminal OUT. As a result, the output signal as shown in the figure
OUT turns on with a delay of a certain time T1 after the input signal IN turns on. This is an on-delay operation.

Next, off-delay operation will be explained. In this case, switch S3 is turned off in the same way as above, switch S4 is turned on, and exclusive OR circuits 5 and 7
Apply an L level input signal to the other input terminal of
The exclusive OR circuits 5 and 7 are made to function as non-inverters. As shown in FIG. 3, when the input signal IN which changes from the L level to the H level is applied, a square wave signal having the same polarity as the input signal IN appears from the exclusive OR circuit 5. Therefore, the integrating circuit 6 performs a delay operation in response to the fall of the input signal IN, and the signal OUT obtained by binarizing the output signal c of the integrating circuit 6 at the threshold level SL is as shown in the figure. It will turn off after a certain period of time T1 after the input IN turns off. This is off-delay operation.

The operation of the one-shot multivibrator will be explained. In this case, the switch S3 is turned on to effectively operate the differentiating circuit 4. As a result, an L level input signal is applied to the other input terminal of each of the exclusive OR circuits 5 and 7.
The switch S4 may be either on or off. As shown in FIG. 3, when a square wave input signal IN that changes from L level to H level is applied, the rising edge of this input signal IN is differentiated by the differentiating circuit 4, and a constant value is output from the differentiating circuit 4. A pulse signal of the same width is applied to one input terminal a of the exclusive OR circuit 5. At this time, since the exclusive OR circuit 5 functions as a non-inverter, the differentiated pulse from the differentiator circuit 4 appears as it is at its output terminal b. Integrating circuit 6 operates with a delay in response to the fall of signal b, and as shown in FIG. 2, its output signal c gradually becomes H level after signal b returns to L level. This signal c is binarized at the threshold level SL and the inverted output signal OUT becomes a pulse signal with a constant width T2 in response to the rise of the input signal IN, as shown in FIG. This is one-shot multivibrator operation.

FIG. 4 shows another embodiment of the timer circuit according to the present invention, which is basically the same as the embodiment shown in FIG. is reversed. Regarding this timer circuit, parts corresponding to those in FIG. 2 are denoted by the same reference numerals, and a description thereof will be omitted.

As is clear from the above explanation, the timer circuit according to the present invention has two states: a first state in which the input binary signal is output as is, and a second state in which the leading edge of the input binary signal is differentiated and output. An input circuit that can be switched (corresponding to the differentiator circuit 4, diode _D1 , and switch _S3 ), and a first exclusive circuit that outputs the exclusive OR of the logic of the signal obtained from the input circuit and the set logic. Integration is started at either the rising edge or the falling edge of the signal obtained from the exclusive OR circuit (corresponding to the exclusive OR circuit 5) and the first exclusive OR circuit, and is reset at the other point. a second exclusive OR circuit (corresponding to the exclusive OR circuit 7) that obtains the exclusive OR of the logic of the signal obtained from the integration circuit and the set logic. a logic setting circuit (corresponding to a resistor R ₃ and a switch S ₄ ) capable of switching each logic of the first and second exclusive OR circuits in conjunction with the opposite logic; It is characterized by this.

Therefore, after setting the input circuit to the first state, if each logic of the first and second exclusive OR circuits is appropriately set to either "H" or "L", the first As a result, the exclusive OR circuit functions as either an inverter or a converter, so the integrating circuit integrates either the rising edge or the falling edge of the input binary signal, which is then converted into a waveform by the second exclusive OR circuit. As a result of the shaping, the function of an on-day delay timer or an off-day delay timer is achieved.

On the other hand, if the input circuit is set to the second state, a differential waveform is obtained from the input circuit, and this is waveform-shaped by the first exclusive OR circuit and converted into a minute width rectangular pulse. By passing this further through an integrator circuit and a second exclusive OR circuit, a one-shot pulse responsive to the leading edge of the input binary signal is obtained, and a one-shot multivibrator function is achieved. be.

In addition, when achieving the above on-delay, off-delay timer functions, and one-shot multivibrator functions, the first exclusive OR circuit, the integrating circuit, the second exclusive OR circuit, etc. can be shared, so this type of timer The circuit can be manufactured at low cost.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a conventional timer circuit.
FIG. 2 is a circuit diagram showing one embodiment of the timer circuit according to the present invention, FIG. 3 is a waveform diagram showing the operation of the timer circuit in FIG. 2, and FIG. 4 is another embodiment of the timer circuit according to the present invention. FIG. 2 is a circuit diagram showing an example. 4...Differentiating circuit, 5...First exclusive OR circuit, 6...Integrator circuit, 7...Second exclusive OR circuit, S3, S4...Switches forming a switching circuit.

Claims (1)

[Claims] 1. A first state in which the input binary signal is output as is, and a second state in which the leading edge of the input binary signal is differentiated and output.
a first exclusive OR circuit that outputs an exclusive OR of the logic of the signal obtained from the input circuit and the set logic; An integration circuit that starts integration at either the rise or fall of the signal obtained from the OR circuit and is reset at the other time, the logic of the signal obtained from the integration circuit, and the set logic. a second exclusive OR circuit that obtains an exclusive OR; a logic setting circuit that can switch each logic of the first and second exclusive OR circuits in conjunction with the opposite logic; A timer circuit comprising: