JPH058609B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a multifunctional timer circuit equipped with a mode changeover switch.

[Background Art] Conventionally, a multi-function timer circuit in which one timer can be switched and used as an on-delay timer, an off-delay timer, etc. has been used by switching each circuit with a rotary switch as shown in FIG. However, this configuration has disadvantages in that the delay circuits and logic circuits common to each circuit are redundantly provided, which is not only uneconomical but also increases the external size.

[Object of the Invention] The present invention has been made in view of the above points, and an object thereof is to construct a timer circuit having five functions as shown in Fig. 4 in a compact size using as few components as possible. It is something.

[Disclosure of the Invention] The timer circuit of the present invention applies an input signal to a monostable multivibrator by passing it through first and second exclusive OR circuits and a first AND circuit, and applies the output of the monostable multivibrator to a first AND circuit. The output signal is passed through the first switch, the OR circuit, the third exclusive OR circuit, and the second AND circuit, and the level of the other inputs of the first and third exclusive OR circuits is switched to L. A second switch, a third switch that switches the level of the other input of the second exclusive OR circuit to L, and a third switch that switches the other input of the first AND circuit to L by the inverted output of the monostable multivibrator. A fourth switch and a fifth switch that adds the output of the first exclusive OR circuit to the other inputs of the OR circuit are provided, and are set to H level by the above input signal and inverted to L level by the reset input signal. The output of the flip-flop is used as the other input of the second AND circuit, and the second and third outputs of the third AND circuit inserted into the reset input circuit are
input to L using the second and third switches respectively.
It uses a monostable multivibrator, a flip-flop, and a small number of gates and switches.
Normal mode outputs the input state as is, one shot mode outputs a signal with a fixed time width,
On-day-lay mode that performs on-day-lay operation,
Off-delay mode that performs off-delay operation,
The feature is that it is possible to switch between five latch modes in which the input signal is held.

The present invention will be described in detail below based on the embodiment shown in FIG. 1. An input signal applied to the input terminal SIN causes the first exclusive OR circuit EOR ₁ and the second exclusive OR circuit EOR ₂ to and the first AND circuit
Monostable multivibrator MUL through AND ₁
added to. Monostable multivibrator MUL
The Q output of is connected to the OR circuit via the first switch _S1 .
Added to OR ₁ , and a third exclusive OR circuit
It passes through EOR ₃ and second AND circuit AND ₂ to become an output signal OUT. In addition, a second switch S2 switches the level of other inputs of the first and third exclusive OR circuits EOR ₁ and EOR ₃ to L, and a second switch _S2 switches the level of other inputs of the second exclusive OR circuit EOR ₂ to L. A third switch S ₃ to switch to L and a monostable multivibrator
The first logical product circuit AND ₁ is generated by the inverted output of MUL.
A fourth switch _S4 that switches other inputs to L and the output of the first exclusive OR circuit _EOR1 are connected to an OR circuit.
A fifth switch _S5 is provided which is added to the other input of _OR1 , and the output of the flip-flop FF, which is set to H level by the above input signal and inverted to L level by reset input signal RIN, is connected to a second logical product. The second and _third AND circuits of the third AND circuit AND 3 are inserted into the reset input circuit and are used as other inputs of the circuit AND ₂ .
input to the second and third switches S ₂ and
It is configured to switch to L level at _S3 .
In this embodiment, a D timer flip-flop is used as the flip-flop FF, and the output of the fourth AND circuit _AND4 , which has its Q output as one input and the input signal SIN as the other input, and the third The output of the AND circuit _AND3 is added to the second OR circuit _OR2 , and its output is used as the clock input CP of the flip-flop FF, and the inverted output of the flip-flop FF is connected to its D input and the third AND circuit OR2.
It is used as the fourth input of AND ₃ . In the same figure, R ₁ , R ₂ , R ₃ are pull-up resistors, R ₄ , R ₅ are pull-down resistors, and C ₁ , R ₆ and C ₂ , R ₇ are monostable multivibrators when the power is turned on.
Capacitors and resistors are used to set the initial states of MUL and flip-flop FF, and Cx and Rx are capacitors and resistors that are used to set the pulse width of the output of the monostable multivibrator MUL.

FIGS. 2a to 2e are timer charts showing the operation of each mode. a is normal mode, Fig. 1 b
As shown in the figure, all switches except the fifth switch _S5 are off, and the signal input SIN is inverted by the first exclusive OR circuit EOR ₁ , and further inverted by the third exclusive OR circuit EOR _3. and the input state remains the same.
Output to the OUT terminal. b is in one shot mode, switches S ₁ , S ₂ and S ₄ are on,
The output of the monostable multivibrator MUL is inverted at the rising edge of the input signal SIN, and returns after the time T set by Cx and Rx. Therefore, a signal with a pulse width T is outputted to the output terminal OUT from the rising edge of the input signal. In the on-delay mode, switches S ₁ , S ₃ , and S ₅ are turned on, and the output of the monostable multivibrator MUL is inverted at the rising edge of the input signal SIN, and the mode returns after T time. Therefore, the output terminal
An output signal appears at OUT after T time from the rise of the input signal. Of course, if the input signal has already returned to the L level after time T, no output signal will appear. d is an off-delay mode, switches S ₁ , S ₂ , S ₃ , and S ₅ are turned on, and the output of the monostable multivibrator MUL is inverted at the falling edge of the input signal SIN and returns after T time. Therefore, the output terminal OUT becomes H level at the rising edge of the input signal,
It returns to L level after T time from the fall of the input signal. e is latch mode, all switches
S ₁ , S ₂ , S ₃ , S ₄ , and S ₅ are off, and the inverted output of flip-flop FF becomes H level at the rising edge of input signal SIN, and returns to L level at the rising edge of reset input signal RIN. During this time, the output of the third exclusive OR circuit _EOR3 is held at H level, so the inverted output of the flip-flop FF appears as it is at the output terminal OUT. In this way, the circuit shown in Figure 1 uses one monostable multivibrator, one flip-flop, and a small number of gates, allowing you to select any of the five modes, and by using a DIP type switch. , an extremely compact multifunctional timer circuit can be constructed.

FIG. 3 shows another embodiment, in which a first input terminal SIN ₁ and a second input terminal SIN ₂ are provided as input terminals, and in the latch mode, the reset is applied by the first input SIN ₁ . In other modes, the operation is performed by logical product of both inputs. The switch _S6 is for switching between the 10 second range and the 1 second range, and the time is set using the variable resistor _VR1 . Also, switch S ₇ has the first input SIN ₁
This is for switching between active H and active L. Note that the second input SIN ₂ operates at an active low level, and the non-contact output OUT ₁ operates at an active high level. Further, in this embodiment, an output from relay Ry ₁ can also be obtained.

[Effects of the Invention] As described above, according to the present invention, there is an advantage that a multifunctional timer circuit that can arbitrarily select five types of functions can be constructed with a small number of components at a small size and at low cost.

[Brief explanation of the drawing]

FIG. 1a is a block circuit diagram showing an embodiment of the timer circuit of the present invention, FIG. 1b is a state diagram of the switch in each mode of the above, and FIGS. 3A is a block circuit diagram showing another embodiment of the timer circuit of the present invention, FIG. 3B is a state diagram of the switch in each mode of the same, and FIG. 4 is a block circuit diagram of a conventional example. MUL is a monostable multivibrator, FF is a flip-flop, EOR ₁ is the first exclusive OR circuit, EOR ₂ is the second exclusive OR circuit, EOR ₃ is the third exclusive OR circuit, AND ₁ is the The first AND circuit, AND ₂ is the second AND circuit, AND ₃ is the third AND circuit.
AND circuit, OR ₁ is OR circuit, S ₁ , S ₂ , S ₃ ,
_S4 and _S5 are the first to fifth switches, SIN is the input signal terminal, RIN is the reset input signal terminal, and OUT is the output signal terminal.

Claims (1)

[Claims] 1. The input signal is applied to the monostable multivibrator through the first and second exclusive OR circuits and the first AND circuit, and the output of the monostable multivibrator is applied to the first switch, the OR circuit, and the third AND circuit. a second switch that outputs the output signal through an exclusive OR circuit and a second AND circuit, and switches the level of other inputs of the first and third exclusive OR circuits to L; a third switch that switches the level of the other input of the logical OR circuit to L; a fourth switch that switches the other input of the first AND circuit to L by the inverted output of the monostable multivibrator; and a first exclusive switch. A fifth switch is provided to apply the output of the logical OR circuit to the other inputs of the OR circuit, and the output of the flip-flop, which is set to H level by the input signal and inverted to L level by the reset input signal, is connected to the second AND circuit. The second and third inputs of a third AND circuit inserted into the reset input circuit are configured to be switched to L level by the second and third switches, respectively. timer circuit.