JPS6118787B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention has two sets of computer units capable of executing at least one of the four arithmetic operations, and each of the two sets of calculator units is individually instructed to perform an operation by a key, and the results of the calculations are individually displayed. Regarding multicalculators configured to
The present invention provides a multicalculator configured to mutually transfer data displayed on both of the above-mentioned two sets of computer units and to use the transferred data for further calculations. With conventional computers, if you wanted to perform another calculation in the middle of one calculation, you had to abandon the original calculation. The present invention seeks to eliminate these drawbacks by providing two sets of independently calculating devices. Furthermore, the data obtained through interrupt calculations is transferred as is and used as data related to the original calculation, which eliminates the hassle of having to take the trouble of entering numbers while looking at the interrupt calculation results. Interrupt calculations are suitable, for example, for simplifying complex mathematical expressions. In other words, conventionally, calculations are performed by rearranging mathematical formulas and performing multiplication and division first. This recombination is tricky. For example, A
When calculating xB+CxD=, do AxB to load memory, then do CxD. Then press the addition key □+ and press the memory recall key.

Press [Formula] and then press the □= key. It is difficult to use because the memory contents are not displayed, and the key operations are cumbersome. With the multicalculator of the present invention, A×
For example, calculate B using the calculator section on the left, and calculate C×D.
You can do this on the right side, add both values by pressing the □ + key, and press the instruction key to put the answer on either the left or the right side, and you can do it without thinking too hard. Of course, it can also be used as just a memory, and the calculation results of the left side computer section can be transferred to the right side and recalled after performing other calculations, or the data stored in memory and the results of other calculations can be used for mutual calculations. can. Also, the display is always visible and easy to read. In addition, these controls use two 1-map microprocessors of the same type, except for the key part.
Since the interconnections are matched, there is an advantage that there are very few wiring errors. Of course, since the same microprocessor can be used, costs can be reduced. Examples of the present invention will be described below. FIG. 1 is a perspective view showing the appearance of an embodiment of the present invention. In FIG. 1, the cabinet CA has a first key group _K1 and a corresponding display section _DSP1 . On the right side is the second key group K ₂ and its corresponding display.
There is DSP ₂ . K ₀ is a key group that instructs mutual transfer or mutual operation between the left and right computer sections. The functions of each key included in the key group _K0 are shown below. Assuming that the data in the computer section on the left is X, the data in the computer section on the right is Y, and the memories are M ₁ and M ₂ , the □← key is the key that instructs the execution of Y→M ₁ , and the □→ key is , X→M ₂ The □× key instructs to execute X×Y, □÷ key instructs to execute X÷Y, □＋ key instructs to execute X+Y The □- key is a key that instructs the execution of X-Y. If you press the □×, □÷, □+, □- keys and then press the □← key, the answer will be in _M1 , and if you press the □→ key, the answer will be in _M2 .

The [Formula] key is used to simultaneously clear the contents X and Y of _M1 and _M2 . FIG. 2 is a block diagram of the same embodiment. The calculation section on the left side consists of a first one-chip microprocessor CPU ₁ , a first key group K ₁ and a first display section DSP ₁ . The calculation section on the right side has a second one-chip microprocessor CPU ₂ , a second key group K ₂ , a key group K ₀ , a second
Consists of display section DSP ₂ . CG is an oscillator that operates CPU ₁ and CPU ₂ at the same frequency. FIG. 3 is a specific wiring diagram of FIG. 2. CPU ₁ and CPU ₂ are the same microprocessor, and the internal configuration is shown in FIG. Below is an explanation of the internal configuration of the CPU, an explanation of the instruction codes that make up the ROM that operates the CPU, and
The main processing operations of the CPU will be explained. (Circuit configuration of CPU) RAM is a random access memory, and input/output is performed in units of 4 bits, and desired digit contents can be input/output by specifying the digit address and file address. BL is the memory RAM digit address counter, DC ₁ is the memory RAM digit address decoder,
BM is the memory RAM file address counter, DC ₂ is the memory RAM file address decoder, and AD ₁ is the adder. It operates as a subtracter when the control command 〓 is given, and as an adder when it is not given. . AD ₂ is an adder, G ₁ is an adder/subtractor
Numeric value 1 or operand I _A to one input of AD ₁
This gate outputs either I when a control command is given, and I _A when it is given. G ₂ is a memory digit address counter
The input gate of BL outputs the output of the adder/subtractor AD when , the operand I _A when , and the operand I _B when . _G3 is a gate for supplying either the numerical value 1 or the operand I _A to one input of the adder/subtractor _AD2 ;
When , operand I _A is output. G ₄ is the input gate of memory file address BM, when , the output of adder AD ₂ is input, when is the operand I _A ,
When , the contents of the accumulator ACC are output.
G ₅ is the memory RAM file selection gate, DC ₃
is the operand I _A decoder, which decodes the operand I _A and gates the signal specifying the desired bit in the memory.
Let G ₆ input. _G6 is the input gate of the memory RAM, and when a control command is given, the desired bit of the memory specified by the operand decoder _DC3 is set to 2.
It has a built-in circuit that inputs a binary number 1 and inputs a binary number 0 to the desired bit of the memory specified by _DC3 , and outputs the contents of the accumulator ACC. ROM is a read-only memory, and PL is a program counter that specifies the desired step of the read-only memory ROM. _DC4 is the step access degoder of the read-only memory ROM, _G7 is the output gate of the read-only memory ROM, and when the flip-flop (F/F) J is set, the ROM is Output instruction decoder
Transmission to DC ₅ is cut off. DC ₅ is an instruction decoder that decodes the instruction code from the ROM.The instruction code in the ROM is divided into an operation code part I ₀ and operand parts I _A and I _B. One of the control commands ~〓 is generated corresponding to the operation code. It also has a built-in circuit that determines that the opcode is accompanied by an operand and outputs the operand I _A or I _B as is at that time. AD ₃ is an adder and a program counter
This is to add the number 1 to the contents of PL and count up. _G8 is the input gate of the program counter PL, which outputs the operand I _A when .
When 〓, the contents of the program stack register SP are transmitted. , 〓 and 〓 for gate _G39 , the output of adder AD ₃ is not transmitted.
, 〓, 〓 transmits the AD ₃ output and automatically adds 1 to the contents of the program counter PL. FC is the flag F/F, G ₉ is the input gate of the flag F/FFC, when is the binary number I, when is the binary number 0
This is for inputting each into the flag F/FFC. _G10 is a key signal generation gate, which outputs the desired output of the memory digital address decoder _DC1 as it is when the flag F/FFC is in the reset state (0), and outputs the desired output of the memory digital address decoder DC1 as is when the flag F/FFC is in the set state ( ₁ ). I ₁ regardless of the output
It has a built-in circuit that sets the outputs of ~ _Io to 1 all at once.
ACC is an accumulator consisting of 4 bits,
X is a temporary (temporary storage) register consisting of 4 bits, _G11 is the input gate of temporary register do. AD ₄ is an adder, which is used to perform binary addition of the contents of the accumulator ACC and other data. During binary addition, if a carry occurs in the addition of the 4th bit, the _C4 output is set to 1. C is the carry F/F, _G12 is the input gate control command of the carry F/F, and if the fourth bit _C4 is 1, input 1 to the carry F/FC, and if _C4 is 0, For example, a circuit for inputting 0 to C is built-in. This is to input 1 to C when , and 0 to C when . _G13 is a carry C input gate for causing the adder _AD4 to perform binary addition including the carry, and transmits the output of the carry F/FC to the adder _AD4 at the time of 〓. G ₁₄ is adder AD ₄
The input gate transmits the output of the memory RAM when 〓 and the operand I _A when . F is 4
Output buffer register consisting of bits, G ₁₅
is the input gate of the output buffer register F, which transmits the contents of the accumulator ACC and inputs it to F when . SD is an output decoder for decoding the contents of the output buffer register F and converting it into display segment signals SS ₁ to SS _o . W is an output buffer register, and SHC is for shifting all bit contents of the output buffer register W by 1 bit to the right at once, and operates when or occurs. This is a shift circuit for the output buffer register W. _G16 is the input gate of the output buffer register W, and when , 1 is input to the first bit of W.
When , the purpose is to input 0 to the first bit of W, and the output buffer shift circuit SHC operates immediately before inputting 1 or 0 to the first bit of W, so that it is input after shifting. It is assumed that N _p is the output control flag F/F, G ₁₇ is the output control flag F/F.
At the input gate of FN _p , input 1 when 〓, and input 0 when 〓. _G18 is an output control gate of the buffer register W, and is used to output the outputs of each bit of W at the same time only when the flag F/ _FNp is set (1). J is a jack F/F, IV ₁ to _{IV 4} are inverter circuits, G ₁₉
is the input gate of the switch F/FJ, and is used to transmit the state of the input KN ₁ to J when 〓.
However, since it is via inverter IV ₁ , KN ₁ =
When it is 0, J=1. G ₂₀ is the input gate of the switch F/FJ, and transmits the state of the input KN ₂ to J at the time of 〓. However, since it is passed through the inverter _IV2 , J=1 when _KN2 =0. G ₂₁ is the input gate of the jumper F/FJ, and it is used to transmit the state of the input KF ₁ to J at the time of 〓. However, inverter
Since it is via IV ₃ , J=1 when KF ₁ =0. G ₂₂ is the input gate of the jumper F/FJ, and is used to transmit the state of the input KF ₂ to J at the time of 〓.
However, since it is passed through the inverter _IV4 , J=1 when _KF2 . G ₂₃ is the input gate of the jack F/FJ, and it is used to transmit the state of the input AK to J when it is 〓. When AK=1, J=1. G ₂₄ is the input gate of Jersey F/FJ, input when 〓
This is for transmitting the TAB status to J. TAB=
1, J=1. G ₂₅ is a gate for setting the jumper F/FJ, and is used to input I to J when ≦.V ₁ is a comparator circuit that compares the contents of the memory digit address counter BL with predetermined data. , if they match, output 1 is generated, and the circuit operates when 〓 or 〓 is generated. The data to be compared is output from gate _G26 . G ₂₆ is a comparison value input gate to comparator circuit V ₁ ,
The comparison value n ₁ corresponds to a specific address value on the higher side that is often used for controlling the memory RAM. When 〓, output n ₁ as a comparison value, when 〓, output n ₂
Output to use as a comparison value. G ₂₇ is the input gate of the carry F/FJ.
When the content of FC is 1, input 1 to J. DC ₆ is a decoder for operand I _A , which decodes operand I _A and uses it to determine whether the content of a desired bit in the memory RAM is 1 or not. _G28 is a gate that transmits the bit contents specified by the operand decoder _DC6 of the memory RAM to the switch F/F, and operates when ≦. Make sure that J=1 when the specified bit of RAM is 1. V ₂ is a comparator circuit and an accumulator
Checks whether the contents of ACC and the contents of operand I _A are equal, and generates an output of 1 when they are equal.
It works when 〓. _V3 is a comparison circuit that checks whether the contents of the memory digit address counter BL and the contents of the operand _IA are equal.
When they are equal, output 1 is generated. It works when 〓.
_V4 is a comparison circuit that judges whether the contents of the accumulator ACC and the contents of the memory RAM are equal, and generates an output of 1 when they are equal. _G29 is a transmission gate for the addition fourth bit carrier _C4 to the judge F/FJ, and when 〓, _C4 is transmitted to F/FJ. _C4
When , J=1. FA is a flag flip-flop, and _G31 is the input gate of flag F/FF _A , which outputs 1 when ≦, and 0 when ≦. _G32
is the input gate of the switch F/FJ, and sets F/FJ to 1 when the flag F/FF _A is 1. F _B
is the flag F/F, G ₃₃ is the input gate of the flag F/FF _B , which outputs 1 when ≦, and 0 when ≦. _G34 is the input gate of the flag F/FJ and transmits the contents of the flag F/FF _B to F/FJ.
It works when 〓. _G35 is the input gate of the switch F/FJ, which is operated by transmitting the contents of input B. When B=1, J=1. _G36 is the input gate _of the accumulator ACC.
IV ₅ inverts and transmits the contents of the accumulator ACC. 〓 transmits the contents of memory RAM,
When , the contents of operand _IA are transmitted. When , the 4-bit contents of inputs k ₁ to k ₄ are transmitted. 〓
When , the contents of stack register SA are transmitted.
IV ₅ is an inverter circuit, and SA is a stack register whose output is led out of the system. The output of SX is led out of the system using a stack register. _G37 is the input gate of stack register SA,
〓, transmits the contents of Asayumulator ACC. _G38 is the input gate of stack register SX,
〓, the contents of temporary register X are transmitted. SP is the program stack register, _G39 is the input gate of the program stack register SP,
When 〓, the adder is added to the contents of the program counter PL.
This is to introduce the value added by 1 at _AD3 into the program stack register. Next, the table below shows an example of the instruction code written in the storage ROM of the CPU device, the instruction code name, operation content, and control commands generated based on the instruction code. In the table, A: Instruction code;
B: Instruction name, C: Content, D:
Indicates CPU control instructions.

【table】

【table】

[Table] Explanation of (C) 1 SKIP Do not execute the next program step command.
Only the program counter PL is incremented, essentially skipping. 2 AD Accumulator ACC contents and memory RAM
Add the contents in binary and input the addition result to the accumulator ACC. 3 Add the contents of the ADC accumulator ACC, memory RAM, and carry F/FC in binary, and input the addition result to the accumulator ACC. 4 ADCSK Performs binary addition of the contents of the accumulator ACC, memory RAM, and carry F/FC, inputs the addition result to the accumulator ACC, and if the fourth bit carry _C4 occurs as a result of this addition, moves to the next program step. . 5 Add the contents of the ADI accumulator ACC and the operand I _A in binary, and add the addition result to the accumulator.
In addition to inputting to ACC, the fourth
If bit carry _C4 occurs, the next program step is skipped. 6 Set the DC operand I _A to 1010 (decimal number 10),
As with the ADI instruction, by adding the contents of the accumulator ACC and this operand I _A in binary, the contents of the accumulator ACC are essentially added.
Add the decimal number 10 and enter the result in ACC. 7 Set SC Carry F/FC. (Input 1 to C.) 8 RC Reset the carry F/FC. (Input 0 to C.) 9 SM Decodes the contents of operand I _A and sets the desired bit in the memory specified by the operand. (Input 1.) 10 RM Decodes the contents of operand I _A and resets the desired bit in the memory specified by the operand. (Input 0.) 11 COMA Invert the contents of each bit of the accumulator ACC, take the 15's complement, and input it to the accumulator ACC. 12 Introduce operand I _A to LDI accumulator ACC. 13 L Saves the contents of memory RAM to the accumulator ACC.
At the same time, the operand I _A is input to the file address counter BM. 14 LI Saves the contents of memory RAM to the accumulator ACC.
At the same time, the operand I _A is input to the memory file address counter BM. Furthermore, memory digit address counter BL
to increase. However, when the content of BL is equal to the predetermined value _n1 , the next program step is skipped. 15 XD Memory RAM contents and accumulator ACC
At the same time, the operand I _A is input to the memory file address counter BM. Furthermore, the memory digit address counter BL is decreased. However, when the content of BL is equal to the predetermined value _n2 , the next program step is skipped. 16 X′ Memory RAM contents and accumulator ACC
At the same time, the operand I _A is input to the memory file address counter BM. 17 XI Memory RAM contents and accumulator ACC
At the same time, the operand I _A is input to the memory file address counter BM. Furthermore, the memory digit address counter BL is increased. However, when the content of BL is equal to the predetermined value _n1 , the next program step is skipped. 18 XD Memory RAM contents and accumulator ACC
At the same time, the operand I _A is input to the memory file address counter BM. Furthermore, the memory digit address counter BL is decreased. However, when the content of BL is equal to the predetermined value _n2 , the next program step is skipped. 19 LBLI Operand I Input to _A and memory digit address counter BL. 20 LB Operand I _A is input to memory file address counter BM, and operand I
Input _B to memory digit address counter BL. 21 ABLI Performs binary addition of the contents of memory digit address counter BL and operand I _A , and stores the addition result in BL. However, when the contents of BL are equal to the predetermined value _n1 , the next program is skipped. 22 ABMI Adds the contents of memory file address counter BM and operand I _A in binary, and adds the addition result.
Put it in BM. 23 T Inputs operand I _A to program step counter PL. 24 SKC If carry F/FC is 1, skip the next program step. 25 SKM Deciphers the contents of operand I _A , and if the desired bit in the memory specified by the operand is 1, skips the next program step. 26 SKBI Compares the contents of the memory digit address counter BL and the operand I _A , and if they are equal, skips the next program step. 27 SKAI Compares the contents of accumulator ACC and operand I _A , and if they are equal, skips the next program step. 28 SKAM Accumulator ACC contents and memory
Compare the contents of RAM, and if they are equal, skip the next program step. 29 SKN ₁ When the KN ₁ input is 0, skip the next program step. 30 SKN ₂ When KN ₂ input is 0, skip next program step. 31 SKF ₁ When KF ₁ input is 0, skip next program step. 32 SKF ₂ When KF ₂ input is 0, skip next program step. 33 SKAK When the AK input is 1, skips the next program step. 34 SKTAB When the TAB input is 1, skip the next program step. 35 SKFA Flag F/FF When _A is 1, skips the next program step. 36 SKFB Flag F/FF When _B is 1, skips the next program step. 37 WIS Shifts the contents of the output buffer register W by 1 bit to the right and inputs 1 to the first bit (most significant bit). 38 WIR Shifts the contents of the output buffer register W by 1 bit to the right and inputs 0 to the first bit (most significant bit). 39 NPS Buffer register W output control F/
Set FN _p . (Input 1.) 40 NPR Buffer register W output control F/
Reset FN _p . (Input 0.) 41 ATF Transfers the contents of accumulator ACC to output buffer register F. 42 LXA Loads the contents of accumulator ACC into temporary register X. 48 XAX Exchanges the contents of accumulator ACC and temporary register X. 44 SFA Set flag F/FF _A. (Input 1.) 45 RFA Reset flag F/FF _B. (Input 0.) 46 SFB Set flag F/FF _B. (Input 1.) 47 RFB Resets flag F/FF _B. (Input 0.) 48 SFC Set input test flag F/FF _c . (Input 1.) 49 Reset the RFC input test flag F/FF _c . (Input 0.) 50 SKB When input β is 1, skip the next program step. 51 KTA Introduce the contents of inputs k ₁ to _{k 4} to the accumulator ACC. 52 STPO Loads the contents of accumulator ACC into stack register SA and the contents of temporary register X into stack register SX. 53 EXPO Exchanges the contents of accumulator ACC and stack register SA, and exchanges the contents of temporary register X and stack register SX. 54 TML Transfers the contents of program counter P _L plus 1 to program stack register SP. Furthermore, operand I _A is introduced into program counter P _L . 55 RIT Transfers the contents of program stack register SP to program counter _PL . Next, Table 2 shows the relationship between the opcodes and operands stored in the ROM (read-only memory) in the CPU device.

【table】

[Table] Here, for example, read-only memory
Taking an example where the ROM output is 10 bits, instruction AD or COMA (see Table 1) will be output by instruction decoder DC ₅ and the 10 bit code will be 0001011000 or 0001011111 respectively.
It decodes and determines that it is, and generates the control command 〓, 〓, or 〓. On the other hand, in SKBI, the top 6 bits are
It is determined that it is 000110, and at this time, the lower 4 bits 0010 are treated as operand _IA . moreover
LB is judged by the upper 2 bits being 01,
At this time, the 3rd to 8th bits 001010 are operand I
The 9th and 10th bits, 11, are treated as _{operand IB .} operand
is a constituent part of an instruction word, and is a part that indicates data, the address where the next instruction is stored, etc., and can be called the address part of the instruction. Next, an example of the main processing operations of the above-mentioned CPU device (hereinafter referred to as a processing list) will be explained. (Processing list) (1) Introduce the same numerical value N to the desired area of memory RAM. (NNN→X) (2) Introduce a plurality of different predetermined numerical values into a desired area of memory. (N ₁ , N ₂ , N ₃ ...→X) (3) Transfer the contents of the desired area of the memory to another desired area of the memory. (X→Y) (4) Exchange the contents of a desired area of memory with the contents of another desired area of memory. (X←→Y) (5) Predetermined value N in the desired area of memory
Add or subtract binary. (X±N) (6) Add the contents of another area to the contents of the desired area of memory in decimal form. (X±Y) (7) Shift the contents of the memory in the desired area by one digit. (X right, X left) (8) Set or reset the 1-bit conditional F/F in the desired area of memory.
(Fset, Freset) (9) Change the contents of the 1-bit conditional F/F in the desired area of memory, and change the next program address based on the change result. (10) Check whether the digit content in the desired area of the memory is a predetermined value, and change the next program step based on the check result. (11) Check whether the contents of a plurality of digits in a desired area of the memory are all equal to a predetermined value, and change the program step based on the check result. (12) Judge whether the contents of the desired area of memory are smaller than a predetermined value, and change the next program step based on the result of the judgment. (13) Judge whether the contents of the desired area of memory are larger than a predetermined value, and change the next program step based on the result of the judgment. (14) Display the contents of the desired area of memory. (15) Determine the type of key switch that was pressed. Next, a specific example of executing the processes (1) to (15) above based on the instruction code will be described below according to the process list. (Specific example of processing list) (1) Introduce the same numerical value N to a desired area of memory. (NNN→X)

【table】

【table】

【table】

[Table] (2) Introduce a plurality of different predetermined values into a desired area of memory. (N ₁ , N ₂ , N ₃ …
→X) (Type 1) An example of introducing a 4-digit number N ₄ N ₃ N ₂ N ₁ into memory is shown. (The same applies to the introduction of arbitrary digits)

【table】

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[Table] (3) Transfer the contents of a desired area of memory to another desired area of memory. (X→Y)

【table】

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[Table] (4) Exchange the contents of the desired area of memory with the contents of another desired area of memory. (X←→Y)

【table】

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[Table] ▽

[Table] (5) Add or subtract a predetermined numerical value N to or from a desired area of memory.

【table】

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[Table] ▽

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[Table] ▽

[Table] (6) Add or subtract the contents of another area to or from the contents of the desired area of memory in decimal form.

【table】

【table】

【table】

[Table] (7) Shift the memory contents of the desired area by one digit.

【table】

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[Table] (8) Set or reset the 1-bit conditional F/F in the desired area of memory.

【table】

【table】

[Table] (9) Change the contents of the 1-bit conditional F/F in the desired area of memory, and change the next program address (step) based on the change result.

【table】

[Table] (10) Check whether the digit content in the desired area of memory is a predetermined value,
Change the next program address (step) based on the change result.

[Table] (11) Check whether the contents of a plurality of digits in a desired area of memory are all equal to a predetermined value N, and change the next address (step) based on the check result.

【table】

[Table] (12) Judge whether the contents of the desired area of memory are smaller than a predetermined value N, and change the next address (step) based on the judgment result.

【table】

[Table] (13) Check whether the contents of the desired area of memory are larger than a predetermined value N, and change the next program address (step) based on the check result.

【table】 (14) Display the contents of the desired area of memory.

【table】

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[Table] (15) Determines the type of key switch pressed. (Checks whether a key is pressed while displaying)

【table】

[Table] The above is an explanation of the main processing operations of the CPU device. The operation will be explained below. FIG. 5 is an operational state diagram of the calculation unit (CPU ₂ ) on the right side. The key group K ₀ in the center of FIG. 1 is included as described above. The four usual arithmetic calculations are general and have no relation to the present invention, so they will be omitted. It is assumed that the input value or the operation result is stored in memory _M2 . When no key in key group K ₀ is pressed, n ₄ to _{n 8} , n ₂₀ , n ₂₁ are in the NO state, so change the four arithmetic calculation key group K ₂ (represented by other keys) and change these. When neither is pressed, the contents of memory _M2 are displayed on DSP ₂ (n ₃₉ ). Proceed to n ₂₀ → n ₂₄ . Flag A will be explained later, but it is a key group.
Since this is set only when a key other than □→ or □← of _K0 is pressed immediately before, proceed to _n26 and accept the contents _M1 of the calculation section on the left into _M2 .
And it ends. That is, what is shown on the left
The contents of M ₁ are transferred to M ₂ and also displayed on DSP ₂ . The process proceeds as n ₂₁ →n ₂₂ , and since A is in the reset state, it proceeds to n ₂₃ . Then, conversely, the contents of _M2 are transferred to _M1 and the operation is reversed to that of the □→ key. Since the □+ key is pressed at n ₄ , the process progresses from n ₉ to n ₁₀ to n ₁₁ , and flags F ₁ , F ₂ , and A are set. Here A
is set, so when you press the □→ key, n ₂₀
Proceed as →n ₂₄ →n ₂₅ . The B set here is the memory of pressing the □→ key. Proceed as n ₂₅ →n ₂₇ , and then
Depending on the state of F ₁ and F ₂ in the case of n ₂₈ and n ₃₁ , when F ₁ = 1, F ₂ = 1, addition when F ₁ = 1, F ₂ = 0, subtraction F ₁ = 0, F ₂ When = 1, it is multiplication; when F ₁ = 0, F ₂ = 0, it is division. Here, F ₁ = 1, F ₂ = 1, so proceed to n ₂₉ , add the contents of memory M ₁ and memory M ₂ ,
Process the result into _M2 . A specific processing example of this part is shown in FIG. Transfer the contents of _M2 to _M3 using _m1 (the contents of _M2 remain unchanged). This is to leave the contents of _M2 as they were when pressing the □← key. and
_m2 transfers the contents of _M1 in CPU ₁ to _M2 in CPU ₂ (this process will be described later). Then, m ₃ calculates the answer using memories M ₂ and M ₃ in the usual way.
Ask for M ₂ . Then, perform M ₂ ←→M ₃ with m ₄ , and as a result, find the original number of operations in M ₂ and the answer in M ₃ . Then proceed to n ₃₄ . □→ key press, B=
1, so do M ₃ → M ₂ with n ₃₅ and return the answer to M ₂ . Therefore, as a result, the combination of □→ and □+ is M ₁
remains the same, and M ₂ becomes the new addition result. Since the process proceeds as n ₂₁ → n ₂₂ → n ₂₇ , B is not set and n ₃₄
→n ₃₆ and the contents of memory _M3 containing the answer
Transfer to _M1 . As a result, by pressing the □← key and the □+ key, the new addition result is entered into M _{1 while leaving M 2 as} it was. Multiplication and subtraction can also be processed using the same concept. At _n37 and _n38 , A and B are reset to their initial states, a series of processing is completed, and the display state is returned. In addition, M ₃ → M ₁ of n ₃₆ is processing between CPUs,
In order to unify the processing with _n23 , specifically, as shown in Figure 7, the contents of _M3 and _M2 are exchanged in _m5 , and the contents of _M3 are transferred to _M6 in _m6 via M2. Transfer to ₁ . the number
Return the original data that was transferred to _M3 with _m7 to _M2 . Note that since M ₁ →M ₂ and M ₂ →M ₁ are transfers between CPUs, special processing is performed. This will be explained with reference to FIGS. 8 and 9. FIG. 8 is an operating state diagram of CPU ₁ , and FIG. 9 is an operating state diagram of CPU ₂ . At n ₂₄ in Figure 5, do the A jigsaw and A≠1.
When (A=0), perform M ₁ → M ₂ with n ₂₆ . The processing is between the CPUs, and the operation state diagram on the left side of FIG. 9 is the operation of the CPU ₂ at this time. This is the process of M ₁ →M ₂ to which O ₁ and O ₁₃ correspond. When □→ is pressed and A=0, that is, when only the □→ key is pressed, proceed to n ₂₄ →O ₁ . The processing at O ₁ and O ₂ sets flags F _A and F _B , and issues a command to CPU ₁ to perform the processing operation "M ₁ → M ₂ ", which will be described later. Here, before explaining O3 _and below, a part of the processing on the CPU ₁ side will be explained with reference to FIG. CPU ₁ side is a normal key group, clear key

It contains [Formula] and looks like K1 in Figure ₁ . n′ ₃₉ is the clear key

In the processing of the key group excluding [Formula], n ₄₀ is a processing unit for setting numbers, calculations, etc. in response to pressing each key. n ₄₁ is clear key

n ₄₂ is the clear key in the press button part of [Formula]

This is the processing section that should be performed when [Formula] is pressed. If no key is pressed, proceed to n ₄₃ . n ₄₃ is
This is to change the input KF ₂ of CPU ₁ , and KF ₂ is
Since it is connected to the SA ₁ terminal of CPU ₂ (SA is 4 bits, the first bit is used),
When the SA ₁ terminal of CPU ₂ is ``1'', skip n <sub>44</sub> and go to n <sub>42</sub> ; when SA <sub>1</sub> is ``0'', jump from n ₄₄ to n ₄₅ (operand n ₄₅ of the T instruction of n ₄₄ ). correspond to the step). The SKF ₂ instructions here are:

【formula】 The process when a key is pressed will be described later.

[Formula] When the key is not pressed, SKF ₂ = 0, so proceed to n ₄₃ → n ₄₄ → n ₄₅ . The judgment of α=1 in n ₄₅ is for determining whether to process “M ₁ →M ₂ ” or “M ₂ →M ₁ ”. That is,
The α input terminal of CPU ₁ is connected to the flag flip-flop F _A of CPU ₂ , so when F _A = 1,
Go to n ₄₇ , and if F _A = 0, go to n ₄₆ . F _A is the aforementioned O ₁
It is set (becomes 1) by the SFA instruction in . Furthermore, when you press the □← key, A≠1 and M ₂ →
When you want to do M ₁ , as will be explained later, the SFA command is issued at O ₁₅ , so in the end A≠1, press the □→ key or □← key to process M ₁ → M ₂ or M ₂ → M ₁ . You'll be wondering what to do with this _N45 . When α≠1, _n46 displays the contents of register _M1 as is. Therefore, when no key is pressed, n' ₃₉ → n ₄₁ → n ₄₃ → n ₄₄ → n ₄₅ → n ₄₆ → n' ₃₉ →... is repeated to display the contents of M ₁ . □→Press O ₁ to flip flop the flag
When FA is set, α=1 of _n45 is satisfied, so proceed to _n47 . For n ₄₇ , β = 1, M ₁ →
It is determining whether to perform M ₂ or M ₂ → M _1. When the □→ key is pressed, the SFB command is issued with O ₂ , so the flag flip-flop F _B is also set. Proceed from n ₄₇ to n ₄₈ . _n48 is a reset of the flag flip-flop _FE , which will also be described later, and a command indicating that a series of processing has been completed is sent to _FE at _n58 .
Since this is done by setting , the _FE set at this time is reset at _n48 . n ₄₉
specifies the first digit of memory M ₁ and LI of n ₅₀
The contents of the memory specified by the instruction are stored in the accumulator.
Introduced into AAC. This accumulator ACC with n ₅₁
Transfer the contents of to output register F. On the other hand, on the CPU ₂ side, O ₁ and O ₂ set F _A and F _B , and O ₃ specifies the first digit of memory M ₂ to be accepted. The RFD instruction at _O4 is for resetting the flag flip-flop _FD , and is for restoring the _FD set by the SFD instruction at _O9 , which will be described later. _O5 indicates whether the input AK is "1". That is, since the acceptance state has been prepared at _O3 , unless the flag flip-flop F _D of CPU ₁ connected to the AK terminal of CPU ₂ is set, the process proceeds from _O5 to _O6 , and the T instruction of _{O6 is} executed. By setting the operand to step O ₅ , repeat O ₅ → O ₆ → O ₅ →…. Then, when _FD is set in _n52 on the CPU ₁ side, the AK input of CPU ₂ becomes "1", so skip O ₅ to O ₆ and proceed to O ₇ , and CPU ₁ is set based on the KTA instruction. The contents of the K input connected to the output register F of the accumulator
Transfer to ACC. Then exchange the contents of memory _M2 and accumulator ACC with the XI instruction at _O8 ,
The contents of the first digit of memory _M1 input to ACC are transferred to the first digit of memory _M2 . Then, set the flag flip-flop F _D at _O9 . On the other hand, on the CPU ₁ side, after setting _FD at _n52 , the process advances to _n53 and changes the input AK. Since the AK terminal of CPU ₁ is connected to the _FD output of CPU ₂ , repeat n ₅₃ → n ₅₄ → n ₅₃ →... until _FD becomes "1". In other words, the processing here checks whether the transfer of one digit from M ₁ to M ₂ has been completed. Transfer is performed at _O8 , and _FD is set at _O9 , so _n53 receives this, skips _n54 , and proceeds to _n55 . On the other hand, on the CPU ₂ side, after setting F _D at O ₉ , at O ₁₀
Change TAB input. TAB input is F of CPU ₁
Connected to _E output. F _E will be explained later, but M ₁ →
It is set when all M ₂ transfers are completed, so here we proceed to O ₁₁ , jump to O ₄ , and return to O _9.
Reset the _FD you set with , and change the AK input again with O ₅ . The CPU ₁ side resets _FD at _n55 , and transfers the contents of memory _M1 to the accumulator ACC with the LI instruction at _n56 . Since the specified digit address of the memory is automatically uploaded in the processing of the LI instruction in _n50 , the second digit is specified in memory _M1 in the processing of _n56 , so the contents of the second digit are
Enter ACC. The LI instruction skips _n57 when the specified digit address in memory reaches a specific value _n1 (here, one digit higher than the most significant digit of the data).
Proceed to n ₅₈ , otherwise proceed to n ₅₇ with T command
Return to n ₅₁ . Here, the contents of the second digit of memory _M1 , which has now entered ACC, are transferred to register F. Then, set F _D at _n52 . On the CDU ₂ side, as mentioned above, AK is adjusted at O ₅ , so AK = 1 due to the F _D set of n ₅₂ , skipping O ₆ and proceeding to O ₇ , and changing the memory at O ₇ and O ₈ . The second digit contents of _M1 are stored in the second digit of memory _M2 .
(Note that the specified digit address in memory _M2 is the same as the one used when processing the first digit.)
Since it was automatically uploaded by the XI instruction in _O8 , the second digit address is specified at this time). By repeating the above steps, memory
The contents of _M1 are transferred to _M2 . The last digit of the data is introduced into the accumulator ACC at _n56 on the CPU ₁ side, returns to _n51 , and is transferred to the memory of CPU _2.
After transferring this content to the last digit of _M2 , when the program goes to _n56 again, BL=V (V=n ₁ ) is satisfied, so it skips _n57 and goes to _n58 . Then, set F _E here. In F _E set, CPU ₂ side is _O10 .
When the TAB input direction is satisfied, the program proceeds to O ₁₂ and O ₁₃ , resets F _A and F _B , and returns to the initial state.
On the CPU ₁ side, after setting F _E at _n58 , the process returns to _n'39 and ends the series of processing. The F _E set at n ₅₈ is
Make sure to reset it with _n48 . Next, I will explain the process of pressing the □← key to change from M ₂ to M ₁ . At this time, proceed from n ₂₂ to n ₂₃ . _n23 is represented on the right side of FIG. 9 as specific processing _O14 to _O25 . When A≠1 and press the □← key, advance to O ₁₄ and F _E
Reset. This process has the same purpose as n ₄₈ above. F _A set at O ₁₅ is n ₄₅ on CPU ₁ side
(α=1 shot). however
When M ₂ →M ₁ , F _B is not set, so n ₄₅ → n ₄₇
→ Proceed to n ₅₉ . On the CPU ₂ side, after setting F _A at _O15 , specify the first digit of memory _M2 at _O16 ,
_O17 introduces the contents of the first digit of this designated memory _M2 into the accumulator ACC. This content is then transferred to output register F at _O18 . On the CPU ₁ side, reset F _D (described later) with n ₆₁ and n ₆₂
Proceed to. n ₆₂ is the AK input jack, and the AK input is
Connected to CPU ₂ 's flag flip-flop _FD , n ₆₂ and n ₆₃ until CPU ₂ 's _FD is set.
Repeat. In CPU ₂ , after transferring the contents of ACC to F at O ₁₈
Set _FD at O ₁₉ and proceed to O ₂₀ . Since this F _D set is received on the CPU ₁ side, it skips _n62 to _n63 and proceeds to _n64 , and uses the KTA instruction to transfer the first digit content of the second memory _M2 , which is at the K input at that time, to the accumulator ACC. . It is then exchanged with the first digit of the first memory _M1 at _n65 , essentially transferring the contents of the first digit of the second memory _M2 to the first digit of _M1 . Then proceed to _n66 and set _FD . On the CPU ₂ side, O ₂₁ is running AK.
Since the AK input of CPU ₂ is connected to the _FD output of CPU ₁ , until _FD is set by _n66 on the CPU ₁ side,
Repeat O ₂₀ →O ₂₀ →O ₂₀ →…. When F _D is set at _n66 , the process advances to _O22 . At _O22 , reset the _FD set at _O19 . Then proceed to _O23 . Now issue the LI command and put the contents of memory _M2 into the accumulator ACC. Since the designated digit address has been automatically raised at _O17 , the contents ACC of the second digit in memory _M2 are entered at _O23 . This _O23 LI instruction simultaneously checks whether the specified digit address is one digit higher than the last digit of the data, BL=V (V=n ₁ ), but since they do not match yet, O _{twenty four}
Return to O ₁₈ with the T command. and ACC with ATF command
transfer the contents of the second digit to register F;
At _O19 , F _p is set again. On the other hand, on the CPU ₁ side, after setting _FD at n ₆₆ , n ₆₇
Proceed to , and perform TAB input. The TAB input is connected to the F _E output of CPU ₂ , and the TAB input is connected to the F _E output of CPU _2.
is set at _O25 when all digits of the memory contents have been transferred, so until then the process proceeds as n ₆₇ → n ₆₈ → n ₆₁ , and after resetting _FD at n ₆₁ , AK is reset again at n ₆₂ . Perform input maneuvers. Since _FD is set at _O19 on the CPU ₂ side, _n63 is skipped and the process proceeds to _n64 , so this KTA
At the instruction, the contents in the second digit of the second memory _M2 are transferred to the accumulator ACC of the CPU ₁ via the K input.
and enters the second digit of memory _M1 at the next _n65 . After repeating the above, when the CPU ₂ side reaches _O23 after processing the final digit, it will skip _O24 and proceed to _O25 , where F _E is set, so the CPU ₁ side will also go to n. Skip steps ₆₇ to n ₆₈ and return to the cut-off state. Of course, the CPU ₂ side also returns to its initial state from O ₂₅ . As described above, by pressing the □← key when A≠1, M ₂ →M ₁ is performed. In addition _{, " M 2}
→M ₁ ” and “M ₁ →M ₂ ” may be processed in the same way as in FIG.

The [Formula] key is used to clear both CPU ₁ and CPU ₂ at the same time. In Figure 5, _n8 is used to check whether this key is pressed or not.

When the [Formula] key is pressed, proceed to n ₁₈ . Set the operand of _n18 ADI instruction to "0001". and generate a STPO instruction at n ₁₉ ,
The contents of the accumulator ACC are stored in the stack register.
Transfer to SA. This causes the SA to be ``0001''.
enters. In other words, the first bit of SA ₁ is "1"
become. Connect the SA ₁ terminal of CPU ₂ to the KF ₂ input terminal of CPU ₁ . On the CPU ₁ side, as mentioned above, when no keys are pressed, the sequence is n' ₃₉ →n ₄₁ →n ₄₃ →n ₄₄ →n ₄₅ →n ₄₆ →n' ₃₉ →..., and n ₄₃ is KF ₂ I'm playing the input game.
accordingly

When the [Formula] key is pressed and SA ₁ output is output, this jump at n ₄₃ is satisfied and n ₄₄ is skipped.
Proceed to n ₄₂ . n ₄₂ is the clearing process for CPU ₁ , where
CPU ₁ is cleared. CPU ₂ sets SA ₁ = 1 at n ₁₉ and then proceeds to n ₂ .
Clear processing for CPU ₂ . and after finishing n ₂
Proceed to n ₃ (clear processing of n ₂ clears the accumulator)
Make sure that ACC is also cleared). again with n ₃
Issue the STPO command and set SA ₁ to "0". As above

[Formula] Clear CPU ₁ and CPU ₂ by pressing the key. In addition, among the processes shown in FIG. 5, FIG. 6, FIG. 7, FIG. 8, and FIG. 9, n ₁ , n ₄ , n 5 , n ₆ , n ₇ , n _{8 ,} n ₂₀ ,
n ₂₁ , n ₃₉ , n′ ₃₉ , n ₄₁ are 15 in the processing list mentioned above.
, n ₂₂ , n ₂₄ , n ₂₈ , n ₃₁ , n ₃₄ , n ₄₅ , n ₄₇ are 9 of list, m ₁ , m ₅ , m ₇ , n ₃₅ are type 1 of list 3
, m ₄ is type 1 of list 4, m ₃ is list 6
Type 1 of n ₄₆ can be realized by using List 14. As described above, according to the present invention, the first, which can execute at least one of the four arithmetic operations,
It has a second computer section, and the two sets of computer sections are:
Each operation is individually instructed by the first and second keys, and the operation results are stored in the first and second memories, respectively, and the stored operation results are
A multicalculator configured to be displayed separately on first and second display sections, respectively, which performs at least one of the four arithmetic operations using the operation results stored in the first and second memories. a third key for instructing a calculation; a calculation execution means for executing the commanded calculation in response to the operation of the third key; a third memory for storing the result of the executed calculation; and the third memory. a transfer instruction key for instructing transfer of the calculation result stored in the third memory to the first memory or the second memory; and a transfer instruction key for instructing transfer of the calculation result stored in the third memory to the third memory; Since the computer has a display control means for displaying on the first display section or the second display section, by operating the third key, the two calculation results separately held by the first and second computer sections can be used. Therefore, when performing the four arithmetic operations, the operator can save the trouble of transferring data between the first computer section and the second computer section, and There is no need to re-input the calculation results of the second computer unit, and therefore the calculation results of the four arithmetic operations can be obtained quickly and accurately.

[Brief explanation of the drawing]

FIG. 1 is a perspective view, FIGS. 2, 3, and 4 are block diagrams, and FIGS. 5 to 9 are operational state diagrams. Code CA: Cabinet, K ₁ : First key group,
DSP ₁ : first display section, K ₂ : second key group,
DSP ₂ : Second display section, K ₀ : Key group for instructing mutual transfer or mutual calculation between the left and right computer sections,
CPU ₁ : 1st microprocessor, CPU ₂ : 2nd microprocessor
microprocessor, CG: oscillator.

Claims (1)

[Claims] 1. It has first and second computer units capable of executing at least one of the four arithmetic operations, and the second set of computer units each independently performs an operation using the first and second keys. The multifunction computer is configured such that the calculation results are stored in the first and second memories, respectively, and the stored calculation results are displayed separately on the first and second display sections, respectively. a third key for instructing to perform at least one of the four arithmetic operations using the arithmetic results stored in the first and second memories; a third memory that stores the results of the executed calculations; and an instruction to transfer the calculation results stored in the third memory to the first memory or the second memory. A transfer instruction key; and display control means for performing the transfer instructed by the transfer instruction key and displaying the calculation result stored in the third memory on the first display section or the second display section. A multi-calculator with special features.