JPS6118873B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a gallium arsenide field effect transistor (hereinafter referred to as
The present invention relates to a method for metallizing the side surfaces of devices (called GaAsFETs).

Conventionally, for example, in high-power GaAsFETs for ultra-high frequencies, it is necessary to minimize the grounding inductance in order to obtain a large power gain, especially in the C band (4.2 to 8.2 GHz) and above. Instead, a method has been used in which metal is bonded from the source side electrode to the side surface of the element in the element manufacturing process, and this metal is grounded to a stem or the like when mounted in the assembly process. And, as a method to implement this side metalization,
After dividing a GaAsFET wafer into each element piece, the individual element pieces are rearranged on a metal plate, for example, and the required metal is coated on the sides of the element piece by vapor deposition, sputtering, plating, etc. It was getting worse. According to this method, it takes a huge number of man-hours to handle each minute element piece, and also
Due to the brittle nature of GaAs, chipping and cracking of the device occurs, leading to a significant drop in yield, which inevitably increases the manufacturing cost of the device at the time the side metallization is completed.

An object of the present invention is to eliminate all of the above-mentioned drawbacks by performing metallization on the wafer without changing the shape of the wafer, and dividing the wafer into element pieces after completing the metallization on the side.

Next, an outline of the present invention will be explained using a GaAsFET as an example. First, the surface of the wafer on which the required electrodes on the source, drain, and gate sides of the GaAsFET have been completed, that is, only the source side electrode is drawn out to the scribe line, is completely covered with photoresist. Gold is applied to a certain thickness using the plating method. Then, scribe along the scribe line using a dicing saw up to the border of gold on the back side. Subsequently, the wafer is placed in a gold plating solution and gold plating is applied to the side surfaces of each scribed element, at least on the side surfaces of the elements where the electrodes led out from the source are located. The side surface metallization is thus completed, and then pelletization is performed using a dicing saw.

According to the present invention, the number of man-hours in the side metallization process is reduced to one-tenth of the conventional process, and the yield is almost reduced.
100%, reducing device manufacturing costs to one-third of conventional costs.

Next, the present invention will be explained based on preferred embodiments thereof with reference to the drawings.

FIG. 1 shows a state in which GaAsFET wafer manufacturing has been completed by a conventionally known method. That is, an epitaxial layer (epitaxial layer) 2 doped with, for example, sulfur is placed on a GaAs substrate 1, a gate electrode 3 made of, for example, aluminum is placed on this epitaxial layer 2, and then a layer is formed on the GaAs substrate 1 from above this epitaxial layer 2. In the exposed state, a source electrode 4 and a drain electrode 5 made of, for example, AuGe-Pt-Ti-Pt-Au are arranged, and a silicon oxide film 6, for example, formed by vapor phase growth is arranged to protect the wafer surface. Furthermore, in FIG. 1, 4' is an oxide film 6 to connect the source electrode to the metal of the side surface metallization, which will be described later.
The opening portion 7 shows a hole opening in the oxide film 6 for bonding a lead wire to the drain electrode 5, and the reference numeral 8 shows a scribing groove exposing the GaAs surface for dividing into each element.

Next, as shown in FIG. 2, the entire surface of the element is covered with photoresist 9, and gold 10 is deposited to a thickness of about 50 .mu.m on the entire rear surface of the element by electrolytic plating.

Next, as shown in FIG. 3, after the gold plating shown in FIG. 2 is completed, the photoresist 9 is removed, and a cut groove 11 is made from the scribe groove 8 with the same width as the groove. This cut groove 11 can be easily formed using a dicing saw, for example. What is important in this process is to insert this groove 11 into the GaAs substrate 1,
The gold layer 10 formed on the back surface should maintain approximately the same thickness. Thus the side surface 12 of each element
is exposed. Next, each element is connected by the support of the gold layer 10, and the wafer is placed in a gold plating solution such as Neutronex 309 (trade name) while maintaining its shape, and the gold layer 10 is used as a conductive path for plating on the side surface of each element. Gold plating is applied to a thickness of approximately 2μ. It is important to perform this gold plating on the side surface of the device while it is connected to the source side electrode 4, and in this embodiment, the gold plating layer 13 in FIG. 3 is the gold plating layer. In this example, in order to simplify the process, gold plating was performed while the wafer surface was exposed without being masked with a special photoresist or the like. Therefore, the gold plating layer 7' is also formed on the exposed portion of the drain side electrode 5, but this does not pose any particular problem. In this way, as shown in FIG. 3, a desired side metallization, that is, a gold plating layer 13 is formed on the side surface of the device.

FIG. 4 shows the completed device of the invention separated from the state of FIG.

According to the above method, as mentioned above, the yield of the side metallization process is greatly improved and the number of man-hours is greatly reduced.Furthermore, the power gain of the GaAsFET device to which the present invention is applied, for example, in the C band, can be set to the desired value with very good reproducibility. It was confirmed that

As explained above, the present invention achieves the desired effect by metallizing the side surfaces of devices in the wafer state, and the present invention is particularly applicable to GaAsFETs.
It is possible to implement the present invention in any semiconductor device as long as it satisfies the purpose of the present invention, and the specific shape, material, etc. thereof are not limited to the present embodiment, and can be implemented in any semiconductor device that fulfills the purpose of the present invention. It doesn't matter what type it is.

[Brief explanation of the drawing]

1 to 3 are cross-sectional views of a wafer for explaining an embodiment of the present invention in the order of steps, and FIG. 4 is a cross-sectional view of a device. 1...GaAs substrate, 2...GaAs epi layer, 3...
Gate electrode, 4, 4'... Source electrode, 5, 7,
7'...Drain electrode, 6...Silicon oxide film,
8...Scribe groove, 9...Photoresist, 10
...Gold plating layer, 11...Scribe groove, 1
2...Element side surface, 13...Element side surface metallized gold plating layer.

Claims (1)

[Claims] 1. A step of depositing metal on the back side of a semiconductor wafer on which a plurality of semiconductor elements have been formed, and a step of forming grooves reaching from the wafer surface to the back metal layer at the boundaries of each of the elements to expose the side surfaces of each element. and a step of depositing a desired metal on the side surface of each element in this state.