JPS6119055B2 - - Google Patents
Info
- Publication number
- JPS6119055B2 JPS6119055B2 JP8003280A JP8003280A JPS6119055B2 JP S6119055 B2 JPS6119055 B2 JP S6119055B2 JP 8003280 A JP8003280 A JP 8003280A JP 8003280 A JP8003280 A JP 8003280A JP S6119055 B2 JPS6119055 B2 JP S6119055B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- processors
- memory
- processor
- processor bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Information Transfer Systems (AREA)
Description
【発明の詳細な説明】
本発明は、複数のプロセツサを設けたマルチプ
ロセツサシステムに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiprocessor system provided with a plurality of processors.
従来、マルチプロセツサシステムでのプロセツ
サ間のデータの授受には共通メモリ方式が取られ
ていた。この方式ではプロセツサ間でメモリを使
用するタイミングがぶつからないように、待ち合
わせにより、タイミングを調整して、複数のプロ
セツサが１つの共通メモリを使用していた。 Conventionally, a common memory method has been used for exchanging data between processors in a multiprocessor system. In this method, a plurality of processors use one common memory by adjusting the timing by waiting so that the timing of memory usage does not conflict between the processors.
しかし、この方式ではプロセツサ間でのデータ
の転送が頻繁になると、待ち合わせ時間が大きく
なり、プロセツサの効率が下がることになるとい
う欠点があつた。 However, this method has the drawback that if data transfer between processors becomes frequent, the waiting time increases and the efficiency of the processors decreases.
本発明は、プロセツサ間のデータの授受のため
に、データ転送用メモリをそれぞれに含む複数の
メモリ制御回路を設け、また各プロセツサ毎にプ
ロセツサと前記複数のメモリ制御回路を結合する
プロセツサバスを設けることにより、複数のプロ
セツサそれぞれが別々のメモリ制御回路のデータ
転送用メモリを同時にアクセスでき、各プロセツ
サがデータ転送用メモリを使用するための待ち時
間を無くし、マルチプロセツサシステムの効率を
充分に発揮し得るマルチプロセツサシステムを提
供するものである。 The present invention provides a plurality of memory control circuits each including a data transfer memory for exchanging data between processors, and also provides a processor bus for coupling the processor and the plurality of memory control circuits for each processor. This allows multiple processors to simultaneously access the data transfer memory of separate memory control circuits, eliminates the waiting time for each processor to use the data transfer memory, and fully utilizes the efficiency of the multiprocessor system. This provides a multiprocessor system that can
本発明によれば、複数のプロセツサを設けたマ
ルチプロセツサシステムにおいて、前記プロセツ
サの各々に対応して結合された複数のプロセツサ
バスと、複数のメモリ制御回路とを有し、このメ
モリ制御回路各々はデータ転送用メモリと、前記
複数のプロセツサバスから１つの指定プロセツサ
バスを選択する信号を出力する指定手段と、前記
指定プロセツサバスのみを前記データ転送用メモ
リにアクセス可能とする接続手段と、前記プロセ
ツサバスの所定の第１の信号により前記指定手段
の出力信号を変換する指定プロセツサ変換手段
と、前記プロセツサバスが所定の第２の信号によ
り前記指定手段の出力信号を読出す指定信号読出
し手段とを含むことを特徴とするマルチプロセツ
サシステムが得られる。 According to the present invention, a multiprocessor system including a plurality of processors includes a plurality of processor buses coupled to each of the processors and a plurality of memory control circuits, each of which has a plurality of memory control circuits. a data transfer memory; a designation means for outputting a signal for selecting one designated processor bus from the plurality of processor buses; a connection means for allowing only the designated processor bus to access the data transfer memory; The processor bus is characterized in that it includes designated processor converting means for converting the output signal of the designating means using a first signal, and designated signal reading means for reading out the output signal of the designating means using a predetermined second signal. A multiprocessor system is obtained.
次に本発明の実施例の図面を参照して説明す
る。第１図は本発明の一実施例で、２つのプロセ
ツサ１，２を有するマルチプロセツサシステムの
場合を示す。プロセツサ１はプロセツサバス３１
により個別メモリ４１、入出力装置５１、および
複数のメモリ制御回路６と結合され、同じように
プロセツサ２もプロセツサバス３２により個別メ
モリ４２，入出力装置５２，および複数のメモリ
制御回路６と結合されている。 Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows one embodiment of the present invention, which is a multiprocessor system having two processors 1 and 2. In FIG. Processor 1 is processor bus 31
The processor 2 is connected to the individual memory 41, the input/output device 51, and the plurality of memory control circuits 6 by the processor bus 32. There is.
第２図にメモリ制御回路６の１つを詳細に示
す。ここでアドレスバスＡ1.1〜Ａn+k FIG. 2 shows one of the memory control circuits 6 in detail. Here, the address bus A 1 . 1 ~ A n+k
Claims (1)
システムにおいて、前記プロセツサの各々に対応
して結合された複数のプロセツサバスと、複数の
メモリ制御回路とを有し、このメモリ制御回路
各々はデータ転送用メモリと、前記複数のプロセ
ツサバスから１つの指定プロセツサバスを選択す
る信号を出力する指定手段と、前記指定プロセツ
サバスのみを前記データ転送用メモリにアクセス
可能とする接続手段と、前記指定プロセツサバス
の所定の第１の信号により前記指定手段の出力信
号を変換する指定プロセツサバス変換手段と、前
記プロセツサバスが所定の第２の信号により前記
指定手段の出力信号を読出す指定信号読出し手段
とを含むことを特徴とするマルチプロセツサシス
テム。1. A multiprocessor system having a plurality of processors has a plurality of processor buses connected to each of the processors and a plurality of memory control circuits, each of which has a memory for data transfer and a plurality of memory control circuits. , specifying means for outputting a signal for selecting one designated processor bus from the plurality of processor buses; connecting means for allowing only the designated processor bus to access the data transfer memory; and a predetermined first signal of the designated processor bus. A multiprocessor characterized in that the processor bus includes designated processor bus conversion means for converting the output signal of the designation means by a predetermined second signal, and designated signal readout means for reading out the output signal of the designation means using a predetermined second signal. system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8003280A JPS576954A (en) | 1980-06-13 | 1980-06-13 | Multiprocessor system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8003280A JPS576954A (en) | 1980-06-13 | 1980-06-13 | Multiprocessor system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS576954A JPS576954A (en) | 1982-01-13 |
| JPS6119055B2 true JPS6119055B2 (en) | 1986-05-15 |
Family
ID=13706918
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8003280A Granted JPS576954A (en) | 1980-06-13 | 1980-06-13 | Multiprocessor system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS576954A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6149262A (en) * | 1984-08-16 | 1986-03-11 | Oki Electric Ind Co Ltd | Page memory information transfer system |
| JPH0164752U (en) * | 1987-10-21 | 1989-04-25 |
-
1980
- 1980-06-13 JP JP8003280A patent/JPS576954A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS576954A (en) | 1982-01-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| ATE73241T1 (en) | DATA PROCESSING SYSTEM BUS WITH FAULT CYCLING OPERATION. | |
| JPS6119055B2 (en) | ||
| JPS5930292B2 (en) | Souchikanketsugohoshiki | |
| JPS6136845A (en) | single chip microcomputer | |
| JPH0227696B2 (en) | JOHOSHORISOCHI | |
| JPS6363940B2 (en) | ||
| JPS6120172A (en) | Multi-microprocessor system | |
| JPS5953564B2 (en) | data processing equipment | |
| SU962905A1 (en) | Device for interfacing electronic computers | |
| JPS5953565B2 (en) | Direct memory access control device | |
| JPH069036B2 (en) | Input/Output Control Unit | |
| JPS5844426Y2 (en) | Inter-processor information transfer device | |
| SU758118A1 (en) | DATA COLLECTION AND PROCESSING SYSTEM 1 | |
| JPH07175768A (en) | Dual CPU system | |
| SU1566361A1 (en) | Device for data exchange between processors | |
| JP2822414B2 (en) | Dual port memory | |
| JPS6126104B2 (en) | ||
| JPS5999522A (en) | Input and output control system | |
| JPS60247767A (en) | Simultaneous input and output system for reading-out and writing-in operation of shared memory | |
| JPH04308955A (en) | Multiprocessor device | |
| WO1989003565A1 (en) | Selective receiver for each processor in a multiple processor system | |
| JPS5836380B2 (en) | Direct memory access method in multiprocessor systems | |
| JPS614237U (en) | video tape recorder | |
| JPS60140145U (en) | Image memory device with multiple inputs and exits | |
| JPS598184A (en) | Memory |