JPS6119064B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a program parallel processing method for an information processing apparatus that uses a sub-central processing unit to process programs in parallel and shortens execution time.

2. Description of the Related Art In general, an information processing device including a central processing unit and a memory device stores a program for executing processing in the memory device in advance, reads and analyzes the program, and executes predetermined data processing. At this time, there is a single central processing unit, and the stored programs must be processed sequentially from the beginning. Therefore, rather than processing data together, it is possible to simply have the program process it in parallel, and then process it again on a single device after the processing is completed, which would be faster in terms of time. There was no equipment that could process it.

SUMMARY OF THE INVENTION An object of the present invention is to provide a program parallel processing method for an information processing apparatus that improves the above-mentioned drawbacks and reduces execution time by processing programs in parallel by providing a sub-central processing unit.

Embodiments of the present invention shown in the drawings will be described below. FIG. 1 is a block configuration diagram of a first embodiment of the present invention, in which the information processing device consisting of a main central processing unit MCC and a main memory device MM is a conventional general device, and is surrounded by a chain line. This section is a device added according to the present invention. SCC1, SCC2,...SCCn
is n sub-central processing units, SCT is a sub-central processing unit control section, ADA is an address calculation section, CT is a control section, and MCN is a memory contention circuit. Before starting information processing, the program is analyzed, programs that can be divided and processed independently are found, and the programs are divided into parallel processing units. Next, set the loading address, program identification name, and parallel processing flag for that program.
They are loaded into the main memory device MM. This operation is mainly performed by the control unit CT, which also passes the location of the common data to the address calculation unit ADA. After the main central processing unit MCC starts operating according to the program in the main memory unit MM, when it is decided to execute a program capable of parallel processing, the main central processing unit MCC executes the parallel processing program for the control unit CT. We will notify you that we will do so. The control unit CT passes the parallel processing program identification name to the address calculation unit ADA in order to start up the sub-central processing unit SCC. The address calculation unit ADA associates the program identification name with the loading address in the main memory device MM, and reports the address to the sub-central processing unit control unit SCT. The sub-central processing unit control unit SCT uses hardware to find an empty sub-central processing unit SCC, passes the loading address to it, and starts the sub-central processing unit. reading,
Start the next action. The memory contention circuit MCN performs processing according to a predetermined priority order when a plurality of main central processing units MCC and sub central processing units SCC operate and access the main memory device MM at the same time. In this way, the sub-central processor SCC
When the main central processing unit (MCC) is running, when the scheduled processing of the main central processing unit (MCC) is completed, it will wait for the processing of the sub-central processing unit. Priority is given to the processing of Normally, the processing of multiple sub-central processing units SCC is completed simultaneously or sequentially, and the completion is reported to the main central processing unit MCC, so the main central processing unit maintains synchronization and starts the next processing when necessary. The sub-central processing unit operates again.

It is convenient for the operator if a display device such as a lamp is provided in the main memory device MM, and the display device is turned on when a parallel processing request is made to the sub-central processing unit SCC and the relevant program is read. It is.

Next, FIG. 2 shows a second embodiment of the present invention in which, in addition to the main memory device MM shown in FIG. 1, a separate sub-memory device SM is also provided for the sub-central processing unit SCC. Set up the circuit SMCN and make the necessary connections. The sub memory device SM stores programs divided into parallel processing units. At this time, when the sub-central processing unit operates, the main memory device
Secondary memory device SM without accessing MM each time
All you need to do is access. It is also advantageous when processing data is stored and reprocessed later. Note that the data shared by the central processing unit MCC, sub-central processing unit SCC, and sub-central processing unit SCC is stored in the main memory device, so the sub-central processing unit can refer to it via the main memory contention circuit MCN whenever necessary. do.

In this way, according to the present invention, since the program that can be executed by parallel processing is stored in the memory device in advance, the operation of the sub-central processing unit can be performed in parallel with the main central processing unit or with other sub-central processing units. As a result, program execution time is shortened and information processing is performed efficiently.

[Brief explanation of the drawing]

FIGS. 1 and 2 show block diagrams of first and second embodiments of the present invention. MCC...Main central processing unit, MM...Main memory device, SCC1, SCC2,...SCCn...Sub central processing unit, CT...Control unit, MCN...Main memory contention circuit, ADA...Address calculation unit, SCT ...Sub central processing unit control unit, SM...Sub memory device, SMCN
...Sub-memory contention circuit.

Claims (1)

[Claims] 1. In a program processing method for an information processing device in which a main central processing unit sequentially executes programs stored in advance in a memory device, programs that can be divided into parallel processing units are divided in advance. A control unit, a plurality of sub-central processing units, and a memory contention circuit are provided between the memory device storing the parallel processing information and the main central processing unit, and when the main central processing unit issues parallel processing information,
A program parallel processing method for an information processing device, characterized in that under the control of a control unit and a memory contention unit, one of the sub-central processing units that is in an empty state executes a divided program. 2. Program parallel processing according to claim 1, characterized in that the memory device is provided with a display indicating that parallel processing is in progress when a predetermined program is read from the memory device based on parallel processing request information. method. 3. The program parallel processing system according to claim 1, further comprising a sub-memory device used by the sub-central processing unit.