JPS6125189B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bus control device for an information processing device that can appropriately switch and use data buses depending on the number of vector register elements used.

2. Description of the Related Art There is a processing device having the configuration shown in FIG. 1 as a device that provides a vector register at the input of an arithmetic unit for high-speed data processing and transfers data between it and a main memory. Each memory module MDL that constitutes the main memory MEM has multiple banks BNK.
The data in bank BNK is transferred to vector register VR, and the data is processed by the arithmetic unit.
VPU does the processing. Usually, a plurality of arithmetic units VPU (eight in Fig. 1) are provided, and a plurality of vector registers VR ₀ to VR _o-1 are each numbered from 0 to 16 in the drawing.
It is composed of elements ELM indicated by the numbers ``...'', and 8 element data can be input in parallel to 8 arithmetic units from each vector register, allowing high-speed processing. Data in the main memory is associated with the data bus for each module MDL by address, and data on the vector register is associated with the data bus on the vector register side by element number. Therefore, a data alignment circuit DCC is required during data transfer.

In principle, the data alignment circuit DCC is connected to each module.
The interconnection between the MDL compatible bus and the bus corresponding to the element number of the vector register is switched and connected using a predetermined control signal. Note that the data alignment circuit DCC can also be considered as an internal configuration of the memory access control device MAC. The vector register VR is a set of flip-flops, and data is transferred at high speed between it and the arithmetic unit VPU, but in comparison, the main memory is a large capacity memory element, and the data between the main memory and the vector register is Transfer cannot be made at high speed. For this reason, a large number of banks BNK are set up to perform "interleave" operation, but there are physical constraints such as the number of cables, and there are limits to access time and cycle time, and the more data is transferred in and out, the more , the degree to which performance can be suppressed is large.

The purpose of the present invention is to improve the above-mentioned drawbacks by inserting a bus conversion circuit between the main memory and the vector register,
To provide a bus control device for an information processing device which enables data transfer between a main memory and a vector register to an extent commensurate with the calculation speed of an arithmetic unit, and which can cope with varying numbers of vector register elements.

Embodiments of the present invention shown in the drawings will be described below. Figure 2 is a diagram of the principle of the present invention, and shows the bus conversion circuit BSC.
The figure shows an example in which the number of elements that can be accessed in parallel in the vector register is reduced to half that of FIG. In other words, since it takes time to transfer between the main memory MEM and the vector register VR, the parallelism of the vector register VR and the arithmetic unit VPU (first
In the figure, increasing the degree of parallelism (8) does not have much effect on improving overall performance. On the contrary, if the degree of parallelism is halved, the amount of hardware and costs will be halved, but the overall performance will not drop that much. In this way, there are cases where you want to achieve even a little higher performance by spending a lot of hardware, and cases where you want to reduce the price even if you sacrifice some performance.It is preferable that the same bus conversion circuit BSC can be used in both cases.

In Figure 2, there are eight buses D- on the main memory side.
There are 1N ₀₀₀ to D-IN ₇₀₀ , and eight buses D-OUT ₀₀₀ to D-OUT ₇₀₀ on the vector register side, with a bus conversion circuit BSC located between them. The thick white arrows indicate the gate control line group of the bus conversion circuit BSC. In addition, buffer registers shown in double frames are connected to D-OUT _{400 to 700} of the vector register side bus, and the first four elements of the eight elements transferred at once from the main memory side are directly transferred to the vector register once. However, the latter four elements are once held in the buffer register and then written as the next four elements in the same vector register in the next cycle. Therefore, vector register write cycles can be generated at twice the speed of operation cycles on the main memory side. FIG. 3 is a diagram showing an example of a bus conversion circuit. In Figure 3, G00, G01...G7
2 is the aforementioned gate control signal, and for each of the terminals D-OUT _{000 to 700} on the cell register side,
One of the memory side data buses D-IN _{000 to 700} is selected. That is, for the bus D-OUT on the vector register side, D-OUT ₀₀₀ : G00, G01, G02 D-OUT ₁₀₀ : G10, G11, G12 D-OUT ₂₀₀ : G20, G21, G22 : : D-OUT ₇₀₀ : G70 , G71, G72, and as a result, the bus on the memory side and the bus on the vector register side are connected in the desired correspondence. The configuration shown in FIG. 3 can be used as is as a data alignment circuit DCC in the case of a conventional vector register in units of 8 elements.

Furthermore, the gate control signal generation circuit of the bus conversion circuit BSC can be modified to switch between a vector register in units of 8 elements and a case in units of 4 elements. In FIG. 4, generation of the gate control signal is switched in the case of 8 element units in 1 access mode with 1ASM signal and in the case of 4 element units in 2 access mode with 2ASM signal.

In this way, according to the present invention, the same bus switching circuit BSC can be used regardless of whether the number of vector register elements is increased or decreased, and the vector register configuration is improved to match main memory access performance. It is effective as an information processing device.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an information processing device having only a data alignment circuit, FIG. 2 is a principle diagram showing the configuration of the present invention, and FIG. 3 is one of the bus conversion circuits in FIG.
A diagram showing an example, FIG. 4, is a diagram showing a gate control signal generation circuit of a bus conversion circuit. MEM...Main memory, MDL...Memory module, BNK...Bank, MAC...Memory access control device, DCC...Data alignment circuit, VR ₀ ~
VR _o-1 ...Vector register, VPU...Vector arithmetic unit, BSC...Bus conversion circuit.

Claims (1)

[Claims] 1 A main memory consisting of a plurality of modules each consisting of a plurality of banks, and a plurality of vector registers consisting of a plurality of elements, with a data bus corresponding to the address of the main memory and a data bus corresponding to the elements of the vector register. By inserting a bus conversion circuit between the
(integers above), buffers are provided for N-M data buses on the vector register side, and data transfer is performed n times on the vector register side for one data transfer on the main memory side. A bus control device for an information processing device.