JPS6126157B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile semiconductor integrated circuit having a gate insulating layer having a storage medium portion for storing charge under a gate electrode.

As shown in FIG. 1, the method conventionally used is that the write high voltage 9 applied when writing certain memory contents is set to select either the read mode or the write mode. The voltage is applied to the drain of the enhancement type MOS transistor 2. During a write operation, the write high voltage 9 is an enhancement type that is in a conductive state.
It communicates with Y=decoder 4 through MOS transistor 2. In the read mode, this enhancement type MOS transistor 2 is in a cut-off state,
High voltage 9 for writing is not input to Y=decoder 4. The source is grounded through the sense amplifier 5. Recently, as gates have become smaller, arsenic has been used as the impurity added to the sources and drains of MOS transistors. Since arsenic has a smaller diffusion coefficient than phosphorus, the impurity concentration gradient between the junctions, that is, between the arsenic-containing region, the substrate, and the channel stopper becomes large, which causes a phenomenon in which the source and drain breakdown voltages decrease. was. Therefore, such MOS
It is becoming practically difficult to apply a large write voltage to a cell via a transistor.

In this way, in a semiconductor memory integrated circuit that includes a nonvolatile semiconductor element that has a gate insulating layer that has a storage medium section for accumulating charges under the gate electrode, the high voltage for writing is an enhancement type.
When applied to the drain of a MOS transistor, it is easily destroyed due to low BV _DS . Furthermore, if the breakdown voltage of the junction made by the drain and channel stopper is lower than the high voltage applied, there is a possibility of destruction. Therefore, if the depletion type MOS transistor 8 is used as a resistance element as shown in FIG. 2, as shown in FIG. 3, due to the equivalent resistance R, the current flowing due to low BV _DS or low junction breakdown voltage is This will make it more resistant to destruction. In this way, it is possible to provide a semiconductor memory device that maintains a high degree of integration and has a high voltage by just using one depletion type MOS transistor 8 as a resistive element.

In particular, the present invention provides a semiconductor substrate, a source and drain region having a conductivity type opposite to that of the semiconductor substrate, a channel region formed between the source and drain regions, and a storage medium portion for storing charge under the gate electrode. When writing a predetermined memory state in a non-volatile semiconductor integrated circuit having a gate insulating layer with The feature is that it is applied to the drain terminal. As a result, even if the enhancement type MOS transistor has a low BV _DS or a low junction breakdown voltage, the current flowing due to the resistance of the depletion type MOS transistor is limited, making it resistant to breakdown.

Next, in order to better understand the features of the present invention, a more detailed explanation will be given using the drawings.

FIG. 1 shows a case in which a conventional high voltage for writing is directly applied to the drain of an enhancement type MOS transistor 2. In FIG. In Figure 2, the high voltage is the depletion type MOS transistor 8.
The figure shows a case in which the voltage is applied to the drain of the enhancement type MOS transistor 2 through the MOS transistor 2, which is an embodiment of the present invention. FIG. 3 shows that when the depletion type MOS transistor is used as a resistor R, the current flowing through the enhancement type MOS transistor is limited.

During writing, the writing high voltage 9 is an enhancement type MOS that is turned on by signal 1.
Y=input to decoder 4 through transistor 2. The selected selection line is then applied to the drain of the storage element 3. When reading out the state, the enhancement type MOS transistor 2 is in a cut-off state and the write voltage 9 is separated. The memory element is selected by the X=decoder 6 and Y=decoder 4, and the "0" or "1" state is determined through the sense amplifier 5.Here, in the write state, the write high voltage 9 is set to the enhancement type. If the junction breakdown voltage is higher than the junction breakdown voltage of the MOS transistor 2, the MOS transistor 2 may be destroyed.

Therefore, a depletion type MOS transistor 8 is added as a resistance element before the enhancement type MOS transistor 2. FIG. 2 shows this state. As shown in FIG. 3, this resistor element has a low BV _DS and a low junction breakdown voltage, so that excessive current is limited to point a, thereby preventing destruction of the enhancement type MOS transistor 2.

Further, although the above embodiment is limited to non-volatile semiconductor integrated circuits, it can be used in any circuit as long as a high voltage is applied to the drain of the enhancement type MOS transistor used in the circuit. . According to the invention, phosphorus is added as impurities in the source and drain, and the gate oxide film thickness is 500 Å.
The BV _DS of a MOS transistor is about 20 (v), but when arsenic is added to form the source and drain, the BV DS drops to about 15 (v). When the voltage between the drain and substrate of this transistor reaches BV _DS , the transistor is destroyed. However, if a load is attached to the drain side of this enhancement type MOS transistor, it will not be destroyed even if the pulse peak value reaches BV _DS , and as the resistance of the load increases, the pulse peak value until it reaches breakdown will decrease. It will increase. Even with a resistance equivalent to 1KΩ, an increase of 4 to 5 (V) can be seen, and depending on the resistance value, the withstand voltage required for a nonvolatile semiconductor element can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventionally used circuit format, and FIG. 2 is a circuit diagram showing an improvement measure for an embodiment of the present invention in which a depletion type MOS transistor is inserted to increase the withstand voltage. FIG. 3 is a characteristic diagram showing that the current flowing through the enhancement type MOS transistor is limited by the depletion type MOS transistor. In the figure, 1...signal, 2...enhancement type MOS transistor, 3...nonvolatile element, 4...Y=decoder, 5...sense amplifier, 6...X=decoder, 7...external power supply, 8...
...depression type MOS transistor, 9...
...High voltage for writing, 10...Load line, 11...
Current waveform.

Claims (1)

[Claims] 1 In a storage device in which a voltage applied during writing is higher than a voltage applied during reading, a depletion-type first transistor whose drain and gate are connected to a write voltage terminal, and one end connected to the source of the first transistor and means for selectively connecting the other end of the second transistor to the storage element, the second transistor being rendered conductive during writing. A semiconductor memory device characterized by: