JPS6127787B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to a signal selection circuit for selecting one signal from a plurality of signals, and particularly to a channel control device that controls a plurality of input/output channel devices having different transfer speeds. The present invention relates to a suitable signal selection circuit, a so-called priority circuit.

Prior Art Within a limited total transfer rate, multiple input/output channel devices (hereinafter referred to as
Conventionally, in channel control devices that control channels (referred to as "channels"), a system has been used in which a fixed priority circuit is used as the priority circuit to guarantee service at time intervals depending on the transfer rate of each channel.

However, the above method has a problem in that the transfer rate of each channel is fixed. One way to solve this problem is to use the physical channel number inside the channel, which has traditionally been used.
When a conversion circuit that performs conversion with a logical channel number viewed from the outside is also used, problems arise in that the amount of hardware increases and confusion occurs in system settings and maintenance.

FIG. 1 is a block diagram showing an outline of a priority circuit in a channel control device to which the present invention is preferably applied.

In the figure, a channel control device 102 controls a plurality of channels 101 _p to 101 _o in a time-sharing manner. For example, access requests from each channel to the data buffer 104 are prioritized for each access cycle of the data buffer 104. One of the channels is selected in the data buffer circuit 103, and the channel is connected to the data buffer 1.
04 access rights.

In the channel control device controlled in this way, if the overall data transfer rate of the data buffer 104 is T (MB/S, megabyte/second), then, for example, the priority circuit 103 has the characteristic of equally serving n channels. If so, the data transfer rate of each channel _101p to _101o is T/n (MB/S).

By the way, in reality, (1) the data transfer speed differs depending on the channel, and (2) there are cases where the total data transfer speed does not reach n (number of channels) times the data transfer speed of the fastest channel. In such a case, it is necessary to perform control to perform maximum data transmission within the overall data transmission rate.

For example, in a channel control device that controls 8 channels, the total data transfer rate is 20
(MB/C), and the data transfer speed of the connected channel is 2 (MB/S) and 3 (MB/S).
In this case, the combination of the above two types of channels (hereinafter referred to as "channel configuration") is required to maximize the data transfer capability of this channel control device.
) is shown in Figure 2.

Therefore, a priority circuit for realizing the channel configuration as shown in FIG. 2 will be explained below. FIG. 3 shows an example of this. In the figure, 202 is a counter for selecting a specific channel for each access cycle of the data buffer, 203 is a counter update circuit for updating the value of the counter 202, and 201 is a counter for selecting a specific channel for each access cycle of the data buffer. This is a selection circuit that selects one signal from eight access request signals (input signals) from each channel according to the value of the counter 202, encodes the value, and outputs three output signals. .

A control signal for identifying the channel configuration is input to the counter update circuit 203 from hardware (not shown) that stores the system configuration. As shown in the figure, the value of the counter 202 is updated.

The counter 202 is operated as shown in FIG.
When a corresponding channel is selected based on the value of the lower three bits, the data transfer rate assigned to each channel is as shown in FIG.

By controlling as described above, it becomes possible to control the required number of channels, but if left as is, there is a problem that the channel number is fixed.

However, when changing the system configuration, a channel with a higher data transfer rate may be connected below a channel with a lower data transfer rate, and in such cases, it is desirable to be able to deal with this without changing the channel connection. .

OBJECTS OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the priority circuit in a conventional channel control device, and to provide a channel control device suitable for controlling a plurality of channels with different transfer speeds. It is an object of the present invention to provide a priority circuit in which the combination of numbers of devices can be easily changed and channel numbers assigned to those channels can be easily set.

General Description of the Invention The above object of the present invention is to provide a signal selection circuit that selects one signal from among a plurality of input signals, an input signal identification information registration table consisting of a plurality of entries in which identification information of input signals is registered; instruction means for instructing one entry from among the plurality of entries in the identification information registration table; updating means for updating the instruction value of the instruction means with reference to information registered in the identification information registration table; and the instruction. By means of a signal selection circuit, comprising means for selecting one signal from a plurality of input signals based on input signal identification information in the identification information registration table read out by an instruction value of the means. achieved.

Embodiments of the invention and their effects Embodiments of the invention will be described below with reference to the drawings.
Based on the matters shown in Figure 5.

FIG. 6 is a block diagram of a priority circuit showing one embodiment of the present invention. As is clear from the figure, the priority circuit of this embodiment includes a channel number registration table (hereinafter simply referred to as "registration table") 301 between the counter 202 shown in FIG. 3 and the selection circuit 201. It is something that

The registration table 301 is located between the counter 202 and the selection circuit 201 as described above,
The value of the lower three bits of the counter 202 is selected. It plays the role of associating channel numbers with each other. That is, the value of the lower three bits of the counter 202 now becomes the read address of the registration table 301. That is, the counter 202 plays the role of indicating one entry in the registration tape 301.

The registration table 301 consists of eight entries, and one entry stores 5-bit input signal identification information. The meaning of each bit is as shown in FIG.

Each piece of information in the registration table 301 is service/
Support Processor (hereinafter referred to as "SVP")
It is stored in a floppy diskette (hereinafter referred to as "FD") within the floppy disk, and is loaded at the same time as the initial micro program load of the channel control device. Also, the information in the above FD is
When installing the system, it is created in the FD using the support functions of the SVP shown below.

Hereinafter, the method for creating the registration table 301 will be explained in detail based on FIG.

First, channels with a high data transfer rate (in this case, 3 (MB/S)) are selected from among the ON-LINE specified channels, and are registered in the registration table in order of channel number.At this time, V =1 and H=1.

When the registration of channel 3 (MB/S) is completed, next select channel 2 (MB/S) from among the channels that are also designated ON-LINE.
The information is sequentially registered in the registration table. At this time, V=1 and H=0 are registered.

All "0" values are registered in the remaining entries of the registration table.

Registration table 301 created as described above
The upper H bit is used to create a control signal for the counter update circuit 203. The relationship between the H bit value of each entry and the control signal value is as shown in FIG. The meaning of Figure 9 is: (1) If the H ₀ bit (H bit of the 0th entry) is “0”, the 3 (MB/S) high-speed channel is not connected, so in Figure 4 From the channel configuration shown, the value of the control signal is “00”, and (2) even if the _H0 bit is “1”, if the _H4 bit is “0”, the 3 (MB/S) high-speed channel is 1 to 4.
This indicates that the unit is connected, so the value of the control signal is “01”. (3) Similarly, if the _H4 bit is “1”,
This indicates that five or six high-speed channels of 3 (MB/S) are connected, so the value of the control signal becomes "10" and the corresponding counter updating method is selected. That is, the registration table 301
The counter update circuit 2 is controlled by the control signal outputted based on the information registered in the
03, the value of the counter 202 is updated according to the updating method shown in FIG. The input signal corresponding to the channel number registered in is selected.

Therefore, according to the circuit of this embodiment, different data transfer speeds can be set within a limited total transfer speed range by a very simple operation of specifying the data transfer speed of each channel from the SVP during system installation. A combination of channels with (channel configuration)
The advantage is that the channel number can also be specified.

In the above embodiment, an example was shown in which the present invention is applied to a channel control device that controls eight channels, but the present invention is not limited to this.
Needless to say, the present invention can be widely used as a signal selection circuit for arbitrarily setting the selection interval of a plurality of input signals.

Effects of the Invention As described above, according to the present invention, there is provided an input signal identification information registration table consisting of a plurality of entries in which identification information of an input signal is registered in a signal selection circuit that selects one signal from a plurality of input signals; an instruction means for instructing one entry from among the plurality of entries in the identification information registration table; an updating means for updating an instruction value of the instruction means with reference to information registered in the identification information registration table; Since means is provided for selecting one signal from a plurality of input signals based on the input signal identification information in the identification information table read by the instruction value of the instruction means, the information to be registered in the identification information registration table is provided. Accordingly, the selection interval of the plurality of input signals can be set, and a signal selection circuit that is easy to operate can be realized, which is a remarkable effect.

In particular, when the present invention is used as a priority circuit of a channel control device that controls a plurality of channels with different data transfer speeds, it is possible to apply the priority circuit to each channel according to its data transfer speed within the range of the overall data transfer speed. It is possible to realize a channel control device that provides service slots at time intervals, allows the combination of the channels to be easily changed, and also allows the channel numbers assigned to these channels to be set according to the capacity. .

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an overview of the priority circuit of the channel control device, Figure 2 is a diagram showing the channel configuration, and Figure 3 is a block diagram showing the priority circuit for realizing the channel configuration shown in Figure 2. , FIG. 4 is a diagram showing the counter updating method in the circuit shown in FIG. 3, FIG. 5 is a diagram showing the resulting data transfer rate assigned to each channel, and FIG. A block diagram of a priority circuit showing an embodiment, FIG. 7 is a diagram showing input signal identification information, FIG. 8 is a diagram showing a method of creating information in the registration table, and FIG. 9 is a diagram showing the combination of information in the registration table and control information. It is a figure showing a relationship. 201...Selection circuit, 202...Counter, 203
...Counter update circuit, 301...Registration table.

Claims (1)

[Claims] 1. In a signal selection circuit that selects one signal from among a plurality of input signals, an input signal identification information registration table consisting of a plurality of entries in which identification information of an input signal is registered, and an input signal identification information registration table consisting of a plurality of entries in which identification information of the input signal is registered, and among the plurality of entries in the identification information registration table. an instruction means for instructing one entry from the above, an updating means for updating an instruction value of the instruction means with reference to information registered in the identification information registration table, and the identification read out by the instruction value of the instruction means. A signal selection circuit comprising means for selecting one signal from a plurality of input signals based on input identification information in an information registration table.