JPS6128134B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-input signal comparator which compares two systems of multi-input signals and detects a mismatch between the two systems, and which has its own fail-safe property.

In recent years, processors such as microphone processors have been used in various fields, but in signal control devices that require high reliability and fail-safe performance, data processing systems using processors are multiplexed and In addition to performing synchronous operation,
Monitoring is carried out to see if the data of each system match, and a "high-speed signal comparator" (Japanese Patent Application Laid-Open No. 17444-1983) has been proposed in a separate application filed with this application.

However, the content of the patent application requires a considerably complicated circuit to be provided for each bit of each signal, and in the case of a large number of bits, the structure becomes large-scale and has the disadvantage that the device becomes expensive.

The present invention has the purpose of fundamentally eliminating such drawbacks of the conventional technology, and includes a gate circuit that generates a shift pulse based on the logical product of two timing pulses and a data signal, and a gate circuit that generates a shift pulse based on the AND of two timing pulses and a data signal, and a gate circuit that generates a shift pulse based on the AND of two timing pulses and a data signal. a shift register that performs shifting, a delay circuit,
To provide an extremely effective multi-input signal comparator that compares multi-input signals with a simple and inexpensive configuration by skillfully combining a detection circuit that detects the presence or absence of an output change. It is.

Hereinafter, details of the present invention will be explained with reference to figures showing examples.

FIG. 1 is a block diagram showing the configuration, and FIGS. 2 and 3 are timing charts showing the waveforms of each part in FIG _{. 3} and
DS ₂ and DS ₄ are to be given, and the second
As shown in Figures a and l, each data signal DS ₁ to _{DS 4} changes with a period t ₁ , and since both systems operate synchronously, the first data signal
DS ₁ and the second data signal DS ₂ and corresponding ones of the third data signal DS ₃ and the fourth data signal DS ₄ indicate the same logical value "1" or "0". It's summery.

On the other hand, first to fourth timing pulses TP ₁ b to _{TP 4} e generated in synchronization with the change period t ₁ of the data signals DS 1 to DS 4 are provided, and the first and second timing pulses TP ₁ b to TP ₄ e
Taking the gate circuits GC ₁ and GC ₂ as an example, when the data signals DS ₁ and DS ₂ are both "1", the logical product with the timing pulses TP ₁ b and TP ₃ d is an AND gate.
G ₁₁ and G ₂₁ are taken, and the output based on this is ORed
It is sent out via gates G ₁₃ and G ₂₃ and given to the first shift register SRG ₁ as shift pulses f and g, and when the data signals DS ₁ and DS ₂ are “0”, they are sent to the inverters IN ₁₁ and IN. _{twenty one}
AND gates G ₁₂ and G ₂₂ inverted by
Therefore, the logical product with the timing pulses TP ₂ c and TP ₄ e is taken, and the output based on this is passed through the OR gates G ₁₅ and G ₂₃ and becomes the shift pulses f,
It is given to shift register SRG ₁ as g.

In addition, a control pulse CPh synchronized with the period _t1 is given to the shift register _SRG1 , and when this is "1", a shift from the previous stage S _F to the subsequent stage S _R is performed in accordance with the shift pulse f. control pulse
When CPh is "0", a shift in the opposite direction is performed in response to the shift pulse g.

Therefore, if the preset circuit (not shown in the figure) is used to set data "1" in the front stage _SF , the shift from the front stage _SF to the rear stage _SR and the shift in the opposite direction can be performed in response to shift pulses f and g. Shifting is repeated, and output j is obtained from the subsequent stage S _R.

This output j is a delay circuit with a delay time t ₂
It is delayed by DL, becomes the output k, and the second
It is given as a control pulse to the shift register SRG ₂ , and similarly to the shift register SRG ₁ , when the output k is "1", it shifts from the previous stage _SF to the latter stage S _R ,
When it is "0", a shift in the opposite direction is performed.

Therefore, if "1" data is also set in the previous stage _SF of the shift register SRG ₂ , the third and fourth gate circuits configured similarly to the gate circuits GC ₁ and GC ₂
The gate circuits GC ₃ and GC ₄ output the third and fourth data signals DS ₃ and DS ₄ l and the timing pulse TP ₁ b~
Since shift pulses m and n are generated based on the AND with TP ₄ e, data of “1” is transmitted to the front stage S _F and the rear stage S _R
Shifting is repeated between the shift registers SRG and 2, and a constantly changing output p is obtained from the rear stage P _R of the shift register SRG ₂ .

An amplification detector AD as a detection circuit is connected to the output side of the latter stage of shift register SRG ₂ .
As long as the output p changes, it is amplified and detected to put the relay RL into operation.

In the above state, as shown in FIG. 3, if both data signals DS ₃ and DS ₄ l should be in the "1" state, but only the data signal DS ₄ becomes "0". Shift pulse m is timing pulse TP ₁ b
and TP ₂ c occur continuously, and the “1” data in shift register SRG ₂ is further shifted outward from the subsequent stage S _R , so that the shift register
All the contents of SRG ₂ become “0” and the output p does not change from then on, and the amplified detector AD
The detection output disappears and relay RL is restored.

Note that data signal DS ₃ is “0” and data signal DS ₄ is “0”.
The same is true when the data signal becomes “1”.
Depending on the logic mismatch between DS ₁ and DS ₂ , the output j of shift register SRG ₁ remains unchanged, so
The shift register SRG ₂ is no longer shifted, the output p remains unchanged, and the relay RL is restored.

Therefore, the first system data signals DS ₁ , DS ₃
If there is a mismatch between the corresponding data signals DS ₂ and DS ₄ of the second system, the relay is activated.
Inconsistency is detected by restoring the RL.

Therefore, the delay time _t2 of the delay circuit DL is such that its output k is the timing pulse in the next cycle.
It is necessary to select a relationship that matches TP ₁ b to TP ₄ e.

In addition, gate circuits GO ₁ to GO ₄ and shift registers
If an abnormality occurs in any of SRG ₁ to SRG ₂ and the delay circuit DL, the output p will remain unchanged and the relay RL will recover, and the same will occur even if an abnormality occurs in the amplification detector AD. Overall fail-safety is achieved.

Also, due to the mismatch of data signals DS ₁ to DS ₄ ,
Since relay RL returns immediately, mismatch detection is performed at high speed.

However, the shift register SRG ₁ may be a bidirectional shift register that performs bidirectional shifting only in response to the shift pulses f and g, and in this case, the control pulse h can be omitted and the control pulse h can be omitted. , instead of AND gates G ₁₂ and G ₂₂ , use one-input inversion type AND gates and omit inverters IN ₁₁ and IN ₂₁ , or change each gate according to conditions.
The same effect can be obtained by replacing with a NAND gate, a NOR gate, etc., and only a detection circuit may be used in place of the amplification detector AD.

In addition, if the data signals of the two systems have a larger number of bits, a delay circuit DL and gate circuits GC ₃ and GC ₄ are used.
The present invention can be modified in various ways, such as adding each circuit such as shift register SRG ₂ and shift register SRG ₂ to the output side of shift register SRG 2, or taking out outputs j and p from the previous stage _SF side. It is.

As is clear from the above description, according to the present invention, data signals of two systems and multiple bits are compared and a discrepancy is promptly detected using a simple and inexpensive configuration, thereby meeting the requirements for high reliability and fail-safe performance. Remarkable effects can be obtained when applied to various data processing devices.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention; FIG. 1 is a block diagram of the configuration, and FIGS. 2 and 3 are timing charts showing waveforms of various parts in FIG. 1. DS ₁ to DS ₄ ...Data signal, TP ₁ to _{TP 4} ...Timing pulse, GC ₁ to _{GC 4} ...Gate circuit,
SRG ₁ , SRG ₂ ...Shift register, DL...Delay circuit, AD...Amplification detector (detection circuit).

Claims (1)

[Claims] 1 a first gate circuit that generates a shift pulse based on an AND of first and second data signals and first and second timing pulses;
and a second gate circuit that generates a shift pulse based on the logical product of the second data signal and the third and fourth timing pulses; a first shift register that shifts and shifts in the opposite direction in response to a shift pulse from the second gate circuit; a delay circuit that delays the output of the shift register; third and fourth data signals; a third gate circuit that generates a shift pulse based on an AND of the first and second timing pulses; and a third gate circuit that generates a shift pulse based on an AND of the third and fourth data signals and the third and fourth timing pulses; a fourth gate circuit that generates a shift pulse based on the output of the fourth gate circuit; and a shift direction is controlled according to the output of the delay circuit, and the shift direction is controlled from the front stage to the rear stage according to the shift pulse from the third gate circuit; A multi-input device comprising: a second shift register that shifts in the opposite direction in response to a shift pulse from a gate circuit; and a detection circuit connected to the output side of the shift register that detects the presence or absence of an output change. signal comparator.