JPS6128135B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-input signal comparator which compares two systems of multi-input signals and detects a mismatch between the two systems, and which has its own fail-safe property.

In recent years, processors such as microphone processors have been used in various fields, but in signal control equipment that requires high reliability and fail-safe performance, data processing systems using processors are multiplexed and In addition to performing synchronized operation, it is also monitored to see whether the data of each system matches. Proposed.

However, the content of the patent application requires a considerably complicated circuit to be provided for each bit of each signal, and in the case of a large number of bits, the structure becomes large-scale and has the disadvantage that the device becomes expensive.

The present invention aims to fundamentally eliminate such drawbacks of the conventional technology, and includes a gate circuit that generates a shift pulse based on the AND of this data signal and two timing signals, and a gate circuit that generates a shift pulse based on the AND of this data signal and two timing signals, and a gate circuit that generates a shift pulse based on the AND of this data signal and two timing signals. This is an extremely effective multi-input signal that compares multi-input signals with a simple and inexpensive configuration by skillfully combining a shift register that performs shifting to A signal comparator is provided.

Hereinafter, details of the present invention will be explained with reference to figures showing examples.

FIG. 1 is a block diagram showing the configuration, and FIGS. 2 and 3 are timing charts showing the waveforms of each part in FIG _{. 3} and
DS ₂ and DS ₄ are to be given, and the second
As shown in Figures a and k, each data signal DS ₁ to _{DS 4} changes according to the period t ₁ , and since both systems operate synchronously, the first data signal DS ₁ is always
and a second data signal DS ₂ and a third data signal
The corresponding ones of DS ₃ and fourth data signal DS ₄ indicate the same logical value "1" or "0".

On the other hand, first to fourth timing pulses TP ₁ (b) to _{TP 4 (} e) generated in synchronization with the ratio change period t ₁ of the data signals DS ₁ to DS 4 are provided, and Taking the example of the gate circuits GC _{1 and} GC ₂ in No. 2, when the data signals DS ₁ and DS ₂ are both “1”, the logical product of the timing pulses TP ₁ (b) and TP ₃ (d) is an AND gate.
G ₁₁ and G ₂₁ are taken, and the output based on this is ORed
It is sent out via gates G ₁₃ and G ₂₃ and given to the first shift register SRG ₁ as shift pulses f and g, and when the data signals DS ₁ and DS ₂ are “0”, they are sent to the inverters IN ₁₁ and IN. _{twenty one}
AND gates G ₁₂ and G ₂₂ inverted by
Therefore, the logical product with the timing pulses TP ₂ (c) and TP ₄ (e) is taken, and the output based on this is passed through the OR gates G ₁₅ and G ₂₃ and becomes the shift pulses f,
It is given to shift register SRG ₁ as g.

In addition, a control pulse CP ₁ (h) synchronized with the period t ₁ is given to the shift register SRG ₁ ,
When this is "1", a shift from the front stage S _F to the rear stage S _R is performed according to the shift pulse f, and when the control pulse CP ₁ (h) is "0", the shift is performed in the opposite direction according to the shift pulse g. A shift will take place.

Therefore, if the preset circuit (not shown in the figure) is used to set data "1" in the front stage _SF , the shift from the front stage _SF to the rear stage _SR and the shift in the opposite direction can be performed in response to shift pulses f and g. Shifting is repeated, and output j is obtained from the subsequent stage S _R.

On the other hand, the shift direction of the second shift register SRG ₂ is also controlled by the control pulse CP ₁ (h). Front stage S _F according to shift pulse l
A shift is performed from to the rear stage S _R , and a shift in the opposite direction is performed in response to a shift pulse m.

Therefore, if "1" data is also set in the previous stage _SF of the shift register SRG ₂ , the third and fourth gate circuits configured similarly to the gate circuits GC ₁ and GC ₂
The gate circuits GC ₃ , GC ₄ output the third and fourth data signals DS ₃ , DS ₄ (k) and the timing pulses.
Since shift pulses l and m are generated based on the logical product of TP ₁ (b) to TP ₄ (e), data of "1" is repeatedly shifted between the front stage S _F and the rear stage _SR , and constantly changes. An output n is obtained from the subsequent stage P _R of the shift register SRG ₂ .

The output j of shift register SRG ₁ and the output n of shift register SRG ₂ are the third shift register
A control pulse CP ₂ p having a period t ₂ that is twice the period _{t 1 is also applied to the shift register SRG 3 as} a shift pulse, and the shift direction is controlled accordingly. It has become something that is done.

Therefore, if data "1" is set in the previous stage of shift register SRG ₃ , the shift from the previous stage _SF to the subsequent stage _SR will be performed according to the output j, and the shift will be performed in the opposite direction according to the output n. , the constantly changing output q is output from the subsequent stage S _R.
is obtained.

An amplification detector AD as a detection circuit is connected to the output side of the latter stage of shift register SRG ₁ .
As long as the output q changes, it is amplified and detected to put the relay RL into operation.

Regarding the above state, as shown in Figure 3, if both data signals DS ₅ and DS ₄ (k) should be in the "0" state, only the data signal DS ₄ should be in the "0" state. For example, shift pulse l occurs successively at timing pulses TP ₁ (b) and TP ₂ (c),
Since the “1” data in shift register SRG ₂ is further shifted outward from the subsequent stage S _R ,
The contents of shift register SRG ₂ will all become “0” and the output n will not change from then on.
Since the shift operation of the shift register SRG ₃ is no longer performed, the output q remains unchanged, the detection output of the amplification detector AD disappears, and the relay RL is restored.

Note that data signal DS ₃ is “0” and data signal DS ₄ is “0”.
The same is true when the data signal becomes “1”.
Depending on the logic mismatch between DS ₁ and DS ₂ , the output j of shift register SRG ₁ remains unchanged, so
Shift register SRG ₃ is no longer shifted, output q remains unchanged, and relay RL is restored.

Therefore, the first system data signals DS ₁ , DS ₃
If there is a mismatch between the corresponding data signals DS ₂ and DS ₄ of the second system, the relay is activated.
Inconsistency is detected by restoring the RL.

In addition, gate circuits GC ₁ to GC ₄ , shift registers
If an abnormality occurs in any of SRG ₁ to _{SRG 3} , output q will remain unchanged and relay RL will be restored.
The same thing happens even if an abnormality occurs in the amplified wave detector AD, so the overall fail-safe property is realized, and since the relay RL immediately returns to normal state due to a mismatch between data DS ₁ to _{DS 4} , the mismatch can be detected faster. It is done.

However, the shift registers SRG ₁ and SRG ₂ may be bidirectional shift registers that shift in both directions only in response to the shift pulses f, g and l, m; in this case, the control pulses CP ₁ (h)
can be omitted and the AND gate
Instead of G ₁₂ and G ₂₂ , use one-input inversion type AND gates and omit inverters IN ₁₁ and IN ₂₁ , or replace each gate with NAND gates and
The same effect can be obtained by replacing it with a NOR gate or the like, and only a detection circuit may be used in place of the amplified detector AD.

In addition, if the data signals of the two systems have a larger number of bits, gate circuits GC ₁ to GC ₄ and shift registers SRG ₁ to SRG ₃ are additionally provided, and the output of each shift register SRG ₃ is sent to a fourth shift register. The entire structure may be configured in a dendritic manner, such as giving it as a shift pulse and giving it as a control pulse having _a period twice the period t ₂ to _the fourth shift register. The present invention can be modified in various ways, such as the same effect even if the output is taken out from the front stage _SF .

As is clear from the above description, according to the present invention, data signals of two systems and multiple bits are compared and a discrepancy is promptly detected using a simple and inexpensive configuration, thereby meeting the requirements for high reliability and fail-safe performance. Remarkable effects can be obtained when applied to various data processing devices.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention; FIG. 1 is a block diagram of the configuration, and FIGS. 2 and 3 are timing charts showing waveforms of various parts in FIG. 1. DS ₁ to DS ₄ ...Data signal, TP ₁ to _{TP 4} ...Timing pulse, GC ₁ to _{GC 4} ...Gate circuit,
SRG ₁ ~ SRG ₂ ... Shift register, CP ₁ ~ CP ₂ ...
...Control pulse, AD...Amplified detector (detection circuit).

Claims (1)

[Claims] 1 a first gate circuit that generates a shift pulse based on an AND of first and second data signals and first and second timing pulses;
and a second gate circuit that generates a shift pulse based on the logical product of the second data signal and the third and fourth timing pulses; a first shift register that shifts and shifts in the opposite direction in response to a shift pulse from said second gate circuit; and a logical AND of said third and fourth data signals and said first and second timing pulses; a third gate circuit that generates a shift pulse based on the above, and a fourth gate circuit that generates a shift pulse based on the AND of the third and fourth data signals and the third and fourth timing pulses; , a second shift register that shifts from a previous stage to a subsequent stage in response to a shift pulse from the third gate circuit and shifts in the opposite direction in response to a shift pulse from the fourth gate circuit; The shift direction is controlled by a control pulse having a period twice as long as the change period of the fourth data signal, and the shift direction is controlled from the previous stage to the next stage according to the output from the first shift register, and the second shift register A multi-input signal comparator comprising: a third shift register that shifts in the opposite direction according to the output from the shift register; and a detection circuit connected to the output side of the shift register that detects the presence or absence of an output change. .