JPS6128147B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to manual switching schemes in dual processor systems.

In systems that require high reliability, for example, systems in which traffic signals installed at road intersections and other locations are controlled by a center to smooth the flow of automobiles, etc., the central control unit of the center Two processors (CPUs) with the same functions are installed in the system to achieve redundancy. In such a dual processor system, a switching control is provided,
This switching control unit constantly monitors the operating status of each CPU, and if an abnormality occurs in the currently operating CPU (hereinafter referred to as the current system), the current system is immediately disconnected from the external bus, and the other normal CPU (hereinafter referred to as the standby system) is automatically connected to continue system operation.

By the way, in such a dual processor system, due to maintenance, inspection, and other needs, manual
There may be times when you want to switch CPUs. In conventional systems, only a manual switching switch was provided on the operation panel, so there were cases where the CPU could be switched by mistake due to some kind of operational error. Since the CPU executes processing in real time, it is necessary to avoid switching easily due to erroneous operation.

This invention was made in view of the above-mentioned circumstances, and prevents easy switching due to erroneous operation, etc., and only allows switching when a predetermined manual switching operation is performed according to a certain procedure. It provides a manual switching scheme in dual processor systems in which CPU switching is accomplished.

Hereinafter, the content of the present invention will be explained in detail with reference to the drawings.

In Figure 1, two CPUs with the same function
31 and 32 are provided, which are connected to a switching control device 30 through internal buses 37 and 38, respectively, and further connected to an external bus 39 via this switching control device 30. Each CPU31,
32 is connected to internal buses 37 and 38, respectively, and includes internal memories 33 and 35 for storing execution programs of each CPU and common data, and necessary input/output devices 34 and 36, respectively.
The external bus 39 is connected to a data memory and an input/output device, and is also connected to a transmission control circuit (both not shown), and through this transmission control circuit is connected to terminal devices such as traffic lights scattered at various locations. Data is sent and received.

The configuration of the switching control device 30 is shown in FIG. This switching control device 30 includes two timers T1 and T2 for detecting an abnormality to which required times are set, a bus switching gate 42 that switches the connection of internal buses 37 and 38 to an external bus 39, and timers T1 and T2.
The bus switching gate 42 is monitored based on the status of T2 and based on the manual switching input.
It is composed of a monitoring device 41 that controls the. This monitoring device 41 is equipped with a CPU (for example, a microprocessor) that controls switching, and
Operating flags Fa1 and Fa2, which also indicate that CPUs 31 and 32 are currently operating, and CPU
31 and 32 have normal flags Fb1 and Fb2 indicating that they are normal, respectively. Operating flag
Fa1 and Fa2 are set to correspond to the currently operating CPU. Also, the normal flag
Fb1 and Fb2 are set when the CPUs 31 and 32 are respectively normal. In addition, the monitoring device 4
The operation panel 1 or the operation panel installed at a suitable location has a push button switch 4 for confirming manual switching.
3. A switching setting switch 44 for manual switching, and indicator lights 45 and 46 indicating completion of switching are provided. The switching setting switch 44 is used to set whether to switch to the CPU 31 or 32. Indicator lights 45 and 46 correspond to CPUs 31 and 32, respectively.

Automatic switching is performed as follows. both
If the CPUs 31 and 32 are normal, they each output a timer set signal at fixed time intervals shorter than the set times of the timers T1 and T2. This timer set signal is applied to each internal bus 3.
7 and 38, and is sent to each timer T1 and T2, respectively. Each timer T1, T2 is a timer.
When the set signal is input, time counting restarts from 0.
Therefore, each time the timer set signal is input, timers T1 and T2 are set, so the CPU
As long as the timers 31 and 32 are normal, the respective timers T1 and T2 will not time out. CPU3
If an abnormality occurs in one of the CPUs 1 and 32 due to a power supply abnormality, CPU abnormality, or CPU release, the CPU in which the abnormality has occurred will not output the timer set signal, or will be unable to output the timer set signal. Of T1 and T2, the timer corresponding to the CPU in which the abnormality has occurred is timed up. The normal flag is set by this timer up signal.
The corresponding flag of Fb1 and Fb2 is reset. The monitoring device 41 monitors the states of the normal flags Fb1 and Fb2, and when either of the normal flags is reset, the bus switching gate 42 is configured to switch the abnormal CPU to a normal CPU.
control. For example, if the normal flag of the standby system is set when the normal flag of the current system is reset, the bus connection is switched from the current system to the standby system.

Manual switching is performed as follows. The staff member who performs manual switching first sets the system to be switched (standby system) using the changeover switch 44. Then, push button switch 43 is pressed to reset the currently operating CPU system. Then, the user continues to press the push button switch 43 until the indicator lamp of the system to be switched among the indicator lamps 45 and 46 lights up. Since the CPU that has been reset by the staff member stops operating, the corresponding timer times up as described above. Then, the monitoring device 41 confirms that the pushbutton switch 43 is pressed and that the normal flag of the system set by the switch 44 is set, and changes the bus connection from the current system to the standby system. , and the standby system switching completion indicator lights up.

The processing procedure of the CPU of such a monitoring device 41 is shown in FIG. Here, the CPU 31 is the active system, and the CPU 32 is the standby system. Also
The CPU 31 is shown as a CPU, and the CPU 32 is shown as a CPU. This switching process is started when the power of the line system including the above-mentioned transmission control circuit is turned on, when there is an instantaneous power failure in the active system or the standby system, and when timer T1 or T2 is timed up.

If the line system power is turned on, the line system can operate from this point on, so the CPU
An interrupt is generated to indicate that the power to the line system has been restored (step 1), and the switching gate 42 is opened (step 2). This is a process for temporarily disconnecting both internal buses 37, 38 from external bus 39, as a step before connecting to either bus 37, 38 in the following process. Next, wait for a certain period of time to pass (step 3). this is,
This is the time from when both CPUs set timers T1 and T2 until the normal flags F1 and F2 are set. In manual switching, this is the time taken to confirm that the manual switching switch 43 has been pressed for a certain period of time. It's time.

The normal flag is flagged due to momentary power failure or timer T1 or T2 time-up.
When Fb1 and Fb2 are reset, the operating flag indicates whether the corresponding CPU is operating.
Judgments are made based on the states of Fa1 and Fa2 (steps 4 and 6), and if flags Fa1 and Fa2 are set, the corresponding in-operation flag is reset (steps 5 and 6). For example, when an abnormality occurs while the current CPU is operating, the corresponding timer T1 times up and the normal flag Fb1
If the flag is reset, the corresponding active flag Fa1 is reset (steps 4 and 5). Timer T that responds when an error occurs in the standby CPU
2 has timed up and the normal flag Fb2 is reset, this CPU is not in operation and the in-operation flag Fa2 has been reset (NO in step 6), so the process ends.
After processing step 5 or step 7, the process proceeds to step 2.

When a certain period of time has elapsed in step 3, it is checked whether the manual changeover push button switch 43 has been pressed (step 8). If the switch 43 has not been pressed down, automatic switching is required and the process proceeds to step 14; if it has been pressed, manual switching is required and the process proceeds to step 9.

In step 14, it is checked whether the operating flag Fa1 is set, and if this flag Fa1 is not set, the process proceeds to step 15, where it is checked whether the operating flag Fa2 is set. If the flag Fa2 is set, the process advances to step 16. Flag in step 14
If Fa1 is set and step 1
If the flag Fa2 has been reset in step 5, the process moves to step 10, which will be described later.

In step 16, it is checked whether the normal flag Fb2 is set, and if this flag Fb2 is set, the process proceeds to step 18, in which the internal bus 38 of the CPU is connected to the external bus section 39 by the bus switching gate 42. , and lights up the indicator light 46. Then, it sends an interrupt to the CPU indicating that it has been switched (step 19), sets the active flag Fa2, and resets Fa1 (step 20).

If it is determined in step 16 that the normality flag Fb2 has been reset, the process advances to step 17 to check whether the normality flag Fb1 has been set. If this flag Fb1 is set, the process moves to step 11, which will be described later, and if it is reset, the process ends.

In the case of manual switching, check which CPU is set by the changeover setting switch 44 (step 9), and if the CPU is set, proceed to step 10 and set the normal flag Fb1. If the flag Fb1 is set, the program proceeds to step 11, where the internal bus 37 of the CPU is connected to the external bus 39 and the indicator light 45 is turned on. Then, an interrupt is generated to indicate that the CPU has been switched (step 12), and finally, the operating flag Fa1 is set and the flag Fa2 is reset.

If the CPU is set in step 9 and if the flag Fb1 is reset in step 10, the process moves to step 16.

When the power to the line system is turned on and the above switching process is executed, proceed to steps 1 to 3 and 8.
If the answer is NO at step 8, the process moves to step 14.
At this time, if the CPU is operating and the flag Fa1 is set, the answer is YES in step 14, and the process moves to step 10. Then, if the CPU is normal and flag Fb1 is set, proceed to step 1.
Proceed to step 1 and connect the CPU. If the CPU is in operation and the CPU is not in operation, the answer at step 14 is NO and the process proceeds to step 15, where the answer is YES. Then, the process proceeds to step 16, and if the normal flag Fb2 is set, the process further proceeds to step 18, where the CPU is connected.

When an abnormality occurs in the current CPU, the process proceeds from step 4 to step 5, 2, 3, and 8, and then moves from step 8 to step 14. The operating flag Fa1 has already been reset in step 5, so step 1
If 4 is NO, proceed to step 15. If flag Fa2 is also reset during operation, the process moves from step 15 to step 10, and the normal flag is reset.
Check whether Rb1 is set. Since this flag Fb1 has been reset, the process moves from step 10 to step 16, and the normal flag Fb2 is reset.
Check the condition. If this flag Fb2 is set, the process advances to step 18, where switching to the standby system is performed.

If an error occurs while the CPU is operating, it can be switched to the CPU in the same way.

When the current system CPU is manually switched to the standby system while it is in operation, the CPU is set by the setting switch 44 and the pushbutton switch 43 is pressed. In this case, the process proceeds from step 4 to step 5, 2, 3, and 8, and from step 8 to step 9. Since the answer at step 9 is NO, the process moves to step 16, and if the normal flag Fb2 is set, the process moves to step 18, so that switching to the CPU is performed.

As explained in detail above, the present invention includes a changeover setting switch that specifies and sets the processor to be connected by switching, and a pushbutton switch that confirms the changeover, and that the pushbutton switch is pressed for a certain period of time. Since the connection of the external bus is switched to the processor set by the above setting switch on the condition that the push button/switch is This operation allows you to fully confirm the switching operation and prevents any erroneous operation.Also, simply touching both switches with some object will not result in switching the processor, so it is possible to confirm the switching operation inadvertently. There is also no chance of erroneous switching.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an overview of the dual processor system, FIG. 2 is a block diagram showing the configuration of a switching control device, and FIG. 3 is a flow chart showing the operation of this switching control device. 30... Switching control device, 31, 32... Processor, 37, 38... Internal bus, 39... External bus, 41... Monitoring device, 42... Bus switching gate, T1, T2... Timer, 43... ...Confirmation push button/switch, 44...Switch setting switch.

Claims (1)

[Claims] 1. A bus switching gate that switches the connection of two processors with the same function to an external bus, a switching setting switch that specifies and sets the processor to be connected by switching, and a push button switch that confirms switching. A manual switching method in a dual processor system, which switches the external bus connection to the processor set by the setting switch on the condition that the pushbutton switch is pressed for a certain period of time.