JPS6129078B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention is a junction-destructive P-ROM (Progra-ROM).
The present invention is particularly concerned with word line drive circuits (mable-Read Only Memory).

As the word line drive circuit 1, the one shown in FIG. 2 is known. This circuit consists of transistors Q ₁ ,
TTL (Transistor) configured by Q ₂
An address decoder circuit using a Transistor Logic (Transistor Logic) circuit and a transistor that amplifies the current of this output.
Q ² ′ and an output transistor Q ₃ .

This output transistor _Q3 is connected to the transistors that make up the memory matrix during writing.
The resistor R ₁ is set so that the large current (approximately 200 mA) required to cause junction breakdown to Q ₁₀ can be passed.
~R ₂ ′ is determined. Further, the area occupied by the transistor is also large.

Therefore, this circuit requires an amplification transistor Q ₂ ' to form an input current to obtain the above-mentioned large output current, and the output transistor Q ₃ is formed large, which reduces the integration density. ,Also, although the current required for readout is as small as about 1mA, the transistor
Since Q ₂ ′ is used, an increase in power consumption is unavoidable.

The present invention was made in order to provide a junction breakdown type P-ROM that improves integration density and reduces power consumption.

This invention utilizes a high write voltage to increase the base current of the word line output transistor during writing, so that the current necessary for the writing flows through the output transistor.

Hereinafter, the present invention will be specifically explained with reference to Examples.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

1 is a word line drive circuit according to the present invention, which includes a multi-emitter structure transistor Q ₁ forming an address decoder output, a current amplifying transistor Q ₂ which receives the decoder output as input, and a collector of this transistor Q ₂ and a power supply. Voltage terminal Vcc
A resistor R ₂ and a backflow prevention diode D ₁ are provided between the
The collector of this transistor Q ₂ and the output terminal OUT
and a Zener diode Dz and a backflow prevention diode _D2 that set the drive input current during writing, the emitter load resistance _R3 of the transistor _Q2 , and an output transistor _Q3 that receives this emitter output as an input. It is composed of

A word line W is connected to the collector of this transistor _Q3 .

Note that 2 _W is a digit line drive circuit for writing, and 2 _R is a digit line drive circuit for reading.

A transistor _Q10 is provided at the intersection of the word line W and digit line D to form a memory matrix. In this figure, only one of them is shown.

Writing in this P-ROM circuit is performed as follows. The transistor _Q10 that causes junction breakdown is designated by the X address and Y address.
Then, a high voltage for writing, for example, a high voltage of about 28V, is applied to the output terminal.

All Y addresses go high, all diodes forming the decoder output turn off, and transistor _Q5 turns on. Therefore,
A write current of 200 mA is generated through the transistor Q ₄ which is turned on by the high voltage supplied from the output terminal OUT, and the Darlington-connected transistors Q ₅ to Q ₇ .

On the other hand, on the word line, all X addresses are at high level, and the multi-emitter transistor _Q1
All emitters and bases of the transistor Q1 are reverse biased, causing current to flow from the base of the transistor _Q1 to the collector, turning on the transistor _Q2 . At this time, a high voltage is supplied to the collector of transistor Q ₂ via the Zener diode Dz, which is turned on by the write voltage, so
The collector current can be made large without being subjected to the current limiting action by the resistor R ₂ and by applying a high voltage. Therefore, since the emitter current also increases, it becomes possible to supply the input base current necessary to flow about 200mA to the output transistor _Q3 , and the transistor
There is no need to increase the area occupied by Q ₂ and Q ₃ , and the integration density can be improved.

By passing the above-mentioned large current, the base-emitter junction of the transistor _Q10 constituting the memory matrix is destroyed, and the transistor Q10 acts as a diode extending from the digit line D to the word line W.

At this time, the backflow prevention diode D1 in the word line drive circuit ₁ causes the output terminal OUT to which the write high voltage is applied to be connected to the power supply voltage terminal.
No current flows into Vcc. Similarly, the write current directed to the read digit line drive circuit _2R is also blocked by the diode _D4 .

Next, a read operation is performed as follows.

The X address information turns on the transistor _Q2 of the word line drive circuit 1 in the same manner as described above. Since the Zener diode Dz is off (no high voltage is applied to the output terminal), the output current of the transistor Q ₂ at this time is equal to the small current required for readout set by the resistors R ₁ and R ₂ . Become. In other words, a small current is obtained to form a read current (approximately 1 mA) flowing through the output transistor _Q3 .

On the other hand, when all the decoder diodes are turned off by the Y address information, current is supplied to the digit line D via the resistor _R6 , and the transistor _Q10 of the memory matrix is turned on (the one written above). If so, a current flows through transistor Q ₁₀ to transistor Q ₃ and the digit line becomes low level, so that a low level is output through transistors Q ₈ and Q ₉ , and transistor Q ₁₀ of the memory matrix is output. If is off, digit line D will be at high level,
A high level is output via transistors Q ₈ and Q ₉ .

4 is an amplifier that amplifies this read level. When this readout output is low level,
In order to prevent current from flowing from the collector of transistor Q ₂ toward the output terminal OUT, a backflow prevention diode D ₂ is connected to the Zener diode Dz.
is provided.

According to the example circuit described above, for example, when configuring a 4K-bit memory matrix, 64 word line drive circuits are required. Since the area and number can be reduced, the integration density can be greatly improved.

The large current during writing uses a high writing voltage, so the transistor
Current settings for Q ₁ and Q ₂ can be made assuming a small current during readout, resulting in lower power consumption. That is, in the conventional circuit, since the current flowing through the matrix transistor _Q10 as a read current is a small current determined by the read digit line drive circuit _2R , the word line drive output transistor _Q3 has Although only the above-mentioned small current flows, a large current set to obtain the above-mentioned large current flows through the transistors Q ₁ to _{Q 2} ' that are the input circuit. Since unnecessary current can be reduced, power consumption can be reduced.

The present invention is not limited to the embodiments described above, and the decoder circuit constituting the word line drive circuit may be replaced with a diode or the like. Furthermore, if necessary, a resistor may be provided in series with the Zener diode. Furthermore, other digit line drive circuits can be modified in various ways.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention;
FIG. 2 is a circuit diagram showing an example of the prior art. DESCRIPTION OF SYMBOLS 1... Word line drive circuit, 2 _W ... Digit line drive circuit for writing, 2 _R ... Digit line drive circuit for reading, 3... Matrix section, 4...
...readout amplifier.

Claims (1)

[Scope of Claims] 1. A word line drive circuit 1 which is provided with a memory element _Q10 at the intersection of a word line W and a digit line D, and which is connected to the word line 1 and to which a power supply voltage Vcc is applied; It is equipped with digit line write/read drive circuits 2W and 2R connected to the digit line D and to which the power supply voltage Vcc is applied, and applies a high voltage to at least the word line when writing information to the memory element _Q10 . A P-ROM characterized in that it is supplied to the drive circuit 1 and the write circuit portion 2W of the digit line write/read drive circuits 2W and 2R. 2 The word line driving circuit 1 includes a base to which an address decoder output is supplied, a word line driving input transistor Q ₂ having an emitter coupled to a resistive element, and the word line driving input transistor Q 2 .
The collector of the word line driving output transistor _Q3 is connected to the word line _{W ,} and when writing information, the high voltage is applied to the word line W. Input transistor for word line drive
The P-ROM according to claim 1, characterized in that the P-ROM is supplied to the collector of _Q2 .