JPS6129152B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device incorporating Darlington-connected transistors.

When high gain or input impedance is required, a Darlington circuit is generally used, and this circuit is as shown in FIG.

That is, a high resistance R ₁ is connected between the emitter and base of the driver transistor Tr ₁ , and a low resistance R ₂ is connected between the emitter and base of the output stage transistor Tr ₂ , and the collector is shared with the driver transistor Tr. The output of emitter Tr ₁ is directly connected to the base of output stage transistor Tr ₂ .

When a Darlington circuit having such a configuration is to be incorporated into a semiconductor chip of a limited size, a problem arises as to how to incorporate the high resistance _R1 . That is, as is well known, in a structure in which the diffusion layer is a resistance layer, there is a limit to the specific resistance of the diffusion layer, so the area occupied within the semiconductor chip must be increased. Therefore, for example, by forming an n-type diffusion layer in the P-type diffusion layer, the thickness of the P-type diffusion layer can be reduced, and at the same time, the n-type diffusion layer can be formed in most of the high concentration part of the P-type diffusion layer. Methods such as incorporating superimposed interrupt type resistors have been adopted, but it has not been possible to obtain a sufficiently high resistance.

Therefore, semiconductor devices incorporating a resistor as described below are generally known. That is, the plan view of Fig. 2a and _A- of Fig. 2a
As shown in FIG. 2b showing the cross section of _A , an N ^- type silicon layer 2 is formed on the main surface of an N ⁺ type silicon substrate 1 by, for example, epitaxial technology, and P type impurities are diffused throughout this surface. P ⁺ type silicon layer 3
is formed. Then, on the surface of the P ⁺ -type silicon layer 3, N-type impurities are selectively diffused into a part of the upper right-hand region and a part of the region other than the above-mentioned region, forming N ⁺ -type diffusion layers 4 and 5, respectively. It is formed. In this way, the N ⁺ type diffusion layer 4
-P ⁺ type silicon layer 3 - N ^- type silicon layer 2 constitutes a driver transistor Tr ₁ , and N ⁺ type diffusion layer 5 - P ⁺ type silicon layer 3 - N ^- type silicon layer 2 constitutes an output stage transistor Tr. ₂ is configured. An N ⁺ type diffusion layer 6 is formed at the boundary between the driver transistor Tr ₁ and the output stage transistor Tr ₂ , which is formed simultaneously with the N ⁺ type diffusion layers 4 and 5, and both ends of the driver transistor Tr 2 are formed at the boundary between the driver transistor Tr 1 and the output stage transistor Tr 2.
In addition to being connected to the P ⁺ type silicon layer 3 of Tr ₁ and the P ⁺ type silicon layer 3 of the output stage transistor Tr ₂ , the grooves 7 and 8 formed around the N ⁺ type diffusion layer 6 in the longitudinal direction are Therefore, it is separated from the P ⁺ type silicon layer 3. In this way, the P ⁺ type silicon layer 3 directly under the N ⁺ type diffusion layer 6 is used as the high resistance R ₁ . The peripheral side of the pellet of the semiconductor device formed in this way is cut, and the extension of the depletion layer generated from the junction between the P ⁺ type silicon layer 3 and the N ^- type silicon layer 2, which contributes to the withstand voltage, is removed, especially at the edges. We are making it possible to increase the amount. Note that since the low resistance R ₂ connected between the base and emitter of the output stage transistor Tr ₂ has a small value, the resistance of the P ⁺ type silicon layer 3 itself, which is the base layer, is used.

In this way, the high resistance R ₁ is the P ⁺ type silicon layer 3
Using the bottom part of , that is, the part where the impurity concentration is small,
Also, by narrowing the distance between the grooves 7 and 8, a high resistance value is obtained.

However, in such a configuration, since the grooves 7 and 8 are formed, the bonding surface between the N type diffusion layer 6 and the P ⁺ type silicon layer 3 is exposed on the side surface of the grooves.
In order to protect this, it is necessary to cover it with a passivation film. However, the formation of this passivation film is difficult and has been an obstacle to improving reliability. Therefore, it is conceivable to increase the width of each of grooves 7 and 8 to facilitate the formation of a passivation film, but an abnormally deep etched groove is formed at the bottom of the groove, which may cause deterioration due to thermal strain or the like.

Furthermore, in order to form such grooves 7 and 8, chemical etching is carried out using a silicon oxide film, which will later become an insulating film, as a mask, but since this etching also progresses in the lateral direction, the silicon oxide film The opening side protrudes (shape) like an eaves. Therefore, when forming a passivation film,
The protrusion of the silicon oxide film becomes an obstacle, resulting in the disadvantage that the insides of the grooves 7 and 8 are not sufficiently passivated.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device which has high resistance without forming a groove, thereby facilitating the formation of a passivation film.

In order to achieve such an object, the present invention incorporates Darlington-connected transistors by forming individual emitter layers at approximately the center and the periphery of a common base layer surface formed by diffusion on the upper surface of a semiconductor substrate. A non-conductive layer is formed surrounding the central emitter layer, and the base layer directly under the non-conductive layer serves as a resistor connected between the emitter and base layers of the driver transistor.

Hereinafter, the present invention will be explained in detail using Examples.

FIGS. 3a and 3b are a top view and a cross-sectional configuration diagram showing an embodiment of a semiconductor device according to the present invention.
Figure 3a is a plan view, Figure 3b is _A- of Figure 3a.
Represents a cross-sectional view at _A. In the same figure, N ⁺
An N ^- type silicon layer 12 is formed on the main surface of a type silicon substrate 11 by, for example, epitaxial technology, and a P type impurity is selectively diffused into one region of this surface.
A P ⁺ type silicon layer 13 is formed. Then, N-type impurities are selectively diffused into the central and peripheral regions of the surface of the P ⁺ -type silicon layer 13 to form N ⁺ -type diffusion layers 14 and 15, respectively.
is formed. In this way, the driver transistor Tr ₁ is constituted by the N ⁺ type diffusion layer 14 - the P ⁺ type diffusion layer 13 and the N ^- type silicon layer 12.
The output stage transistor Tr ₂ is composed of the N ⁺ type diffusion layer 15 - the P ⁺ type diffusion layer 13 and the N ^- type silicon layer 12 . Note that the planar shape of the N ⁺ type diffusion layers 14 and 15 is uneven to prevent current concentration, and the peripheral length is increased. Further, an N ⁺ type diffusion layer 16 formed simultaneously with the N ⁺ type diffusion layers 14 and 15 is provided surrounding the N ⁺ type diffusion layer 14 .
This N ⁺ type diffusion layer 16 is a non-conductive layer, and by providing this layer, the thickness of the base layer 13 immediately below is reduced, and only a low concentration region is formed, so that the driver transistor Used as the resistor _R1 connected between the emitter and base layers of _Tr1 .

In this way, high resistance can be obtained without forming grooves on the semiconductor surface unlike the conventional method, so that the passivation film can be easily formed.
Note that in the past, a technique was known in which a non-conductive layer consisting of a diffusion layer etc. was formed and the diffusion layer immediately below this layer was used as a resistor.
In the plan view of the figure, it was formed in the N type diffusion layer 6 region. Therefore, its resistance value is low,
In order to increase this, even if the width of the non-conductive layer is increased, it will hinder integration, so controls have been put in place. Incidentally, in the above embodiment, as shown in FIG. 3b, the width of the N-type diffusion layer 16 is l, the inner diameter is W, the thickness of the P-type silicon layer 13 directly under the N-type diffusion layer 16 is t, and the specific resistance is ρ, l=300μ, W=
When 300μ, t=3μ, ρ=6Ωcm, R ₁ ≧5K
Ω is obtained, and when ρ=30Ωcm, R ₁ ≧25K
It turns out that Ω can be obtained.

In this embodiment, as a non-conductive layer surrounding the emitter layer 14 of the driver transistor, an N ⁺ type diffusion layer 16 is formed simultaneously with the emitter layer of each transistor. Furthermore, the same effect can be obtained by forming an N ⁺ type diffusion layer 18 on the inner peripheral surface of the moat 17 as shown in FIG. The point is that the object of the present invention can be achieved by forming a layer that does not conduct electricity. Therefore, it may be a silicon oxide film layer formed by selective oxidation. It should be noted that forming the moat 17 poses a problem of passivation film formation, but in the case of FIG. 4 there is no joint, and in the case of FIG. 5 the joint is not exposed on the side of the moat 17. In either case, defects in the formation of the passivation film will no longer affect the electrical characteristics.

Further, in this embodiment, for example, one non-conductive layer of the N ⁺ type diffusion layer 16 is formed, but the number is not limited to one, and a plurality of non-conductive layers may be provided concentrically. For example, when it is desired to form a moat with a large width, an abnormally deep etching groove is formed at the bottom of the moat.In order to prevent the negative effects caused by this, it is necessary to provide a plurality of moats with a small width concentrically. You will be able to increase your effectiveness.

Further, in this embodiment, the base layer 13 is formed by selective diffusion for each semiconductor device, but non-selective diffusion may be performed, and the side surfaces of the pellets may be pebble-cut during dicing. However, if configured as in this embodiment, there is an advantage that the characteristics of each semiconductor device can be inspected at the wafer process stage.

As described above, the semiconductor device according to the present invention has high resistance without forming a groove, thereby making it possible to easily form a passivation film.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a Darlington circuit, FIGS. 2 a and b are block diagrams showing an example of a conventional semiconductor device incorporating a Darlington circuit, and FIGS. 3 a and b are one embodiment of a semiconductor device according to the present invention. A configuration diagram showing an example,
4 and 5 are cross-sectional configuration diagrams showing other embodiments of the semiconductor device according to the present invention. 1, 11...N ⁺ type silicon substrate, 2, 12...
...N ^- type silicon layer, 3, 13... P ⁺ type silicon layer, 4, 5, 6, 14, 15, 16... N ⁺ type diffusion layer, 7, 8... groove.

Claims (1)

[Claims] 1. Incorporate Darlington-connected transistors by forming individual emitter layers approximately at the center of the common base layer surface formed by diffusion on the upper surface of the semiconductor substrate and at its periphery, and this Darlington-connected transistor a driver transistor including an emitter layer in the central part, and an output stage transistor including the emitter layer in the peripheral part at the periphery, and forming a non-conductive layer surrounding the emitter layer in the central part;
A semiconductor device characterized in that a base layer directly below this non-conductive layer serves as a resistor connected between an emitter and a base layer of a driver transistor.