JPS6129167B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a circuit constituting a secondary digital filter, and particularly to a circuit in which a multiplication circuit is realized by an adder/subtracter having a simpler structure. The second-order digital filter is given by the following state equation, where the input is {x _i }, the output is {y _i }, and the internal variable is {w _i }.

[Table] Here, α ₁ and α ₂ are constants indicating the pole positions of the secondary digital filter, and β ₁ and β ₂ are constants indicating the zero point, which determine the frequency characteristics of the filter. . Assuming that the Nyquist sampling time is T, the frequency characteristics are as follows: H(e ^j 〓 ^T ) = 1 + β _1e ^−j 〓 ^T + β _2e ^−j 〓 ^T
/1+α _1e ^−j 〓 ^T +α _2e ^−j2 〓 ^T (2). In other words, to configure the second-order digital filter, α is used to calculate the internal variable w _i
Two multiplications, ₁ w _i-1 and α _{2 w i-2,} are required, and two multiplications, β ₁ w _i , β _{2 w i-2} , are also required to calculate the output y _i . It is. In the end, four multiplications are required to construct the second-order digital filter. Conventionally, when configuring such a digital filter, configuring the multiplier circuit with parallel multipliers would result in too large a circuit scale.
As a multiplication circuit, an accumulator that uses the so-called "addition and shift multiplication algorithm" is usually used, and when used in a high frequency range or when a high multiplicity is required, a secondary filter is required. A method using four accumulators corresponding to four multiplications was used. The accumulator referred to here has an addition input that is either directly or right-shifted (multiplyed by 2 ^-1 ) the accumulation result from one time ago, and the augend input corresponds to the multiplicand. It consists of an adder that inputs a numerical value or zero. The minimum sampling period (Nyquist period) T of a secondary digital filter having such a structure is the maximum operating period of the accumulator T', and the coefficient bit length (the above α ₁ , α ₂ , β ₁ , β _{2 )} . each bit length) is n
Then, since nT' is required for multiplication and addition/subtraction shown in equation (1) is also required, T≧nT' (3). The equality is true only when there is an addition circuit for calculating equation (1) in addition to the accumulator. If the bit pattern of the coefficient is special, there is a possibility that the minimum sampling period can be further shortened, but such an effect cannot be expected at the digital filter circuit design stage, so Equation (3) is It can be considered as the limit of In other words, according to the conventional method, four accumulators are required, and the sampling period is limited to equation (3). An object of the present invention is to halve the number of required accumulators to two by simply adding subtraction to the accumulator function without changing the limit of the sampling period. The accumulator used in the present invention has means for adding or subtracting the contents of three registers or zero, and the accumulation result can be directly or right-shifted (2 ^-1
The structure of the digital filter according to the present invention includes two such addition/subtraction accumulators and an input register for storing {x _i }. , {y _i }, and an internal state register that stores internal variables {w _i-1 } {w _i-2 }.The first addition/subtraction accumulator is connected to the input register and the internal state register. , {w _i },
A second add/sub accumulator is connected to the first add/sub accumulator output, an internal state register, and calculates {y _i }.
An output register is connected to the second add/sub accumulator output. The principle of the invention is to utilize a binary multiplication technique. What is the binomial multiplication method? Variables x ₁ , x ₂ , coefficient A ₁ ,
This is a method of processing P=A ₁ x ₁ +A ₂ x ₂ (4) for A ₂ (individual coefficient) by accumulating the coefficient bit length. now,

【formula】

[Formula] Then, equation (4) can be transformed as follows. Here, f _j ∈{0,1} C _j ∈{1,0,−1} indicates logical negation. The expansion method from equation (5) to equation (6) will be described later.
A good way to obtain equation (6) in cumulative form is to follow the recurrence formula shown below.

[Table] It can be easily proven that equation (7) becomes equation (6) by sequentially substituting equation (7C) into the right-hand side of equation (7B). Equation (7C) can be further expanded as follows depending on the values of C _j and f _j .

[Table] According to this formula, the shift of the sum of partial products P _j-1 (・
2 ^-1 ) and x ₁ or x ₂ once, a new sum of partial products can be found, and P _N can be found at the (n+1)th time counting from P _O. In other words, the binomial sum of products can be processed in (n+1)T' by using an accumulator that adds such subtraction. Therefore, the binomial product sum can be processed in about the same amount of time as the single multiplication. There are several possible ways to determine {f _j } and {C _j } necessary for formulas (5) to (6), but the most efficient method (that is, the bit length of {f _j }, {C _j } becomes n+1)
The coding method is shown below. The method shown below eliminates bit positions where both coefficients A ₁ and A ₂ have non-zero values at the same time by allowing the bit positions to have three values: 0, +1, and -1. , We use the fact that holds true identically. {f _j }, {C _j } can be constructed by performing the following steps. However, if both coefficients are 0 up to the LBS below the bit position determined in the first step 1, both LBSs are expanded by 1 bit and different values (one is 0 and the other is 1) are entered in the new LSB. Step 1: Examine both coefficients A ₁ and A ₂ from the LSB side to the MSB side, and detect the bit position (p) where they become 1 at the same time. Step 2 Examine both coefficients from bit position p to the LSB side, and for A _k (k = 0.1) whose bit position (q) is 1 first, from a ^k _q to a
^k _p-1 is set to -1, a ^k _p is set to 0, and the p+1th bit of A _k is arithmetically incremented by +1. Step 3 Step 1, Step 2 to MSB
Repeat and convert {a ¹ _j }, {a ² _j } into a ternary sequence {α
¹ _j }, converted to {α ² _j }. Step 4 Define {f _j } as {f _j |f _j =|α ¹ _j |}. Here, ｜ indicates an absolute value. {C
_j } is defined as {C _j |C _j =α ¹ _j 〓α ² _j }.
Here, ん is diadic addition.
shall be. The above construction method also proves that it is possible to expand the two coefficients A ₁ and A ₂ into {C _j } and {f _j }, and because of the arithmetic addition in step 2, the maximum 1-bit MSB May be extended laterally. Therefore, it is sufficient to consider the length of n+1 bits for {f _j } and {C _j }. As an example, the means for obtaining {f _j } and {c _j } in the case of A ₁ =11011010 ₂ and A ₂ =10111001 ₂ will be described. First, in step 1, A ₁ and A ₂ are converted to LSB
If the test is started from the LSB side simultaneously, the fourth bit from the LSB side becomes 1 at the same time, and P=4 is obtained. From the 4th bit towards the LSB side by step 2
If you start testing A ₁ and A ₂ at the same time, the LSB of the coefficient of A ₁
There is a 1 in the second bit from the side. For this reason, q=
2, and set the second to third bits to -1 for _A1 , and set the fourth bit to 0,
Furthermore, 1 is arithmetically added to the 5th bit. In other words, A ₁ becomes as follows.

[Table] _---
11010110
In this case, it can be easily verified that both 11011010 ₂ and 11100110 ₂ indicate 218. Step 3 means repeating Steps 1 and 2 to eliminate bits with overlapping non-zero elements from LSB to MSB. Returning to step 1 using the new representation of A ₁ and A ₂ , in this case p=6. Moving on to step 2, from p=6
When searching to the LSB side, q=5, and A ₂ must be changed. As a result, A ₂ = _110110012 . If step 1 is repeated for A ₁ = _111001102 and _A2 = _110110012 , p=7. In step 2, q=6 and changes are made to _A1 . As a result, A ₁ = _1001001102 .
A ₁ and A ₂ were initially displayed as 8 digits, but after this process, they are now 9 digits. _A1 , _A2
When both are displayed in 9 digits, A ₁ = 100100110 ₂ A ₂ = 011011001 ₂ , and A ₁ and A ₂ are designed so that non-zero does not appear in the same digit. Step 3 is executed as described above, and {α ¹ _j }={100100110} {α ² _j }={011011001}. {f _j }, {c _j }, {α
¹ _j } and {α ² _j } as follows. {f _j }={100100110} {c _j }={111111111} In other words, even if A ₁ and A ₂ are expressed as {α ¹ _j } and {α ² _j }, the values of A ₁ and A ₂ are If it is unchanged and α ⁱ _j is zero, α ⁱ _j X _i is zero and there is no need to calculate the product in equation (5). When one coefficient is non-zero, the other is always zero, so 9 times (n+1
binomial product sum can be performed by adding partial products (times), and A ₁ X ₁
{f _j } indicates which of the partial products generated from and A ₂ X ₂ is used. In other words, if f _i = 1, _the A ₁ X ₁ side is selected; if f _i = 0, _{the A 2} It will be understood that if C j = 0, it indicates that the partial product is to be subtracted, and further, that C _j =0 indicates that no addition or subtraction is to be performed. Although the dyadic multiplication method has been understood from the above, some changes are required to apply it to a digital filter. In other words, although the dyadic multiplication method can be applied to equation (1), the dyadic multiplication method alone is insufficient. Equation (1) for specifying the part where the binomial multiplication method can be used in Equation (1) can be summarized as follows.

[Table] In Equation (9), the binary multiplication method can be applied to the parts in parentheses, but it is necessary to further add w _i and x _i respectively. Therefore, in the binomial product-sum accumulator, the accumulation result is always multiplied by 2 ^-1 , but because of the addition of w _i and x _i ,
2 It is necessary to have a function to perform accumulation results without multiplying by ^-1 and a means to use not only w _i-1 and w _i-2 as variables but also x _i and w _i as inputs to the accumulator. . A digital filter can be constructed by using two accumulators modified in this way. The figure is a block diagram showing one embodiment of the present invention, and reference numerals 1 and 2 are internal registers for storing the internal states w _i-1 and w _i-2 , respectively. Reference numeral 3 is an input register that stores the input data x _i , and reference numeral 4 is an output register that stores the output data y _i . Reference numerals 5 and 6 indicate addition/subtraction accumulators, which are a feedback addition/subtraction accumulator for calculating the internal state w _i and a feedback addition/subtraction accumulator for calculating the output data y _i , respectively. The feedback addition/subtraction accumulator includes a selection circuit 5 that selects one of internal status registers 1 and 2 input registers 3 and 0 as the accumulator input.
1. An addition/subtraction circuit 52 that performs addition/subtraction, an accumulation register 53 that stores the output of the addition/subtraction circuit, and either direct or right shift (multiplyed by 2 ^-1 ) of the output of the accumulation register 53 to the input of the addition/subtraction circuit 52. The selection circuit 54 selects and transmits the selected information. The feed-back addition/subtraction accumulator includes a selection circuit 61 for selecting one of the internal status registers 1, 2 accumulation registers 53 and 0 as an accumulator input, and an add/subtractor 52 of the feedback addition/subtraction accumulator component; An accumulation register 53, an adder/subtractor 62 that functions in the same way as the selection circuit 54, and an accumulation register 6.
3. Consists of a selection circuit 64. Reference numeral 100 is a pulse synchronized with the data sampling signal, and is a timing signal input that provides the timing for updating internal status registers 1, 2, input register 3, and output register 4 as well as the timing for resetting accumulation registers 53 and 63. It is a terminal. Reference numeral 101 mainly represents the coefficients (-α ₁ ), (-
This is a terminal for inputting a signal for controlling the selection circuit 51 based on the coefficient {f _j } derived from the binary multiplication algorithm from α ₂ ). Reference number 102 is a control signal for determining addition or subtraction for the addition/subtraction circuit 52 based mainly on the coefficients {C _j } derived from the binary multiplication algorithm from the coefficients (-α ₁ ) and (-α ₂ ). This is an input terminal. Reference number 103
is a terminal for inputting a clock signal of the feedback addition/subtraction accumulator 5 and feedback addition/subtraction accumulator 6, which has a frequency (n+3) times higher than the sampling signal frequency. Reference number 104 is the selection circuit 5
4 and 64, and shifts the outputs of the (n+1) clock-to-clock accumulation registers 53 and 63 to the right while the binary multiplication is being performed, and inputs them to the addition/subtraction circuits 52 and 62, respectively. be. Reference number 111 indicates the coefficients β ₁ , β ₂
This is a terminal for inputting a signal for controlling the selection circuit 61 based on the coefficient {f _j } derived from the binary multiplication algorithm. The reference number 112 is mainly based on the coefficient {C _j } derived from the binary multiplication algorithm from β ₁ and β ₂ , and the addition/subtraction circuit 62
This is the input terminal for the control signal that determines whether to add or subtract from the input signal. Reference numerals 120 and 130 are the input terminal and output terminal of the present secondary digital filter, respectively. The detailed operation of the figure is as follows. When a signal synchronized with the sampling signal is applied to terminal 100, the contents of internal state register 1 are transferred to internal state register 2, and feedback addition/subtraction accumulator 5 is transferred.
The contents of the accumulation register 53 are transferred to the internal register 1 and become the internal states w _i-1 and w _i-2 , respectively. At the same time, the input register 3 is transferred with the data x _i appearing at the input terminal 120, and the output register 4 is transferred with the output result y _i-1 from one sampling time ago from the output of the feed forward addition/subtraction accumulator 6. .
Accumulation registers 53 and 63 are also reset. After this, for (n+1) clocks, the feedback addition/subtraction accumulator 5 and the feedback addition/subtraction accumulator 6 receive −α ₁ w _i-1 −α _{2 from the internal state registers w i-1 and} w _{i- 2,} respectively. Calculate w _i-2 and β ₁ w _i-1 + β ₂ w _i-2 by the binomial multiplication method. In other words, for the feedback addition/subtraction accumulator 5, (-α ₁ ) and (-α
The control signals corresponding to {f _j }, {C _j } derived from ₂ ) are input, and the selection circuit 54 shifts the contents of the accumulation register 53 to the right according to the signal from the terminal 104, and then outputs the contents of the accumulation register 53 to the addition/subtraction circuit 52. between (N+1) clocks, −α ₁ w _i-1 −α ₂ w _i-2
is calculated in the accumulation register 53. Furthermore, control signals corresponding to the {f _j }{C _j } derived from β ₁ and β ₂ are inputted from terminals 111 and 112 to the feed forward addition/subtraction accumulator, and the selection circuit 64 is also applied to the addition/subtraction circuit 62 in the form of right-shifting the contents of the accumulation register 63 by the signal from the terminal 104, so that (n
+1) β ₁ w _i-1 +β ₂ w _i-2 is calculated in the accumulation register 63 between clocks. When the next clock is applied to terminal 103, selection circuit 51 in feedback addition/subtraction accumulator 5 selects the contents of input register 3 by control signal 101, and selection circuit 54 selects the contents of input register 53 by control signal 104. The contents are input as they are to the addition/subtraction circuit 52, and the addition/subtraction circuit 52 receives the control signal 1.
02, x _i +(−α ₁ w _i-1 −α ₂ w _i-2 )=w _i is calculated as the output of the addition/subtraction circuit 52. During this time, the selection circuit 61 selects 0 in the feed forward addition/subtraction accumulator 6, and the selection circuit 64 transmits the output of the accumulation register 63 directly to the addition/subtraction circuit 62 by the control signal applied to the terminal 104. Since the addition/subtraction circuit 62 is controlled, the contents of the accumulation register β ₁ w _i-1 +β ₂ w _i-2 are output as they are. When the next clock is applied to terminal 103, in the feedback addition/subtraction accumulator 5, the accumulation register stores w _i , the selection circuit 51 selects 0, and the selection circuit 54 selects the control signal applied to terminal 104. Since the output of the accumulation register 53 is controlled to be directly transmitted to the addition/subtraction circuit 52, the contents w _i of the accumulation register are output as they are to the output of the addition/subtraction circuit 52. At this time, in the feedback addition/subtraction accumulator 6, the selection circuit 61 selects the output of the feedback addition/subtraction accumulator 5, and the selection circuit 64 selects the output of the feedback addition/subtraction accumulator 63.
Since the contents of are inputted as they are to the addition/subtraction circuit 62, the output of the addition/subtraction circuit 62 is calculated as w _i +β ₁ w _i-1 +β ₂ w _i-2 =y _i . Next, when a signal synchronized with the sampling signal is applied to the terminal 100, the w _{i and} y _i are transferred to the internal register 1 and the output register 4, respectively. As described above, the configuration shown in the figure is expressed by equation (1) (n+
3) It can be seen that it functions as a digital filter with T' as the sampling period T. As explained above, according to the present invention, by simply providing the accumulator with a subtraction function and adding a selection circuit to the accumulator input, it is possible to replace the conventional four multiplication accumulator circuits with approximately equivalent circuit scale. The secondary digital filter that used to be used can be constructed with two improved addition/subtraction accumulators without sacrificing processing speed, and the circuit scale can be significantly reduced. Furthermore, since the structures of the feedback addition/subtraction accumulator and the feedback addition/subtraction accumulator are exactly the same, it is easy to standardize the necessary functional elements when combining secondary digital filters to create a high-order digital filter. ,
Suitable for VLSI. Furthermore, since the structures of the feedback addition/subtraction accumulator and the feedback addition/subtraction accumulator are exactly the same, it is also possible to time-division multiplex them and configure a secondary digital filter with one addition/subtraction accumulator. It is part of the present invention.

[Brief explanation of the drawing]

The figure is a block diagram showing one embodiment of the present invention.
1 and 2 are internal status registers, 3 is an input register, 4 is an output register, 5 is a feedback addition/subtraction accumulator, and 6 is a feedback addition/subtraction accumulator. Accumulation registers 53, 63, selection circuits 51, 61, 5
4,64.

Claims (1)

[Claims] 1 an input register for storing input data; 2
An internal state register that stores internal variables up to the sample time, and the contents of the internal state register, the contents of the input register, and zero are added or subtracted as specified by coefficients calculated by two circulating section filter coefficients. It has a means for inputting it and a means for inputting either the cumulative result directly or shifted to the right (multiplyed by 2 ^-1 ) as an addendum/subtractor input, and according to other coefficients calculated from the two circulation part filter coefficients. a feedback addition/subtraction accumulator designated for addition/subtraction; means for supplying the output of the feedback addition/subtraction accumulator to the internal state register; and any one of the contents of the internal state register, the feedback addition/subtraction cumulative output, and zero. is specified by the coefficient calculated by the two acyclic part filter coefficients as the addition/subtraction input, and either the accumulation result directly or shifted to the right (multiplyed by 2 ^-1 ) is used as the addition/subtraction input. a feedforward addition/subtraction accumulator whose addition/subtraction is designated by another coefficient calculated by said two acyclic part filter coefficients, and said feedforward addition/subtraction accumulator connected to said feedforward addition/subtraction accumulator output; 1. A secondary digital filter comprising an output register and requiring four multiplications, which is realized by two addition/subtraction accumulators without using time division multiplexing.