JPS6129168B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a configuration circuit of a digital filter. Even if the digital filter is a high-order one, it is usually constructed of a second-order digital filter due to the problem of coefficient accuracy.Secondary digital filters include those that have only second-order poles, those that have only second-order zero points, etc.
Or, if it is realized as a combination of both, where the input is {x ₁ }, the internal variable is {w ₁ }, and the output is {y ₁ },

[Table] It can be expressed as a mathematical formula. Conventionally, when configuring such a digital filter, configuring the multiplication circuit with parallel multipliers would result in too large a circuit scale, so the multiplication circuit used an accumulation algorithm using the so-called "addition and shift multiplication algorithm." When using up to a high frequency range or when a high degree of multiplicity is required, a method is used in which one accumulator is used for one multiplication appearing in equation (1). Ta. The accumulator referred to here is, as is generally said, the input for addition is the result from one time ago, either directly or right-shifted (multiplyed by 2 ^-1 ), and the augend input corresponds to the multiplicand. It consists of an adder that inputs a numerical value or zero. The minimum sampling period (Nyquist period) T of a secondary digital filter having such a structure is the maximum operating period of the accumulator T', the coefficient bit length (the above α
₁ , α ₂ , β ₁ , β ₂ ) as n, then for multiplication
nT' is necessary, and since addition and subtraction shown in each of the above equations (1) are also required, T≧nT' (2). The equality is established when an addition/subtraction circuit is used in addition to the accumulator. If the coefficient bit pattern is special, it is possible to further shorten the minimum sampling period, but at the digital filter design stage, we cannot expect effects that depend on the coefficient bit pattern, so Equation (2) This can be considered a limitation of the method. In other words, according to the conventional method, two accumulators are required for each of equations (1), and four biquad digital filters with two poles and two zeros are required, and the sampling period is also as shown in equation (2). was the limit. The purpose of the present invention is to add subtraction to the function of the accumulator and to improve the wiring of internal registers, etc., so as to realize a high-speed two-pole, two-zero, or The object of the present invention is to construct a digital filter having two poles and two zero points. The structure of the digital filter according to the first invention is such that a register for holding input/output data, a register for storing internal variables w _i-1 and w _i-2 , and any one of the above registers are selected, and an addition/subtraction accumulator is input. It consists of a circuit for , an addition/subtraction accumulator, and a circuit for connecting either the output of the addition/subtraction accumulator or the input register to an internal variable storage register. The principle of the present invention is to use the binomial multiplication method and to take advantage of the similarity of each equation in equation (1). The binomial multiplication method consists of variables x ₁ , x ₂ , coefficients A ₁ , A ₂
(for a fixed coefficient), P=A ₁ x ₁ + A ₂ x ₂ (3) This is a method of processing by accumulating approximately the coefficient bit length. now, Then, equation (3) can be transformed as follows. Here, f _j ∈{0,1} c _j ∈{1,0,−1} indicates logical negation. The expansion method from equation (4) to equation (5) will be described later.
To obtain equation (5) in cumulative form, it is best to follow the recurrence formula shown in the following equation.

[Table] It can be easily proven that equation (6) becomes equation (5) by sequentially substituting equation (6C) into the right-hand side of equation (6B). Equation (6C) can be further expanded as follows depending on the values of C _j and f _j .

[Table] According to this formula, the shift of the sum of partial products P _j-1 (2 ^-1 )
It can be seen that a new sum of partial products can be found by adding or subtracting x ₁ or x ₂ once, and P _o is found at the (n+1)th time counting from P _p . In other words, the binomial sum of products can be calculated by (n+1)T by using an accumulator to calculate P _j with subtraction added each time to obtain P _j from P _j-1 . ’ is processed. Therefore, it is possible to perform a binomial product sum in the same processing time as a single multiplication. There are a few ways to determine {f _j } and {C _j } necessary for formulas (4) to (5), but the most efficient method (that is, the method of determining the bits of {f _j }, {C _j }) is possible. The encoding method (length is n+1) is shown below. {C _j }{f _j } can be constructed by performing the following steps. However, from the bit position determined in the first step 1
If both coefficients up to the LSB are 0, both LSBs are expanded by 1 bit, and different values (one is 0 and the other is 1) are entered into the new LSB. Step 1, both coefficients (A ₁ , A ₂ ) from the LSB side
Examine the MSB side and detect the bit position (p) that becomes 1 at the same time. Step 2: Check both coefficients from bit position p to the LSB side, and find the bit position (q) where it becomes 1 first.
For A _k (k=0,1) with a ^k _q to a ^k _p-1
is set to -1, a ^k _p is set to 0, and the p+1th bit of A _k is arithmetic +1. Step 3: Repeat steps 1 and 2 until MSB and convert {a ¹ _j }, {a ² _j } into three-value coefficient {α ¹
_j },
Convert to {α ² _j }. Step 4: Define {f _j } as {f _j |f _j =|α ¹ _j |}. Here |·| indicates an absolute value. {C _j } is defined as {C _j |C _j =α ² _j 〓α ² _j }.
Here, 〓 is assumed to be diadic addition. The above construction method also proves that it is possible to expand the two coefficients A ₁ and A ₂ into {C _j } and {f _j }, and it is also possible to expand the two coefficients A 1 and A 2 into {C j } and {f j }. May be extended to the MSB side.
Therefore, it is sufficient to consider the length of n+1 bits for {f _j } and {C _j }. As an example, the means for obtaining {f _j } and {c _j } in the case of A ₁ =11011010 ₂ and A ₂ =10111001 ₂ will be described. First, in step 1, A ₁ and A ₂ are converted to LSB
If the test is started from the LSB side simultaneously, the fourth bit from the LSB side becomes 1 at the same time, and P=4 is obtained. From the 4th bit towards the LSB side by step 2
If you start testing A ₁ and A ₂ at the same time, the LSB of the coefficient of A ₁
There is a 1 in the second bit from the side. For this reason, q=
2, and set the second to third bits to -1 for _A1 , and set the fourth bit to 0,
Furthermore, 1 is arithmetically added to the 5th bit. In other words, A ₁ becomes as follows.

[Table] _---
11100110
In this case, it can be easily verified that both 11011010 ₂ and 11100110 ₂ indicate 218. Step 3 means repeating Steps 1 and 2 to eliminate bits with overlapping non-zero elements from LSB to MSB. New _A1 expression and
Returning to step 1 using A ₂ , in this case p
=6. Move to step 2, LSB from p=6
When searching to the side, q=5, and A ₂ will be changed. As a result, A ₂ = _110110012 .
If step 1 is repeated for A ₁ = _111001102 and _A2 = _110110012 , p=7. In step 2, q=6 and changes are made to _A1 . As a result, A ₁ = _1001001102 . A ₁ and A ₂ were initially displayed as 8 digits, but after this process, they are now 9 digits. When both A ₁ and A ₂ are displayed in 9 digits, A ₁ = 100100110 ₂ A ₂ = 011011001 ₂ , and non-zero does not appear in both A ₁ and A ₂ in the same digit. Step 3 is executed as described above, and {α ¹ _j }={100100110} {α ² _j }={011011001}. {f _j } and {c _j } to be found in step 4 are determined from {α ¹ _j } and {α ² _j } as follows. {f _j }={100100110} {c _j }={111111111} In other words, even if A ₁ and A ₂ are expressed as {α ¹ _j } and {α ² _j }, the values of A ₁ and A ₂ are If it is unchanged and α ⁱ _j is zero, α ⁱ _j X _i is zero and there is no need to calculate the product in equation (5). When one coefficient is non-zero, the other is always zero, so 9 times (n+1
binomial product sum can be performed by adding partial products (times), and A ₁ X ₁
{f _j } indicates which of the partial products generated from and A ₂ X ₂ is used. In other words, if f _j = 1, _the A ₁ X ₁ side is selected; if f _i = 0, _{the A 2} It will be understood that -1 indicates subtraction of partial products, and C _j =0 indicates no addition or subtraction. From the above, the dyadic multiplication method was understood. Next, we will show the similarities and problems of each equation in equation (1) that describes the digital filter. Equation (1) is rewritten as follows to show that the binomial multiplication method is applicable.

[Table] In Equation (8), the binary multiplication method can be used in each parenthesis, and the variables are internal variables w _i-1 and w _i-2
It is. On the other hand, the terms other than the binary multiplication method are w _i and x _i respectively, and w _i becomes an internal variable at the next sample time, whereas x _i is not an internal variable directly at the next sample time. , the operation result becomes an internal variable. In other words, in a digital filter, internal variable settings are different between a digital filter having a pole and a digital filter having a zero point. Therefore, means is required to select either the accumulator output or the input register depending on whether the internal variable input stage is a digital filter having a pole or not. Other structures may be the same. According to the above configuration, the (n+1)T' time is required for the binary multiplication, and the T' time is required to add w _i or x _i . Even though it is a digital filter, the processing time is only (n+2)T', and when realizing a filter with only poles or only zeros, the processing time is almost the same as that of the conventional method (see equation (2)). In addition, the structure can be easily changed depending on the characteristics of the digital filter (whether it has a pole or a zero point). Furthermore, a biquad digital filter having two poles and two zero points can also be realized by time-division multiplexing the arithmetic section. An embodiment of the invention is shown in FIG. FIG. 1 shows an addition/subtraction accumulator 10 composed of an accumulation register 1, an addition/subtraction circuit 2, and a shift circuit 3, a first internal register 4, a second internal register 5, an O register 6, an input register 7, and an output register. 8 and a selection circuit 9. Terminal 11 is a clock signal input terminal, terminal 1
2 is an input terminal for a signal synchronized with the sampling time, and terminal 13 is for a control signal {C
_Terminal 14 is a terminal that adds a signal according to the control signal {f _j } mainly by the dyadic multiplication method. Terminal 15 requests a shift from the shift circuit 3 during execution of the dyadic multiplication. The terminal to which the signal is applied, terminal 16, is connected to the output of the accumulation register 1 and to the input register 7, depending on whether this circuit is implementing a digital filter with a pole or not.
This is a control signal terminal for selecting one of the outputs. Terminal 17 is an input data terminal, and terminal 18 is an output data terminal. The detailed explanation of FIG.
A case will be described in which the selection circuit 9 always adds the output of the accumulation register 1 to the first internal register 4 due to the DC signal applied to the DC signal, and the lower equation of equation (8) is realized. When a signal synchronized with the sampling signal is applied to the terminal 12, the contents of the accumulation register 1 are transferred to the first internal register 4 and the output register 8, and the contents of the first internal register 4 are transferred to the second internal register 5. The input data that has reached the terminal 17 is transferred to the input register 7. Also, the contents of the accumulation register are cleared. As a result, assume that w _i-1 is transferred to the first internal register 4, w _i-2 is transferred to the second internal register 5, x _i is transferred to the input register 7, and w _i-1 is transferred to the output register. explain. After this, for (n+1) clocks, the addition/subtraction accumulator 1
0, O register 6, first and second internal registers 4 and 5, the binary multiplication −α ₁ w _i-1 −αw _i-
2 is executed. In other words, at clock j, the accumulation register 1 works to shift equation (6) Pj, and the shift circuit 3 works to shift P _j of the accumulation register 1 during this period, and outputs P _j ×2 ^-1 to the addendum and subtraction terminal of the addition/subtraction circuit 13. In 13, addition/subtraction is determined by a control signal based on {C _j } derived from (−α ₁ , −α ₂ ), and terminal 1
4 has {f _j } derived from (−α ₁ , −α ₂ )
and C _j =0, w _{i-1 of the first internal register 4, w i-} 1 of the second
In order to select either w _i-2 of internal register 5 or zero content of O register, at the next clock, P _j+1 corresponding to equation (7) is stored in accumulation register 1, and the clock At n, the accumulation register 1 calculates P=P _o =-α ₁ w _i-1 −α ₂ w _i-2 (9). Before the next clock is applied to terminal 11, a control signal applied to terminal 15 instructs shift circuit 3 to transmit the contents of accumulation register 1 directly to addition/subtraction circuit 2 without shifting; A control signal 13 applied to terminal 1 specifies the addition and
A control signal applied to 4 selects input register 7. Therefore, the output of the addition/subtraction circuit 2 is x _i −α
₁ w _i-1 −α ₂ w _i-2 =w _i is calculated, and this result is stored in the accumulation register 1 in synchronization with the next clock. Next, when a signal synchronized with the sampling signal is input from the terminal 12, the process returns to the beginning and a new w _i-
The operation is repeated for ₁ , w _i-2 , and x _i . The digital filter corresponding to the lower equation of equation (8) has been described above, but when configuring a digital filter with zero points, the contents of the input register 7 are sent to the selection circuit 9 by the DC signal applied to the terminal 16. It will be easily understood that the information may be transmitted to the internal register 4 of No. 1. It is also clear that a biquad filter with two poles and two zeros can be realized as shown in Figure 1 by combining the operations of the filter with two poles and the filter with two zeros mentioned above within one sampling period. Probably. As we have seen above, if the configuration shown in Figure 1 is followed, only the digital filter having a second-order pole or a digital filter having a second-order zero point will be handled independently, and the squaring required for this will be reduced to 1. By using an addition/subtraction accumulator, it is possible to realize a digital filter having the same processing speed as a conventional digital filter using two accumulators. Further, the distinction between a digital filter having a secondary pole and a digital filter having a secondary zero point can be simply set by an external control signal. Furthermore, digital filters and high-order digital filters having two poles and two zero points can also be connected to a circuit having the architecture of the present invention as exemplified in the configuration shown in FIG. 1 or in the configuration described later with reference to FIG. We offer a structure suitable for converting digital filters into LSI and VLSI, which can be configured simply by combining them. In the present invention, the data transfer to the input register is multiplied by 1/2 by wiring in advance,
The present invention also doubles the transfer from the accumulation register to the output register in advance by wiring, eliminates the shift circuit, and automatically controls not to shift when adding the contents of the input register. Part of it. In addition, except for the selection circuit 9, the first internal register 4 and the input register 7 are directly connected in advance, or the first internal register 4 and the accumulation register 1 are directly connected, and a digital filter having a zero point and a digital filter having a pole are used. It is also part of the present invention to do so. By the way, in the configuration shown in Figure 1, the input/output and internal calculations of the digital filter were performed in bit parallel, but if this could be done in the bit serial format used in many communication systems, it would be possible to do so. Improves input/output coordination with external systems. Conventionally, a serial-parallel converter has been used for this purpose, but if such a serial-parallel converter is attached to the input/output terminals shown in Figure 1, the power for one word (one sample time) will be reduced. This causes a conversion delay and requires conversion hardware. In the second embodiment of the present invention, one
It is an object of the present invention to eliminate the conversion delay of word portions and to further simplify the input/output circuit than the first invention. Second
The configuration of this embodiment is mostly the same as that in FIG. 1, except that the input register and output register are one input/output shift register. In the second embodiment, (n+1) clocks are required to perform the parenthesized part of equation (8) using the binary multiplication method, but for addition of the terms (w _i or x _i ) other than the parentheses, Since only one clock is required for
The purpose is to input and output bit serial data during binary multiplication. Next, a second embodiment of the present invention is shown in FIG. In Fig. 2, reference numerals 1 to 6 and 9 to 16 are the same as in Fig. 1, reference numeral 70 is an input/output shift register, reference numeral 170 is a bit serial input terminal, and reference numeral 180 is a bit serial output terminal. Reference numeral 110 is a shift clock input terminal. A signal synchronized with the sampling signal is connected to terminal 12.
, the contents of accumulation register 1 (w _i or k _i ) are transferred to input/output shift register 70 . During (n+1) clocks, add/subtract accumulator 1
0, the first internal register 4, and the second internal register 5 are used for binary multiplication, and during this time, the contents of the input/output shift register are shifted one bit at a time by an external clock applied from the terminal 110, and
A shift out output is applied to 80, and a shift input is applied from terminal 170. After the (n+1) clock applied to the terminal 11, the contents of the input/output shift register 70 are input data (x _i or w _i ), and operations other than the binary multiplication section are performed by the addition/subtraction circuit 1.
It can be done with 0. If the data word length is (n+1) bits, terminal 11 and terminal 110 may be used in common. As we have seen above, if the second invention is followed, the advantages of the first invention can be retained, and bit-serial input/output can be performed without the need for extra hardware (rather,
With input/output registers that are simpler than the first invention)
When a digital filter is introduced into a communication system, a system with good data exchange consistency can be realized. In the second invention, the variable word length is 2 of the coefficient word length.
It is common for the amount to double, so
A system in which the terminal 11 and the terminal 110 are shared, and the shift input and shift output are each 2 bits to perform input/output at high speed is also a part of the present invention.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, in which an accumulation register 1,
An addition/subtraction accumulator 10 consisting of an addition/subtraction circuit 2, a shift circuit 3, a first internal register 4, a second internal register 5, an O register 6 holding O, an input register 7, an output register 8, and a selection circuit 9. Consisting of FIG. 2 shows a second embodiment of the invention, reference numeral 7.
0 is an input/output shift register.

Claims (1)

[Scope of Claims] 1. An addition/subtraction accumulator having a function of accumulating the accumulated result by shifting it one bit to the right, and controlling addition/subtraction by a coefficient derived from two filter coefficients; an output register connected to the output of the addition/subtraction accumulator, an input register for storing input data, and a first internal register for selectively inputting either the input register output or the output of the addition/subtraction accumulator. , a second internal register connected to the first internal register, and any one of the input register, the first internal register, and the second internal register, using the coefficients derived from the two coefficients. A digital filter comprising means for selecting as an input to an addition/subtraction accumulator. 2 the input register and the output register are
The digital filter according to claim 1, characterized in that it is constituted by one input/output shift register.