JPS6129187B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frame synchronizer that converts an input NTSC television signal to a different standard synchronization system signal, and in particular, the present invention relates to a frame synchronizer that converts an input NTSC television signal to a different standard synchronization system signal, and in particular, for V-slip genlock, the horizontal The present invention relates to a frame synchronizer with a V-slip genlock fault correction circuit for correcting faults that occur when an input television signal having a number of synchronization signals different from the normal number is input.

In order to match the vertical phase of the synchronization signal generator with the vertical phase of other target synchronization signals, the V slip genlock normally adjusts the number of horizontal synchronization signals from the 10th H to the 21st H of the vertical blanking period, for example. The phase is adjusted by continuously thinning out one field at a time for each field. When a television video signal subjected to V-slip genlock is supplied to a frame synchronizer, a problem occurs because the number of horizontal synchronization signals is different from the normal number. This failure will be explained below along with a description of the frame synchronizer.

Figure 1 is a system diagram of a conventional frame synchronizer. Different types of synchronized input television image signals are input to video signal input terminal 1, and frequency components of 5.35 MHz or higher in the input signal are band-limited by input side low-pass filter 2. After that, it is sampled at a frequency of 10.7MHz by an analog-to-digital (A/D) converter 4 and converted into PCM parallel n (=8) bit data 5. Further, a write clock pulse 12 synchronized with the color burst of the input signal is generated by a write clock generator 11, and a write address signal 14 synchronized with the synchronization signal of the input signal is generated by a write address generator 13. and parallel n
The information for one field period of bit data 5 is approximately
Each data is written to an elastic digital memory 6 having a capacity of 1.5 megabits at a location determined by a write address signal 14.

On the other hand, a read clock pulse 12' synchronized with the color burst of the read timing reference signal (color black signal) 19 is applied to the read clock generator 1.
A read address signal 14' generated by the read timing reference signal 1' and synchronized with the synchronization signal of the read timing reference signal 19 is generated by the read address generator 13'. Then, the PCM data in the memory 6 is read out using these read address signals and the read clock, and converted into a PAM signal by the D/A converter 8. The output side low-pass filter 2' removes spurious signals of 5.35 MHz or more, and the data is read out. A television signal 10 synchronized to the timing reference signal, ie synchronously converted, is obtained.

Now, in the write address generator 13, a horizontal synchronizing (H) pulse 21 is generated from the input signal 1 by an H pulse separator 20, and a vertical base (V) pulse 25 is generated.
is produced by the V-pulse separator 24. From the H pulse 21 and the write clock pulse 12, an H address counter 22 generates an H address signal 23 that alternates from 0 to 227 or from 0 to 226 every H.

Further, the V address counter 26 generates a V address signal 27 of 0 to 262 or 0 to 261 based on the V pulse 25 and the H pulse 21. The H address signal 23 and the V address signal 27 are mixed by a horizontal/vertical (H/V) address mixer 28 to produce a write address signal 14.

Here, the H address signal 23 is 0 to 227 (or 0
~226) means that the H address counter 22 counts 228 (or 227) subcarriers with a frequency of 3.58 MHz during one scanning line period. Also, the V address signal 27 is 0 to 262
(or 0 to 261) means that the V address
Counter 26 scans 263 scanning lines in one field period.
This means that you are counting books (or 262 books).
As an example, consider the frame synchronizer H address for an NTSC color television input signal.
The operation sequence of the counter 22 and the V address counter 26 is shown in FIG.

Furthermore, every H pulse 2 separated from input signal 1
If the phase of 1 is represented by a vertical solid line, and the H address counter 22's every H clear phase and subcarrier waveform are shown by black dots and a sine wave mark (ⓓ), the result will be as shown in FIG. When the video signal input 1 is a regular NTSC signal, the number of scanning lines of each field and the number of H subcarriers specified in the operation sequence of FIG. is written to memory 6. Of course, the read timing reference input signal 19 is always
Since it is an NTSC synchronization signal, H address counter 22' and V address counter 2 on the reading side
The operation sequence of 6' is the same as in FIG. If the phase of every H pulse 21' separated from the read timing reference input signal 19 is represented by the same vertical solid line, the every H clear phase of the H address counter 22' is indicated by the circle mark (〓 ).

Figure 3 is a diagram for explaining the write and read sequence operations, where A is a normal NTSC signal input, B is an input signal with one less horizontal scanning line (per field). Further, C shows the case where an input signal with two fewer horizontal scanning lines is input. Video signal input 1 is normal
In the case of an NTSC signal, as shown in Figure 3A,
Writing side H clear phase (focus mark) and H pulse 21
The relative phase relationship between the reading side H clear phase (circle mark) and the phase of the H pulse 21' completely matches the relative phase relationship between the reading side H clear phase (circle mark) and the phase of the H pulse 21'. However, the synchronization signal generator related to the input television signal is in V-slip genlock with other synchronization signals, and the number of horizontal synchronization signals in one field is increased or decreased by an odd number from the normal number. In this case, the following problems occur. For example, if the number is one less than the normal number, as shown in FIG. 3B, the H pulses 21, 2
1' phase (vertical solid line), H clear phase (circle mark) when reading #2 and #4 fields,
During writing, the H clear phases (black dots) no longer match. Therefore, when viewing the image of the video signal output 10 within these field periods on a color monitor,
A problem occurs in which the normal information phase fluctuates by ±140ns every 1H.

During the V-slip genlock, the number of horizontal synchronizing signals from the 10th H to the 21st H of the normal vertical blanking period can be continuously thinned out, for example, by one for each field, so that the phase of the V pulse of the synchronizing signal generator is This failure may continue until it catches up with the phase of the V pulse of the other desired synchronization signal, and it may take several seconds to recover. It is clear from FIG. 3C, which shows, as an example, the case where there are two fewer wires than the normal number that the above-mentioned trouble does not occur if the number is increased or decreased by an even number from the normal number.

As explained above, when the synchronization signal generator of the input television signal is V-slip genlocked to another synchronization signal, the number of horizontal synchronization signals in one field is different from the normal number, and the number of odd-numbered In the case of increase/decrease by ±, in conventional frame synchronization, each scanning line has an increase/decrease of ±
There was a drawback that a disturbance occurred that fluctuated by 140 ns.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a frame synchronizer with a V-slip genlock fault correction circuit which eliminates the above-mentioned faults.

According to the present invention, in order to solve the above-mentioned drawbacks of the conventional frame synchronizer, a signal in a V flip genlock state in which horizontal scanning lines increase or decrease by an odd number in an input television signal is detected. A frame synchronizer with a V-slip genlock fault correction circuit is obtained, which is equipped with a V-slip genlock fault correction circuit that corrects the fault according to the result.

That is, there is a circuit for detecting on the writing side whether or not the number of horizontal synchronization signals in one field of the input television signal is different from the normal number by an odd number, and a circuit for correcting the above-mentioned failure in synchronization with the read timing reference signal. It consists of a circuit that writes the detection signal to be used into the elastic memory, a circuit that reads the detection signal from the signal read out from the elastic memory, and a circuit that corrects the above-mentioned failure using the read detection signal. This is a conventional frame synchronizer equipped with a V slip genlock failure correction circuit.

Next, the present invention will be explained in detail with reference to the drawings. FIG. 4 is a diagram showing the principle of detecting a V-slip genlock state that increases or decreases by an odd number. FIG. 5 is a system diagram of an embodiment of the present invention.

The vertical blanking period waveform of the video signal input 1 near the V clear phase of the # field defined in FIG. 2 is shown in FIG. 4 A-a, and below it is the V address 27 corresponding to A-a. Figure 4 A-b
Shown below. Similarly, FIG. 4B shows the waveform and the change in the V address signal 27 during the vertical blanking period in the video signal input 1 of the #2 field. Fourth
It is a diagram showing addresses of #3 and #4 fields similarly to Figures C and D.

Fields #1 and #2 (or #3 and #4) can be distinguished from each other because the phase relationship between the H pulse 21 and the V pulse 25 is 1/2 different. Therefore, for example, the V clear phase of the V address signal 27 of the #1 (or #3) field is set to the video signal input 1 as shown in FIG.
The V pulse 25 phase separated from _P1 is set to have a phase delayed by 4H. In addition, the V clear phase of the V address signal 27 of the #2 (or #4) field is
As shown in Figure 4 B-b, V pulse 25 phase P ₂
The phase is set to be delayed by 4.5H. In the case of this embodiment, the phases P ₁ and P ₂ are each 1H after the start of the vertical synchronization signal.

When the video signal input 1 is a regular NTSC signal, the phase of the V pulse 25 is as shown in FIG.
As shown in normal N shown in c, C-c, D-c, #1 to #4 fields are always V address signal 2.
It exists at 258 (even number) of 7. However, if the number of H pulses 21 in one field is one less than the normal one, the address 257 of the V address signal 27 for both fields #1 to #4
Move to (odd number). These are Figure 4A
-c, B-c, C-c, D-c are shown as ±1H. As is clear from FIG. 4, it is determined whether the address of the V address signal 27 in the phase of the V pulse 25 is an odd number or an even number, and if the address is an odd number, the V slip is increased or decreased by an odd number compared to the normal address. It is possible to detect that the engine is in a locked state.

Using the above detection principle, the V-slip detector 29
Detection is performed at For this detection, V pulse 25
It is only necessary to judge the state of the minimum bit of the address signal 27 when this occurs. When such a V-slip condition is detected by the V-slip detector 29,
The start phase of each field 4H or 4.5H apart, that is, the first address of the V address signal 27
Next, a logic level "high" V-slip flag pulse 32 is written into the memory 6 as a detection mark.
The V-slip flag pulse 32 is the flag generator 3.
Made with 1. On the other hand, as shown in Figure 4 A-a and B-a, video signal input 1 at the first phase of V address 27 is during the vertical blanking period.
The most weighted bit (MSB) of the PCM parallel data 5 output from the A/D converter 4
Significant Bit) is at logic level "low". Therefore, when the V slip flag pulse 32 is generated, the logic level "low" MSB of the PCM data 5 is changed to the V flip flag adder 33.
Then, the V-slip flag pulse 32 is replaced with a logic level "high" V-slip flag pulse 32 and written into the memory 6. Therefore, it can be determined from the state of the MSB of the first address of the V address signal 27 whether or not the number of horizontal synchronization signals is different by an odd number.

On the other hand, if the logic level of the MSB of the PCM data 7 read out by the read address signal 14' is determined using the first address of the read V address signal 27', if the number of scanning lines differs by an odd number, the V slip Flag 32' can be read. This determination is made by the V slip flag detector 45.

In the odd-numbered V-slip genlock state, as shown in Figure 3B, ±
Although there is a difference of 140 ns, the hue (MUE) does not change because the memory control sequence is performed in subcarrier cycles on both the writing and reading sides as shown in FIGS. 2 and 3. Furthermore, since the steepness of the hue change and the chroma level of a normal video signal are not so high, it is sufficient to correct only the luminance signal Y by ±140 ns out of the read PCM data 7 that fluctuated by ±140 ns with respect to the normal information position. . Therefore, the PCM data 7 is separated into a luminance signal 35Y and a chroma signal 43C by a luminance signal/chroma signal separator 34. When the V slip flag detector 45 detects the V slip flag 32', the third
The luminance signals 35 of #2 field and #4 field in Figure B are output by switch 4 in phase modulator 41 for ±140ns.
0 position (-140ns), (+140ns),...
Switch like this. This switching is performed by a switching control signal 47 from the V slip correction controller 46. Therefore, the luminance signal 35 which fluctuated by ±140 ns becomes ±140 ns at the output point of the phase modulator 41.
The 140 ns variation becomes the canceled luminance signal 42. Next, the luminance signal 42 and chroma signal 43 whose fluctuations have been corrected are sent back to the luminance signal/chroma signal mixer 4.
After being mixed in step 4, it passes through a D/A converter 8 and a low-pass filter 2' to become a fluctuation-corrected video signal output 10.

In the embodiment shown in Fig. 5, correction of ±140 ns was performed only on the luminance signal, but if the image information is static information, a more complete image can be obtained by correcting the color signal as well. .

As described above, according to the present invention, it has become possible to convert a television signal in V-slip genlock, which has been considered difficult in the past, to a signal of a different standard synchronization system without any trouble. In addition, ± in Figure 5
It is clear that the same effect can be obtained even if the 140 ns phase modulator 41 is subjected to analog processing at a stage subsequent to the D/A converter 8.

[Brief explanation of the drawing]

Figure 1 is a system diagram of a conventional frame synchronizer, Figure 2 is a diagram showing the operation sequence of the frame synchronizer when the input signal is an NTSC color television system signal, and Figure 3 is a diagram showing write and read operations. Fig. 4 is a diagram for explaining the principle of detecting odd-numbered V-slip genlock states; FIG. 2 is a configuration diagram showing an example. In the figure, 1... input video signal, 2, 2'... low pass filter, 3... low pass filter output, 4...
Analog-digital converter, 5...Writing
PCM data, 6...memory, 7...read out
PCM data, 8...Digital analog converter, 9...D/A conversion output, 10...Output video signal, 1
1...Write clock generator, 12...Write clock pulse, 13...Write address generator,
14...Write address signal, 15...Write.
Read control circuit, 16...Write/read control signal, 17...Memory address selection circuit, 18...Address signal, 19...Read timing reference signal, 20...Horizontal synchronization pulse separation circuit, 21...Horizontal synchronization pulse, 32...Horizontal address counter, 23
...Horizontal address signal, 24...Vertical sync pulse separation circuit, 25...Vertical sync pulse, 26...Vertical address counter, 27...Vertical address signal, 28...Horizontal/vertical address mixer, 11'...Read clock generator, 12'... Read clock, 13'...Read address generator, 14'...Read address signal, 20'Horizontal synchronizing pulse separation circuit, 21'...
Horizontal synchronization pulse, 22'...Horizontal address counter, 23'Horizontal address signal, 24'...Vertical synchronization pulse separation circuit, 25'Vertical synchronization pulse, 26'...Vertical address counter, 27'...Vertical address signal, 28'...Horizontal Vertical address mixer, 29...V
slip detection circuit, 30...V slip detection signal,
31...V slip flag generator, 32, 32'...
V slip flag pulse, 33... V slip flag pulse adder, 34... Luminance/chromaticity separator, 35
...Brightness signal, 36...140ns delay circuit, 37...
280ns delay circuit, 38...140ns delayed luminance signal,
39...280ns delayed luminance signal, 40...switch circuit, 41...±140ns phase modulator, 42...modulated luminance signal, 43...chromaticity signal, 44...luminance/chromaticity synthesizer, 45...V slip flag detection Vessel, 46...
V slip correction controller, 47...switching control signal.

Claims (1)

[Claims] 1. In a frame synchronizer that converts an input television signal into a digital signal and writes it into a memory, reads data from the memory at a timing independent of the synchronization of the input television signal, and converts the read output into an analog signal and outputs it. , first detection means for detecting that the number of horizontal synchronization signals in one field of the input television signal is increased or decreased by an odd number from the normal number; means for writing into the memory; second detecting means for detecting the detection result on the reading side; and when the second detecting means detects that the horizontal synchronization signal has increased or decreased by an odd number, 1. A frame synchronizer with a V-slip genlock failure correction circuit, comprising means for phase modulating read data.