JPS6129476B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an electronic digital timer, and after setting the time of the clock after turning on the power,
This prevents the clock time from being adjusted by mistake unless the power is turned off, thereby preventing the mistake of accidentally changing the clock time when setting each timer.

Generally, the output outlet
There are timers that can be set on and off multiple times over a 24-hour period, but as the number of modes increases, it becomes necessary to use a rotary switch or line up a large number of key switches to change the mode.

For example, in Fig. 1, 1 is the timer external body, 2
are the replacement key and clear key, 3 is the time display section, 4
is a rotary switch. The rotary switch is normally in clock mode, and if necessary, it can be switched to clock correction mode or timer mode to set the clock, and when the settings are complete, it returns to clock mode. Among these, the clock correction mode is a mode that is used only once when the power is turned on, and is never used again while the power is on. In other words, electronic digital clocks use the commercial power supply frequency or the oscillation frequency of a crystal oscillator as the basic frequency, and since they rarely go out of order after being energized, there is no need to switch to correction mode, and they can be used for power outages that occasionally occur. It is used only when the power is turned off when moving the timer for some reason. However, the timer mode is a frequently used mode, and may be used twice or even three times a day. In such a case, if you are switching with the rotary switch, you may accidentally turn it too far to the clock correction mode when returning to the time mode.
You may accidentally change the time on your clock by touching the numeric keys without realizing it. Then,
Not only will the clock go awry, but the timer will also go awry, so devices that are turned on and off by timers may turn on at unexpected times, which is extremely dangerous. This kind of case can occur not only when using a rotary switch, but also when a large number of key switches are arranged side by side.

In order to prevent such erroneous adjustment of the clock time, the present invention provides a timer that does not enter the clock adjustment mode again after the time setting of the clock is completed once the power is turned on. It is something to do.

FIG. 2 is an embodiment showing the configuration of a timer according to the present invention. a is a configuration diagram of the timer, 5 is an operation section consisting of a replacement key, a clear key, a rotary switch, etc., 6 is the content input from the operation section 5,
In other words, a storage section that stores ON and OFF times, etc., a display section 3 that displays clock and timer times, and a display section 7 that counts the reference pulse HZ to create a clock and displays it on the display section 3, and displays the counting contents of the clock. This is a control unit that determines whether or not the time and the timer time in the storage unit 6 match, and outputs an output when they match. Reference numeral 8 denotes a clock correction determination circuit comprising a holding means for holding that the clock correction mode has been switched to the time correction watch mode, and a clock correction mode switching control means for controlling switching to the clock correction mode according to the contents of the holding means; The control section 7 and the clock correction determination circuit 8 are reset by the reset input RST.

b is a specific configuration diagram of the time adjustment judgment circuit; 8
0, 81 and 82 are AND circuits, 83 and 84 are inverters, and 85 and 86 are R-S flip-flops. After the power is turned on, the input of the inverter 84 changes from "0" to "1" because the capacitor C is charged from the power supply voltage V _CC through the resistor R. Therefore, the output RST of the inverter 84 changes from "1" to "0", and while the RST signal is "1", the R-
Reset the S flip-flops 85 and 86.
This RST signal also serves as a reset input for the control section 7 of a, and serves as a start signal for initializing the storage section 6 and displaying a power outage on the display section 3.

After the reset inputs of the R-S flip-flops 85 and 86 become "0", turn the rotary switch to clock correction mode, press the numeric key, and the clock correction signal ADJ and numeric signal are input to the AND circuit 80. The output signal causes the R-S flip-flop 85 to
is set, so the latch signal LAT is output. In this case, since the output of the R-S flip-flop 86 remains "0", it becomes "1" by the inverter 83 and is input to the AND circuit 82 together with the clock correction signal ADJ, so the output ADJ/IN signal becomes "1". You can adjust the clock time with . Thereafter, when the rotary switch is switched to the clock mode, the LAT signal and the clock signal CLK are input to the AND circuit 81 and the R-S flip-flop 86 is set, so that the clock correction completion signal SET is output and passed through the inverter 83 to " 0” signal is input to one side of the AND circuit 82. Therefore, even if the clock adjustment signal ADJ is input from now on, the AND circuit 82
The ADJ/IN signal is “0” and the clock time cannot be adjusted. Since the clock correction completion signal SET is not set unless the power is turned off, the clock correction mode will not be entered again while the power is on, and the clock will not be thrown out of order due to erroneous operation.

FIG. 3 shows the configuration of another embodiment of the invention.
200 in Figure 3 is the microcomputer μ
First, an overview of the functions and data processing process of the microcomputer μP will be explained with reference to FIG.

The first function is a logic operation function, which includes a logic operation unit (ALU) 201, an accumulator (ACC) 202, a temporary register (TEMP) 203, a program status flag (PS) 204, a carry flag 205, and a zero flag. 206, Two's Complement (T/
C) 207 and 4-bit A and B buses for data transfer. ALU2
01 is a logic operation unit that can perform logical product, logical sum, exclusive logical sum, and addition. T/
C207 calculates the two's complement of the data transferred to ALU201, so
ALU 201 can perform subtraction.

PS204, CF205, and ZF206 are 1-bit flip-flops that store the state of the system. PS204 is a flag that is set and reset by instructions, and CF20
5. Based on the calculation results of the ALU 201, the ZF 206 is set and reset depending on the presence or absence of a carrier, and the ZF 206 is set and reset depending on whether the calculation result of the CF 205 is positive or negative, and is used for various determinations in program execution.

ACC202 and TEMP203 are 4-bit registers, which are used to temporarily store ALU input data, calculation results, etc.

The second function is a data storage function. This function is variable memory RAM209, X register 2
34, is executed by the Y register 235.
RAM209 address is X and Y register 2
By order specified by No. 34,235,
The contents of the RAM 209 can be transferred to the ACC 202 and the like.

The third function is a program storage and execution function that stores and executes programs.

This function includes a fixed memory ROM210, a program counter PC208, a subroutine stack STACK211, and a stack pointer SP212.
Executed by The ROM 210 stores a program written in 8-bit instruction words to be executed by the system, and the PC 208, which is constituted by a binary counter, specifies the address of the ROM 210. Therefore, as the PC 208 counts up, the program stored in the ROM 210 is executed word by word.
The STACK 211 stores the contents of the PC 208 in order to specify the address to return from the subroutine when executing the subroutine of the program. SP is used to specify the first address to return to when executing a subroutine at two levels.

The fourth function is an instruction decoding function.

This function is available in instruction register IR2.
13. Instructions are executed by the programmable logic array I-PLA 214. IR21
Reference numeral 3 denotes an 8-bit register for latching the 8-bit instruction word transferred from the ROM 210 while the instruction is executed. , I-PLA214 is
It functions to convert the 8-bit instruction word transferred from the ROM 210 into a control signal, and therefore the I
- The 8-bit instruction word stored in the ROM 210 becomes various control signals in sequence by the PLA 214,
Other functional units (e.g. ALU, ACC, RAM...
etc.), and the microcomputer μP
It operates based on the program stored in the ROM 210.

The fifth function is a counter function. counter 2
15 is an 8-bit binary counter, which is set and reset by a counter flip-flop E/DFF 216. E/DFF216
When the counter 215 is enabled to count, it counts up the pulse input from the _S1 input terminal, and when it counts up to the most significant bit (MSB), the set flag SF217 is set. Therefore, the E/DFF 216 is set and reset by the command from the ROM 210, and the SF
By checking whether 217 is set, the number of pulses from the _S1 input can be counted. Furthermore, the contents of the counter 215 can be divided into the upper 4 bits and the lower 4 bits and transferred directly to the ACC 202 or the like.

The sixth is an input/output function.

The input terminals include 4-bit parallel input terminals _A0 to _A3 and 4-bit parallel input terminals _B0 to _B3 .

These two sets of parallel inputs A ₀ to A ₃ and B ₀ to _{B 3} can be selectively transferred to the ACC 202 or the like via the B bus 219 by the multiplexer MPX 218 .

The A ₀ to _{A 3} and B ₀ to _{B 3} inputs are used for inputting data. As other input terminals, S〓, S ₁
There is an input terminal. This input terminal is convenient for counting pulse signals and performing interrupt operations independently of the clock of the microcomputer μP. S = input is comparator C2
20, it is determined whether the input is high or low.

The _S1 input is connected to the counter 21 by gate G221.
It is a terminal that can be input to SF217 via synchronization circuit S222, and compared by comparator C223, and can be used in the same way as the S〓 input. S ₁ input counter 215
It can be selected by inputting the CS pin.

The RST input terminal is used for the purpose of preventing malfunction by stopping the program stored in the ROM 210 at the start (address 0) until the power to the microcomputer μP is established, such as when the power is turned on for the first time. be able to. At this time, all output terminals become L ₀ . The OSC input terminal is a terminal to which a capacitor and a resistor are connected in order to determine the oscillation frequency of the built-in oscillator 224. The operation of the microcomputer μP is executed using the oscillation frequency of this oscillator as a clock, and the operating speed (processing speed) of the microcomputer μP is determined. Further, V _SS and V _DD are power supply terminals.

Next, there are three types of output terminals.

The first output terminal is a D output terminal consisting of _D0 to _D7 . The data in RAM 209 or ACC 202 and PS 204 are latched by latch 225 to create programmable logic array PLA 226.
When the data is transferred as 5-bit data, the data (5 bits) is output as parallel 8-bit output to eight output terminals _D0 to _D7 . Therefore,
These output terminals D ₀ to D ₇ are suitable for display on a 7-segment display tube.

The second output terminal is an E output terminal consisting of E ₀ to E ₃ and can output 4-bit data in parallel from the ACC 202 or ROM 210. 22
7 is a latch.

The third output is a C output terminal consisting of C ₀ -C ₁₁ , each of which can be independently set or reset. That is, Y register 23
5 specifies which C output to set,
When an output command is issued, the corresponding C output terminal is latched by the latch 229 by the decoder 228 and output. Therefore, various loads can be controlled with this C output terminal.

Note that 230, 231, and 232 are multiplexers, and 233 is a comparator.

The microcomputer μP shown in Figure 4 above
Although the functions and data processing processes have been outlined, the present invention shows an embodiment using such a microcomputer.

Further, in FIG. 3, an example of a specific circuit configuration is shown. In the circuit, the microcomputer μ
Input terminals A ₀ , A ₁ , A ₂ , A ₃ of P200 are output terminals
C ₀ , C ₁ , and C ₂ form a key matrix.
The 10 o'clock digit, 1 o'clock digit, 10 minute digit, and 1 minute digit of the numeric keys correspond to 38, 37, 36, and 35, respectively, and the clear key corresponds to 28. In addition, the rotary switch has two circuits, CLK, ADJ,
CLK, A _ON , A _OFF , B _ON , B _OFF are each 3
It corresponds to contacts 1, 34, 30, 33, 29, and 32, and is connected to the intersection on the matrix. Diode 39, 40, 41, 42, 43, 44, 4
5 is inserted to prevent reverse current so that there is no erroneous input at each scan output when two or more of the aforementioned contacts come into contact.

Output terminals C ₀ , C ₁ , C ₂ , and C ₃ are scan outputs that sequentially repeat H _i and L ₀ , and dynamically output grids G ₁ , G ₂ , G ₃ , and G ₄ of the fluorescent display tube 3, which is a display element. is driven by.

Eight output terminals D ₀ , D ₁ , D ₂ , D ₃ , D ₄ , D ₅ , D ₆ , D ₇ are connected to the 7 segment anodes of the fluorescent display tube 3 from D ₀ to D ₆ . D ₇ is connected to the anode of the colon. Therefore, the time is displayed by the outputs from D ₀ to D ₇ and the scan outputs from C ₁ , C ₁ , C ₂ , and C ₃ .

Each output of E ₀ and E ₁ is for on/off control of output outlets A and B, and each has a base resistance of 2
0 and 25 to the bases of transistors 22 and 27. The resistors 21 and 26 are for improving the switching characteristics of the transistors 22 and 27. Further, relays 19 and 24 are connected to the collectors of the transistors, respectively, and each contact is connected to an A outlet and a B outlet, respectively. The diodes 18 and 23 are for absorbing back electromotive force.

The reference pulse is taken in from the AC of the commercial power supply via the transistor 12 to S ₀ . The resistor 9 is for limiting the base current, the diode 10 is for limiting the reverse base-emitter voltage of the transistor 12,
A resistor 11 is connected to the collector of the transistor. The clock counting section and time storage section are configured programmatically within the RAM of the microcomputer μP200.

Further, the fundamental frequency of each command operation of the microcomputer μP200 is determined by an oscillator constituted by a capacitor 16 and a resistor 17, and a reset circuit when the power is turned on is constituted by a capacitor 13, a resistor 15, and a diode 14.

As for the operation of the present invention, first, when the power is turned on and the rotary switch is set to clock correction mode, the contact 34 is closed and the signal from the output terminal _C1 is transferred to the input terminal.
Since it enters A ₀ and enters clock correction mode, press numeric keys 38, 37, 36, and 35 to output terminal C _0.
is input to input terminals A ₀ , A ₁ , A ₂ , A ₃ ,
At the same time as the clock time is set, it is also displayed on the display unit 3. Next, when the rotary switch is set to the clock mode, the microcomputer μP200 stores the clock time and also stores that the clock time has been corrected. Therefore, from now on, even if the rotary switch is switched to the clock correction mode, the microcomputer μP200 will judge the input to be invalid and will not accept the input from the numeric keys, so the clock will not go out of order.

Flowchart a in FIG. 5 shows this key input determination. b is the variable memory RAM of the microcomputer μP200, in which data for the 10 o'clock digit, 1 o'clock digit, 10 minute digit, and 1 minute digit are stored, and storage areas such as flag SET and LAT are determined. When the power is turned on, it is initialized by the program and the data area is cleared. In flowchart a, when input determination is entered, it is first determined whether an ADJ input is being performed, that is, whether the rotary switch is in the clock correction mode. Here, if ADJ input is in progress, the next flag is
It is determined whether SET is "1", but since it is cleared by initialization when the power is turned on, next if NUM is input, that is, numeric key input, the numeric flag LAT is set and numeric input is performed. Set the time accordingly and store it in RAM. Then, when the rotary switch is set to clock mode, the input judgment is not ADJ input but CLK input, and the flag LAT is "1", so
Next, set the flag clock setting completion flag SET. The input judgment routine in b is passed every time the display 3 is dynamically driven, but even if you switch to the clock correction mode again, the clock setting completion flag SET is still there, so it is ignored entirely and does not accept input from the numeric keys. . Since the flag SET will not be reset unless the power is turned off, there is no chance of accidentally setting the clock incorrectly while the power is on.

As explained in detail above, the timer of the present invention is set to clock correction mode after power is turned on, sets the clock time, and switches to clock mode. This prevents the clock time from being accidentally shifted when setting other timers. With electronic digital clocks, the time is unlikely to go out of order, and the only possibilities for the time to go wrong are human error or a power outage. Furthermore, if the basic clock goes out of order, the set time of the timer itself becomes uncertain, and there is a great risk that the power will turn on at an unexpected time. In this sense as well, the timer of the present invention is extremely effective.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a conventional timer, FIG. 2 is an embodiment showing the configuration of a timer according to the present invention, FIG. 3 is another embodiment showing the configuration of a timer according to the present invention, and FIG. 4 is a micro The configuration diagram of the computer, FIG. 5, is a flowchart showing the flow of input determination and RAM. DESCRIPTION OF SYMBOLS 1...Timer external body, 2...Number key and clear key, 3...Time display section, 4...Rotary switch, 5...Operation section, 6...Storage section, 7...Control section, 8... ...Time correction judgment circuit, μP200...
Microcomputer, 201...ALU, 20
2...ACC, 209...RAM, 210...
ROM, 213...IR, 234...X register,
235...Y register.

Claims (1)

[Claims] 1. An operating section having a number key for setting the time, a switching means for clock/clock correction/timer mode determination, and a clear key, a time display section displaying at least a four-digit number, and a time display section that displays a number of at least four digits, It consists of a storage section that stores contents, and a control section that counts reference pulse signals, displays the counted contents on the time display section, compares the counted contents with the stored contents of the storage section, and controls the output terminal. In the timer, a holding means holds that the switching means has switched to the clock mode after setting the time in the watch correction mode, and a watch correction mode switching control means controls switching to the watch correction mode according to the contents of the holding means. A timer characterized in that a time adjustment determination circuit is provided.