JPS6129593B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a color signal demodulation circuit for a PAL color television receiver.

In the PAL color television system, the color subcarrier is simultaneously modulated using two color signals, each with a predetermined modulation axis, with the modulation axis for one of the color signals reversed by 180 degrees every horizontal scanning period. A color television signal containing a color signal and a burst signal whose phase is alternately reversed by ±45 degrees every horizontal scanning period is transmitted. In other words, the state of this carrier color signal is as shown in Fig. 2. On one line, Fn=(B-Y)n+j(RY)n, on the next line, Fn+1=(B-Y) _o+1 -j( For one color signal, for example, a red color difference signal, the phase of the color carrier wave is inverted line by line, as represented by RY) _o+1 .

A conventional example will be explained using FIGS. 1 and 2. A PAL composite color television signal is supplied to a bandpass amplifier (hereinafter referred to as BPA) 1,
The carrier color signal and the burst signal are separated at BPA1. This signal is supplied as it is to the burst gate circuit 7 and one input terminal of the adder 2 and subtracter 3, and is also supplied to the drive amplifier 4 of the 1H delay line 5 which delays it by one horizontal scanning period (hereinafter referred to as 1H).
is supplied to The drive amplifier 4 amplifies the carrier color signal and supplies it to the 1H delay line 5. The output signal of this 1H delay line 5 is passed through the preamplifier 6 to the adder 2,
The signal is amplified to have the same amplitude as the carrier color signal supplied to the subtracter 3, and is supplied to the other input terminals of the adder 2 and subtracter 3. Therefore, the successive lines L ₁ ,
The color signals carried at L ₂ , L ₃ , L ₄ ... are F ₁ = (B-Y) ₁ +j (R-Y) ₁ F ₂ = (B-Y) ₂ -j (R-Y) ₂ F ₃ = (B-Y) ₃ +j (R-Y) ₃ F ₄ = (B-Y) ₄ -j (R-Y) ₄ Therefore, when line L ₂ arrives, adder 2 calculates (F ₁ + F ₂ )/2 is performed, and the subtracter 3 performs the calculation (F ₁ −F ₂ )/2,
Assuming that the color signals in adjacent lines are equal (B-
When the next line L ₃ arrives, adder 2 and subtracter 3 output the color signal (F ₂ +F ₃ )/2, (F ₂ −F _{3 )} in the same way. )/2 is performed, and color signals of (B-Y) and -j(R-Y) are obtained. That is, the first color signal from the subtracter 3, for example (R
-Y) The signal appears with phase inversion for each line.
The color signals from the adder 2 and the subtracter 3 are separately supplied to a demodulator 8 and a demodulator 9.

On the other hand, the burst signal separated by the burst circuit 7 is transmitted to the subcarrier generation circuit (hereinafter referred to as APC circuit) 1.
0 to generate a subcarrier signal phase-locked to the burst signal. This reference subcarrier signal (phase ₀ ) is supplied to the demodulator 8 as a signal with a phase of ( ₀ - π/2) via a 90° phase shifter 11, and the other demodulator 9 is supplied with a signal with a phase of (0 - π/2). The ₀ phase subcarrier signal from the APC circuit 10 and this
The _-0 phase subcarrier signal that has been phase-shifted by the 180° phase shifter 12 is transferred by the switching circuit 13.
It is switched and supplied every 1H. Therefore, the demodulators 8 and 9 receive continuous (B-Y) signals of the same polarity,
(RY) signal will be obtained.

Since this circuit assumes that the color signals on adjacent lines are equal, the above-mentioned formulas F ₁ and F ₂ must be satisfied. If this formula is not satisfied, adder 2
The output includes not only the (B-Y) color signal but also the (R-
Y) Color signal components are also generated. Conversely, subtractor 3
The output includes not only the (R-Y) color signal but also the (B-
A color signal component of Y) is also generated, which causes color errors in the color signal demodulation circuit. Such a color error occurs when the above-mentioned formulas F ₁ and F ₂ are not satisfied, that is, the gain with respect to temperature in the 1H delay circuit consisting of the drive amplifier 4, 1H delay line 5, and preamplifier 6. , when a phase fluctuation occurs. For this reason, conventional methods include building the 1H delay line 5 in a thermostatic oven to reduce deviation in delay time, and compensating for gain fluctuations of the 1H delay line 5 and drive amplifier 4 with a preamplifier 6, for example. The amplifier was constructed by selecting the operating current of the field effect transistor. However, these methods could not completely compensate for gain fluctuations and phase fluctuations.

An object of the present invention is to provide a color signal demodulation circuit that does not cause the color error by detecting the gain fluctuation and phase fluctuation of the 1H delay circuit and controlling the delay time and gain of the carrier color signal.

Hereinafter, one embodiment of the present invention will be described based on the drawings. FIG. 3 is a specific configuration diagram of a 1H delay circuit which is a main part of the present invention, and FIG. 4 is a time chart thereof. In FIG. 3, the same circuits as those in FIG. 1 are given the same numbers. First automatic gain control circuit (hereinafter referred to as
1H delay circuit 25 consisting of a drive amplifier 4, a 1H delay line 5, a preamplifier 6, and a variable delay circuit 16 (referred to as an AGC circuit) 14. Circuit operation in a state where no gain fluctuation or phase fluctuation occurs. Explain.
The carrier color signal and burst signal separated by the BPA 1 are supplied to an AGC circuit 14 and a phase detector 16, respectively. This signal A is gain controlled by the AGC circuit 14, amplified with high gain by the drive amplifier 4, and drives the 1H delay line 5. The output signal of this 1H delay line 5 is amplified by a preamplifier 6, supplied to a variable delay circuit 15 for phase control, and outputs a burst signal and a carrier color signal. The 1H delayed burst signal and the carrier color signal are supplied to the phase detector 17.

On the other hand, the phase ₀ of the subcarrier signal generated by the APC circuit 10 is inverted by the 180° phase shift circuit 12 to obtain a _-0 subcarrier signal, and this -
₀ is set to a phase of ( ₀ - 5/4π) through a 45° phase shift circuit 18, and a subcarrier signal Sc of this phase is supplied to phase detectors 16 and 17. Therefore, in the phase detector 17, as shown in FIG.
At the output of 7, a detected signal like C shown in the figure is obtained. Here, only the burst signal is shown, and the detection output of the carrier color signal is not shown. This detection signal C
is sample hold (hereinafter referred to as S&H) circuit 1
9,20. In this S&H circuit 19, the 0 potential of the detection signal C is sampled and held using a sample pulse (SAMP. Supplied as.
The variable delay circuit 15 is controlled by, for example, controlling a variable capacitance diode. As for this control operation, as the DC voltage increases, the capacitance of the variable capacitance diode decreases, the delay time becomes shorter, and the phase lags. Further, in the S&H circuit 20, the potential of E ₀ of the burst signal of the detection signal C is sampled and held using a sample pulse (SAMP.2) every 2H, and is supplied to one input terminal of the comparison circuit 22.

On the other hand, 1H supplied to the phase detector 16
The phase relationship between the input burst signal that has not passed through the delay circuit 25 and the subcarrier signal Sc is 0 every 1H.
90 degrees, so the detected signal B shown in the figure is obtained as the output of the phase detector 16. Here, too, only the burst signal is shown, and the detection output of the carrier color signal is not shown. This detected signal B is supplied to the B&H circuit 23. In this S&H circuit 23, the potential of E ₀ of the burst signal of the detection signal B is sampled and held using the sample pulse (SAMP.1), and is supplied to the comparison circuit 22. This comparator circuit 22 compares the detected voltage E ₀ of the burst signal that has not been delayed by 1H with the detected voltage E ₀ of the burst signal that has been delayed by 1H, and outputs this error voltage. Since there is no error voltage, no error voltage is generated.
In this case, the zero voltage is converted to an optimal DC voltage via the inverting DC amplifier 24, and is supplied to the AGC circuit 14 as a control voltage. The AGC circuit 14 may be controlled by controlling a pin diode, for example. As for this control operation, when the DC voltage increases, the operating resistance of the pin diode decreases and the gain increases.

Next, a case where a phase fluctuation occurs in the 1H delay circuit 25 will be explained using FIGS. 3 and 5. When the phase of the burst signal (n+2) is delayed by θ from the normal burst axis in the 1H delay circuit 25, the phase detector 17 detects the difference between the burst signal and the subcarrier signal Sc by 90 degrees.
The phase difference of .degree. is broken, and a potential of .DELTA.e (here, .DELTA.e is the detected potential corresponding to the phase shift of the burst signal by .theta.) is generated in the detected signal C. This potential of Δe is passed through the S&H circuit 19 to the inverting DC amplifier 21.
Amplify with. Therefore, the control voltage of the variable delay circuit 15 becomes lower than the optimum DC voltage of the variable delay circuit 15, and the capacitance of the variable capacitance diode of the variable delay circuit 15 increases, thereby increasing the delay time. That is, the phases of the burst signal and the carrier color signal are advanced by the above-mentioned θ and become in phase with the input signal of the regular 1H delay circuit 25. Here, a description of the case where the phase of the burst signal advances contrary to the above will be omitted, but the phase control operation is the same.

Furthermore, gain fluctuation occurs in the 1H delay circuit 25, and the 1H
A case where the burst signal (n+1) output of the delay circuit 25 decreases will be explained using FIG. 3 and FIG. 6. Input burst signal (n+
1) is detected by the phase detector 16, and the detected signal B is
Generates a potential of E ₀ . This potential E ₀ is supplied to one input terminal of the comparator circuit 22 via the S&H circuit 23 . On the other hand, the burst signal (n+1) output of the 1H delay circuit 25 is detected by the phase detector 17, and the detected signal C is E ₀ -△e (here -△e is the detected potential corresponding to the decrease in the amplitude of the burst signal. ) is generated. This potential of E ₀ −Δe is supplied to the other input terminal of the comparator circuit 22 via the S&H circuit 20 . In this comparison circuit 22, the above E ₀ and E ₀ −△e
The potentials of are compared and an error voltage of -△e is generated,
This error voltage -Δe is amplified by an inverting DC amplifier 24. Therefore, the control voltage of the AGC circuit 14 is
It becomes higher than the optimum DC voltage of the AGC circuit 14,
The operating resistance of the pin diode of the AGC circuit 14 decreases and the gain increases. That is, the amplitudes of the burst signal and the carrier color signal are increased by the amount that they have been reduced, and have the same amplitude as the input signal of the regular 1H delay circuit 25.
Here, a description of the case where the amplitude of the burst signal increases contrary to the above will be omitted, but the gain control operation is the same.

In this way, the gain generated in the 1H delay circuit 25,
Phase fluctuations can be completely compensated for by the closed circuit loop. As a result, only the (B-Y) and (R-Y) carrier color signal components are generated in the outputs of the adder circuit 2 and the subtracter circuit 3, that is, there is no crosstalk between each channel, and the demodulator 8 , 9 (B-
It is possible to demodulate the regular color difference signals of Y) and (RY).

In the above description, the phase of the subcarrier signals of the phase detectors 16 and 17 is set to ( ₀ - 5/4π), but it goes without saying that this phase may also be set to ( ₀ + π/4).

According to the present invention, in the color signal demodulation circuit of PAL color television signals,
By adding a closed circuit loop that detects and controls the gain fluctuations and phase fluctuations of the 1H delay circuit, each fluctuation can be completely compensated for. As a result, crosstalk between channels does not occur in the output of each demodulator of the carrier color signal, and (B-Y), (R-Y)
It is possible to demodulate only the color difference signal components of .

[Brief explanation of the drawing]

Figure 1 is a system diagram of an example of a conventional PAL color television signal demodulation circuit, and Figure 2 is a PAL color television signal demodulation circuit.
3 is a system diagram of an example of a 1H delay circuit according to the present invention. FIG. 4 is a vector diagram and time chart diagram for explaining the method shown in FIG. FIG. 5 is a vector diagram and time chart for explaining phase fluctuations, and FIG. 6 is a vector diagram and time chart for explaining gain fluctuations. 5...1H delay line, 6...Preamplifier, 7...Burst gate circuit, 10...Subcarrier generation circuit, 12...
180° phase shift circuit, 14... automatic gain control circuit, 15
... variable delay circuit, 16, 17... first and second phase detector, 18... 45° phase shift circuit, 19, 20,
23...Sample hold circuit, 21, 24...Inverting DC amplifier, 25...1H delay circuit.

Claims (1)

[Claims] 1 The color signal demodulation circuit of a PAL color television receiver consists of an automatic gain control circuit, a 1 horizontal period delay line, an amplifier, etc., and delays the burst signal and carrier color signal by 1 horizontal period.
a horizontal period delay circuit; a first phase detector that detects the input signal of the one horizontal period delay circuit using a subcarrier signal of the modulation axis of the burst signal; a second phase detector that detects a subcarrier signal of the axis; and a first sample that samples and holds the detected signal during the period in which the burst signal is detected by the first phase detector using sample pulses at intervals of two horizontal periods. a holding circuit; a second sample holding circuit that samples and holds the detected signal of the second phase detector using sample pulses at an interval of two horizontal periods that are one horizontal period different from the sample pulse; A color signal demodulation circuit comprising means for comparing detected voltages of sample holding circuits, detecting a difference voltage, and controlling the gain of the automatic gain control circuit using this error voltage.