JPS6130303B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an information processing system in which a central processing unit reads data from a storage device.
The present invention relates to a memory access abnormality processing method for handling an abnormality when an abnormality is detected in a memory access operation for writing.

For example, in the conventional memory access abnormality handling method, when an abnormality is detected in a memory access operation, the hardware simply re-executes the operation under the same conditions as the operation, and the re-execution is performed. However, if an abnormality is still detected, it is assumed that a permanent failure has occurred, and a high-priority interrupt request is issued, allowing the software to diagnose the failure.
It was being processed.

Also, if no abnormality is detected by the above re-execution, the first abnormality is simply caused by an intermittent, accidental, or recovery failure, and the subsequent processing is simply read. Do not collect information regarding the re-execution, or
Alternatively, even when collecting information, since there is no urgency, a method is used in which the information is held autonomously in the hardware and the information is output based on commands from maintenance personnel. Ta.

However, in these conventional methods, when information is not collected, such intermittent,
Since accidental and recovery failures become latent and failure phenomena cannot be grasped until they later manifest as permanent failures, problems remain in maintaining reliability and preventive maintenance of the system. I was getting used to it.

Furthermore, when collecting information, since the information is held autonomously by hardware, the scale of the hardware becomes large and there is a problem that it is not economically viable.

An object of the present invention is to provide a memory access abnormality processing method that makes it possible to economically and efficiently collect information regarding intermittent, accidental, and recovery failures in order to eliminate the drawbacks of the prior art described above. It's about doing.

A feature of the present invention is that if an abnormality is detected when the central processing unit accesses the memory, the re-execution function of the central processing unit is used to re-execute the memory access, and whether the re-execution is normal or not. In this case, a low-level interrupt request with a lower priority than interrupts that must be processed urgently for system management is immediately made, and the software
Its purpose is to read the access address information held by the hardware, manage the address information, count the number of occurrences, etc.

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram of the main part of an embodiment of the memory access abnormality processing method according to the present invention, and FIG. 2 is a flowchart thereof.

Here, 1 is a storage device, 2 is a data bus,
3 is a parity bit signal line, 4 is a central processing unit, 40 is its control circuit, 41 is the same arithmetic circuit, 42 is the same address bus, 43 is the same address bus buffer, and 44 is the same address decoder. ,
45 is the same address register, 46 is the same data bus buffer, 47 is the same data bus, 47a
is the parity bit signal line, 48 is the parity error detection circuit related to the abnormality detection circuit, and 49 is the parity bit signal line.
The re-execution circuit 49-1 is a flip-flop for requesting re-execution, 49-2 is a flip-flop for holding the parity error detection result, 49-3
is a flip-flop for the same low-level interrupt,
49-4 is a flip-flop for the same high level interrupt, 49-5, 49-6, 49-7, 49-
8, 49-9 is the same AND gate.

In the following, only the memory access operation in which the central processing unit 4 reads desired data from the storage device 1 will be described, but the same applies to the memory access operation in which the central processing unit 4 writes data to the storage device 1. be.

As is well known, the central processing unit 4 is connected to the storage device 1.
When data is read from the memory device 1, the data is stored in the data bus buffer 46 in a predetermined format via the data bus 2 and the parity bit signal line 3.

This data is taken into the parity error detection circuit 48 within the central processing unit 4 via its data bus 47 and parity bit signal line 47a, and its normality is checked using a parity check method.

When a parity error is detected by the parity error detection circuit 48, the parity error detection signal is
PE is a flip-flop 49- of the re-execution circuit 49.
Set to 1.

This causes its output to be the flip-flop 4
9-2 has been reset and the AND gate 49-
5 is open, it is immediately inputted to the control circuit 40 as the re-execution request signal RT.

Upon receiving this re-execution request signal RT, the control circuit 40 identifies that a parity error has occurred in the data related to the read operation currently being executed, terminates the read operation, and issues a bus cycle end signal CE. Output.

This signal resets flip-flop 49-1 and also sets flip-flop 49-2 through AND gate 49-6 to hold that a parity error has been detected (this is the processing in FIG. 2).

On the other hand, the control circuit 40 re-executes the operation in which the parity error occurred by specifying the same address without software intervention (same), and this re-execution is normal. (same).

As a result of this judgment, if the re-execution is successful (that is, if the failure was intermittent, accidental, or recovery), the parity error detection signal PE will disappear at the next memory cycle. Since AND gate 49-7 is open, flip-flop 49-3 is set by the output of flip-flop 49-2, which is still holding.

Its output immediately outputs a low-level interrupt request signal.
LI is input to the control circuit 40 (same as above), and in response, the control circuit 40 outputs a low level interrupt enable signal LA, and the flip-flop 49-3 is immediately reset (same as above).

On the other hand, the control circuit 40 that has received the low level interrupt request starts low level interrupt processing (same).

First, the memory address related to the low-level interrupt request is set in the address register 45 via the arithmetic circuit 41 and the address bus 42, and then the memory address is set by predetermined software processing for fault handling. In addition, the number of occurrences of such low-level interrupt requests is counted and recorded, and this is monitored.

If this number of occurrences reaches a predetermined number (a frequency that cannot be attributed to a mere intermittent, occasional, or restorative failure, e.g. once every day), the software will, for example, issue a normal failure indication (a so-called minor failure indication). (alarm display) and instructs maintenance personnel to perform prescribed fault diagnosis, analysis, repair, etc.

When this process is completed, the original process continues, so the flip-flop 49-2 is reset by the bus cycle end signal CE, and the re-execution circuit 49 returns to its normal state.

Next, if the re-execution is not performed normally, that is, if a permanent failure occurs, the first parity error detection signal PE has not disappeared, so the bus cycle end signal CE after the re-execution is When flip-flop 49-2 is set by In response to this, the control circuit 40 outputs a high-level interrupt enable signal HA, and the flip-flop 49-4 is immediately reset (same as above).

On the other hand, the control circuit 40 that has received the high-level interrupt request starts high-level interrupt processing (same).

As is well known, this displays a message indicating that a failure has occurred at the memory address, and performs predetermined processes such as failure diagnosis, analysis, and system switching.

For example, in a redundant electronic exchange,
The system is switched from the regular system to the standby system, and necessary measures such as diagnostic processing related to the failure are performed.

As explained above, according to the present invention, when an intermittent, accidental, or recovery failure occurs, a low-level interrupt that has a lower priority than an interrupt that must be urgently processed by the central processing unit for system management purposes. immediately make the request and notify the software;
Since the software reads out the information about the failure held by the hardware, the hardware must:
It is necessary to have only a group of registers on one side, which reduces the amount of hardware and has the effect that it can be realized economically.

Furthermore, the method of notifying interrupt software generally affects processing that requires real-time processing. According to the present invention, the problem is solved by setting the interrupt when a failure occurs to a lower priority level than the interrupt processing, which requires real-time processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the main part of an embodiment of the memory access abnormality processing method according to the present invention, and FIG. 2 is a flowchart thereof. 1... Storage device, 2... Data bus, 3... Parity bit signal line, 4... Central processing unit, 40
... Control circuit, 41 ... Arithmetic circuit, 42 ... Address bus, 43 ... Address bus buffer, 44
... Address decoder, 45 ... Address register, 46 ... Data bus buffer, 47 ... Data bus, 47a ... Parity bit signal line, 48
... Parity error detection circuit, 49 ... Re-execution circuit, 49-1 to 49-4 ... Flip-flop,
49-5 to 49-9...and gate.

Claims (1)

[Claims] 1. In the memory access abnormality processing method of the central processing unit of an information processing system, when a memory access abnormality is detected, the memory access is re-executed by the hardware, and if it is normal, it is handled urgently for system management. A memory access abnormality process characterized in that a low-level interrupt request with a lower priority than an interrupt that is required is made, and address information and the number of occurrences of the memory access abnormality are recorded by predetermined software processing. method.