JPH0584932B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an information device having an instruction retry function, and more particularly to an instruction retry control method.

(Prior Art) Conventionally, in an information processing apparatus having this type of command retry function, the following two control methods have been adopted regarding the number of successful command retries.

The first control method allows retries forever as long as the retries are successful, and the second control method counts the number of successful retries, and when a certain number of successful retries is reached, subsequent retries are allowed. will be discontinued.

(Problems to be Solved by the Invention) The first conventional control method described above is quite effective against intermittent failures, but in cases where failures occur almost permanently and in bursts, the command The disadvantage is that the overall performance is degraded due to the overhead caused by retrying, and depending on the nature of the failure, it may induce a 2-bit error and cause data corruption.

The second conventional control method described above is effective in cases where failures occur almost permanently and in bursts, but on the other hand, when failures occur intermittently, the number of successful retries may suddenly reach a constant value. In a case where the problem is old, even if the problem is an intermittent failure that can be recovered by retrying, the problem is that it cannot be recovered from now on.

Furthermore, conventional devices have a drawback in that the threshold value for the number of successful retries is fixed and cannot be easily changed.

An object of the present invention is to start time monitoring at the same time as counting the number of retries when an instruction is successfully retried in a logic device, and when the number of successful instruction retries reaches a certain value within a certain period of time, subsequent instruction retries are started. If the number of successful command retries does not reach a certain value within a certain period of time, the history of the number of successful command retries is cleared and the failure is determined to be intermittent/fixed. Eliminate defects and enable effective instruction retry even in cases where fixed and burst failures occur, or even in cases where the number of successful retries reaches a constant value after an intermittent failure occurs. The objective is to provide a control method.

(Means for solving the problem) The instruction retry control method according to the present invention includes an instruction retry control circuit, an instruction retry success detection reporting circuit,
It includes an instruction retry success detection reporting circuit, a counter means, a counter overflow detection circuit, a counter display device, a time counting circuit, a timer register, a timer register all 0 detection circuit, and a program instruction execution control circuit. It is composed of

The instruction retry control circuit is for controlling instruction retry of a logic device having an instruction retry function.

The instruction retry success detection and reporting circuit is for detecting and reporting the success of instruction retry.

The counter means can have a value set by a program instruction and is for counting executions.

The counter overflow detection circuit is for detecting that the content value of the counter means has reached a predetermined value.

The counter display circuit is for setting the validity/invalidity of the content value of the counter means by a program instruction.

The time counting circuit is for counting time intervals.

The timer register can have a value set by a program instruction, and is used to count the value by a time counting circuit.

The timer register all 0 detection circuit is for detecting that the value of the timer register has reached a predetermined value.

If the counter display circuit indicates invalid when success of the instruction retry is reported, the program instruction execution control circuit causes the counter display circuit to display valid according to the program instruction, and also controls the counter means and the timer register. A fixed value is set for each, and thereafter, the content value of the counter means is counted every time a successful command retry is reported.
This is to prohibit retry of the instruction when the content value of the counter means reaches a predetermined value, and to display invalidity on the counter display circuit when the content of the timer register reaches a predetermined value. be.

(Example) Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of an instruction retry control method according to the present invention. In FIG. 1, 12 is a logic device, 13 is a maintenance diagnosis device, 1 is an instruction retry control circuit for controlling instruction retry of the logic device 12, and 2 is an instruction retry control report from the instruction retry control circuit 1. This is an instruction retry success detection and reporting circuit for detecting the success/failure of the instruction retry of the logic device 12 outputted via the signal line 50 and reporting it to the maintenance diagnosis device 13. 3 is a program instruction execution control circuit for controlling program instructions executed by the maintenance/diagnosis device 13; When the instruction retry success detection reporting circuit 2 detects the success of the instruction retry of the logic circuit 12, the success of the instruction retry is transmitted from the instruction retry success detection reporting circuit 2 via the instruction retry success report signal line 51. It is sent to the program instruction execution control circuit 3.

7 is a counter 7 for setting a value sent out via the counter data signal line 61 in response to a program command from the program command execution control circuit 3;
9 is a counter 7 set by a program instruction.
14 is a selection circuit for incrementing the value of 1 and counting by 1. The data updated in increments of 1 by the counter counting circuit 9 is
It is set in the counter 7 via the counter update signal line 57. Reference numeral 6 denotes a counter display circuit for setting whether the contents of the counter 7 are valid or not based on a program command sent from the program command execution control circuit 3 via a counter display data signal line 59. A display data signal sent from the program instruction execution control circuit 3 to the counter display circuit 6 via the signal line 59 causes the contents of the counter display circuit 6 to be displayed as a counter display signal on the signal line 59.
Sent on 0.

8 is a counter overflow detection circuit for detecting when the value of the counter 7, which is incremented by 1 each time an instruction is successfully retried, overflows. The overflow of the counter 7 is notified to the program instruction execution control circuit 3 via the signal line 58. The program instruction execution control circuit 3 sets the time in the timer register 4 via the timer set signal line 53. The contents of timer register 4 are indicated by the timer data signal on signal line 6. 10 is a time counting circuit for updating the value of the timer register 7 by decrementing it by 1 at certain time intervals. The value counted by the time counting circuit 10 is set in the timer register 4 via the timer update signal line 55. 5 is a timer register all 0 detection circuit for detecting that the contents of the timer register 4 have become all 0.
The timer register all 0 detection circuit 5 notifies the program instruction execution control circuit 3 via the timer register all 0 detection signal line 54 that the contents of the timer register 4 have become all 0.

11 and 14 are selection circuits, respectively, which are controlled by control signals on signal lines 62 and 63, respectively. If retrying the command is not possible, signal line 5
An instruction retry prohibition signal is sent from the program instruction execution control circuit 3 to the instruction retry control circuit 1 via the program instruction retry control circuit 2.

Next, the operation of this embodiment shown in FIG. 1 will be explained in detail.

When a failure occurs in the logic device 12 and the instruction is retried by the instruction retry control circuit 1, an instruction retry report signal on the signal line 50 indicates the success or failure of the instruction retry by the instruction retry success detection circuit. 2 will be notified. When the instruction retry success detection reporting circuit 2 confirms the success of the instruction retry, the signal line 51
The program instruction execution control circuit 3 is notified of the success of the retry by the instruction retry success report signal. The program instruction execution control circuit 3 has a signal line 6
The contents of the counter display circuit 6 are read using the counter display signal above 0, and it is determined whether the contents of the counter 7 are valid or invalid.

First, it is assumed that the contents of the counter 7 are invalidated by the counter display circuit 6 when the success of the instruction retry is reported. The program instruction execution control circuit 3 performs control according to the control signal on the signal line 62 according to the program instruction, and indicates to the counter 7 that the instruction can be retried only once according to the counter data signal on the signal line 61. Instructs to store the data “1” shown. At the same time, the program instruction execution control circuit 3 uses the counter display data signal on the signal line 59 to store in the counter display circuit 6 data indicating that the contents of the counter 7 are valid. At this time, the program instruction execution control circuit 3 is operated by the control signal on the signal line 63, and
A timer value n is set in the timer register 4 using the timer set signal above 3. Thereafter, the contents of the timer register 7 are decremented by 1 and updated by the time counting circuit 10 at regular time intervals.
Therefore, the content of the timer register 7 becomes (ni) after i updates.

Next, when the success of the instruction retry is reported, it is assumed that the counter display circuit 61 has made the contents of the counter 7 valid.

The program command control circuit 3 is operated by the control signal on the signal line 62, and controls the counter counting circuit 9 to set the value incremented by 1 in the counter 7 according to the program command. When the value of the counter 7 is updated by such an operation, when an overflow of the counter 7 is detected by the counter overflow detection circuit 8, the overflow state is detected by the counter overflow signal on the signal line 58. will be notified. The program instruction execution control circuit 3 detects the overflow of the counter 7 based on the counter overflow signal, and uses the instruction retry prohibition instruction signal on the signal line 52 to prohibit the instruction retry control circuit 1 from retrying instructions thereafter. instruct them to do so.

Next, the time counting circuit 10 decrements the contents of the timer register 4 by 1 at certain time intervals, and the timer register all 0 detection circuit 5 detects that the contents of the timer register 4 have become all 0. shall be The timer register all 0 detection circuit 5 detects that the contents of the timer register 4 have become all 0, and the program instruction execution control circuit 3 is notified by the timer register all 0 detection signal on the signal line 54. The program instruction execution control circuit 3 detects the timer register 4 by the timer register all 0 detection signal on the signal line 54.
When informed that the contents of have become all 0,
The counter display data signal on the signal line 59 is set based on a program instruction so that the contents of the counter 7 are invalidated for the counter display circuit 6. That is, if the number of command retries within a certain period is within a certain value, it is assumed that an intermittent failure has occurred and the history of the number of successful command retries is deleted. Conversely, if the number of successful command retries exceeds a certain value within a certain period of time, it is regarded as a fixed failure and subsequent retries of the command are prohibited. Regarding the threshold for the number of instruction retries and the monitoring time for the number of instruction retries, program instructions can be flexibly set depending on the reliability of the elements of the relevant logic device and the actual failure rate statistics. It can be easily changed depending on the operating environment and user requests.

(Effects of the Invention) As explained above, the present invention counts the number of retries when a logic device successfully retries an instruction, and simultaneously starts time monitoring, and measures the number of successful instruction retries within a certain period of time. When a certain value is reached,
Prohibits subsequent command retries, and when the number of successful command retries does not reach a certain value within a certain period of time, clears the history of the number of successful command retries to determine whether the failure is disconnected or fixed. This has the effect of preventing the performance of the entire system from deteriorating due to the overhead of retrying instructions in the event of a fixed failure, and prevents data corruption from occurring due to the induction of 2-bit errors depending on the nature of the failure. This has the effect of preventing the possibility of such occurrence, and has the effect of ensuring that the failure can be recovered in cases of intermittent failure. Furthermore, there is an advantage that the threshold for the number of instruction retries and the monitoring time for the number of instruction retries can be easily changed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the instruction retry control method according to the present invention. DESCRIPTION OF SYMBOLS 1... Instruction retry control circuit, 2... Instruction retry success detection reporting circuit, 3... Program instruction execution control circuit, 4... Timer register, 5... Timer register all 0 detection circuit, 6... Counter display circuit, 7... Counter, 8...Counter overflow detection circuit,
9... Counter counting circuit, 11, 14... Selection circuit,
DESCRIPTION OF SYMBOLS 10... Time counting circuit, 12... Logic device, 13... Maintenance diagnosis device, 50-63... Signal line.

Claims (1)

[Claims] 1. An instruction retry control circuit for controlling instruction retry of a logic device having an instruction retry function, an instruction retry success detection reporting circuit for detecting and reporting the success of the instruction retry, and a program. a counter means that can set a value according to an instruction and counts execution; a counter overflow detection circuit for detecting that a content value of the counter means has reached a predetermined value; and a content value of the counter means. a counter display circuit for setting the enable/disable of by the program instruction; a time counting circuit for counting time intervals; a value can be set by the program instruction and the value is counted by the time counting circuit; a timer register for detecting a timer register; a timer register all 0 detection circuit for detecting that the value of the timer register has reached a predetermined value; and a timer register all 0 detection circuit for detecting that the value of the timer register has reached a predetermined value; If the circuit indicates invalid, the program instruction causes the counter display circuit to display valid, and the counter means and the timer register are each set to a certain value, and from then on, the instruction is retried successfully. The content value of the counter means is counted each time the content value of the timer register is reported, and when the content value of the counter means reaches a predetermined value, the retry of the instruction is prohibited, and the content value of the timer register is set to a predetermined value. and a program instruction execution control circuit for displaying invalidity on the counter display circuit when the instruction value reaches a specified value.