JPS6130304B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a protection device that protects the memory of a microcomputer that is supplied with power from a commercial power source during a power outage of the commercial power source.

FIG. 1 is a block diagram showing an example of a conventional microcomputer. In the figure, 1 is a central processing unit (CPU), 2 is an address decoder, 3a,...
..., 3n is random access memory (RAM),
4 is the address bus from CPU1 to address decoder coder, 5 is CPU1 and RAM3a, ......,
Data bus between 3n, 6 is from CPU1 to RAM3
7 is a memory selection line from the address decoder 2 to the RAM 3a, . . . , 3n, and 8 is a power supply line from the power supply device.

Next, the operation will be explained. Power supply line 8
Power is supplied to the CPU 1 and the RAMs 3a, . . . , 3n. RAM3a from CPU1,...
..., 3n, CPU1 and
While power is being supplied to the RAMs 3a, . . . , 3n, address information is first sent from the CPU 1 to the address decoder 2 via the address bus 4. This address information is sent to address decoder 2.
The data is decoded by the memory selection line 7 and sent to the corresponding RAM 3i. At the same time, read/write commands are transmitted from the CPU 1 to the RAMs 3a, . . . , 3n through the control line 6. As a result, applicable
Only the RAM 3i can send and receive data to and from the CPU 1, and data is sent and received via the data bus 5.

Conventional microcomputers are configured as described above, so microcomputers that are supplied with power from a commercial power source via a power supply device have the disadvantage that the RAM contents will be volatile if the commercial power supply is interrupted. Ta.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above. It protects the memory of a microcomputer during a commercial power outage, and when the power outage stops and power is supplied again, the microcomputer The purpose of the present invention is to provide a microcomputer protection device that protects the microcomputer so that it can continue to operate.

An embodiment of the present invention will be described below.
FIG. 2 is a block diagram showing an embodiment of the present invention, and in the figure, 1, 2, 3a, 3n, 4, 5,
6, 7, and 8 indicate the same or corresponding parts as the same reference numerals in FIG. Note that the power supply line 8 is
Not directly connected to RAM3a, ......, 3n. 9 is a rechargeable battery, 10 is RAM3
11 is a power supply line to RAM 3a, 3n, 12 is a commercial power line that takes in AC from the commercial power supply, 13 is a power failure detection unit, and 14 is a power failure detection unit. Detection signal line, 15 is a reset signal generator, 1
6 is a power failure detection answer signal line, and 17 is a reset signal line.

Next, the operation will be explained. When the commercial power supply fails and the voltage of the AC sent from the commercial power supply through the commercial power line 12 drops, the DC voltage obtained by rectifying the AC in the power failure detection unit 13 becomes lower than the reference voltage. This is detected and regarded as a power outage, and a power outage detection signal is generated. The generated power failure detection signal is sent to the CPU via the power failure detection signal line 14.
1 and the reset signal generator 15. At this point, the voltage on the power supply line 8 has not dropped due to the time constant of the microcomputer's power supply itself, so the microcomputer is operable.

In the CPU 1, the power failure detection signal from the power failure detection unit 13 is input as an interrupt signal, and the internal state of the CPU 1 is changed to the RAM 3 using the power failure detection signal with the highest priority processing.
The program to be saved is driven in a, . . . , 3n. RAM3a of internal state of CPU1,...
. . , 3n, the CPU 1 sends a power failure detection answer signal to the reset signal generating section 15 via the power failure detection answer signal line 16, indicating that the process based on the power failure detection signal has been completed.

The reset signal generating section 15 outputs the power outage detection signal previously sent from the power outage detection section 13 and this power outage detection signal.
By logical product with the power failure detection answer signal sent from CPU1, the power supply line 8
A reset signal is continued to be sent to the CPU 1 through the reset signal line 17 until the power supply to the CPU 1 is stopped, thereby controlling the CPU 1 so that it does not run out of control. In other words, the sending of the power outage detection answer signal means that the evacuation process is complete, so after that
There is no harm in resetting CPU1. In addition, when the voltage of the commercial power line 12 drops and the operation of the reset signal generator 17 stops, the CPU
Since the operation of step 1 also stops, runaway does not occur.

On the other hand, during a power outage of the commercial power supply, the voltage in the power supply line 8 drops after a time delay equal to the time constant of the power supply device. If the voltage on the power supply line 8 becomes lower than the battery voltage of the battery 9,
The power supply switching unit 10 switches the power supply to the RAMs 3a, . . . , 3n from the battery 9. As described above, the power supply is switched and even during a commercial power outage, RAM3a,......,
3n receives power supply from the battery 9, and the RAM contents are protected without being volatile. Note that when power is supplied through the power supply line 8,
The battery 9 is configured to receive power supply through the power supply switching section 10 and to be constantly charged.

When the power outage stops and the power supply from the commercial power source is restored, the voltage of the alternating current taken in from the commercial power source by the commercial power line 12 increases, and the power outage detection unit 13 rectifies the alternating current and converts it into a direct current. voltage becomes higher than the reference voltage, and the power failure detection signal stops generating. Therefore, the reset signal generator 15
Sending of the reset signal to CPU1 stops, and the CPU
1 reset is released. At this time, RAM3
By restoring the internal state of CPU1 that was saved before the power outage to a, ......, 3n, to CPU1 again,
It becomes possible to continue operating in the state before the power outage.

As described above, according to the present invention, even during a commercial power outage, the RAM contents of a microcomputer that is supplied with power from the commercial power source are protected, and the power outage is restored as soon as the power outage ends and the power supply from the commercial power source is restored. Since it is possible to continue the previous system state, there is an effect that the microcomputer can be introduced into equipment that would be inconvenient if the system state changes due to a power outage of the product.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional microcomputer, and FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a CPU, 2 is an address decoder, 3a, ..., 3n is a RAM, 4 is an address bus, 5 is a data bus, 6 is a control line, 7 is a memory selection line, 8 is a power supply line, and 9 is a battery, 10 is a power supply switching unit, 11 is a power supply line,
12 is a commercial power line, 13 is a power outage detection unit, 14
15 is a power failure detection signal line, 15 is a reset signal generator, 16 is a power failure detection answer signal line, and 17 is a reset signal line. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] 1. In a memory protection device for a microcomputer that protects the memory of a microcomputer that has power supplied from a commercial power supply via a power supply device, a battery is installed to supply power to the random access memory during a power outage of the commercial power supply. , a power outage detection unit that generates a power outage detection signal indicating a power outage of the commercial power supply when the voltage obtained from the commercial power supply becomes lower than a predetermined voltage; and a power outage detection signal generated by the power outage detection unit that interrupts the central processing unit. Means for saving the internal state of the central processing unit to the random access memory by inputting it as a signal and activating a predetermined program, and outputting a power failure detection answer signal after the internal state has been saved to the random access memory. means for maintaining the internal state of the central processing unit in a reset state throughout the period during which the power outage detection signal exists after the power outage detection answer signal is output;
The present invention further includes a power supply switching unit that compares the voltage obtained from the commercial power supply and supplied to the random access memory with the voltage of the battery, and switches the power supply with the higher voltage to be supplied to the random access memory. A memory protection device for microcomputers.