JPS6130739B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device equipped with a monitor pattern for a probing test in which a semiconductor wafer is sampled and inspected during a diffusion process.

When forming a large number of semiconductor integrated circuit elements on a semiconductor wafer, a monitor pattern is formed on each element, and transistor element characteristics are inspected using the monitor pattern to determine the depth of the impurity diffusion layer and the like. A method of controlling the concentration during the process is used. This inspection method is called a probing test, in which a probe is brought into contact with the base region, etc., but since the number of elements formed on one wafer is large,
Manual sampling is usually performed to avoid wasting time and to find out variations due to position within the wafer, and is an extremely important test to maintain yield in mass production processes. This is a process that requires many man-hours because it requires minute adjustments.

Of the transistor device characteristics measured in such probing tests, the particularly important one is the current amplification factor (h _FE ), and in a stable manufacturing process, Width 130
A measurement method is used in which a monitor pattern on the order of μm is formed and only the current amplification factor (h _FE ) is estimated.

Figure 1a is a plan view, and Figure 1b is the same as Figure 1a.
In the case of an npn type device, a p + type base region 2 is formed in an n type epitaxial layer 1, and an n ⁺ type base region 2 is formed across the base region 2 ^.
A mold emitter region 3 is formed. and,
When probes are brought into contact with the central positions 2' and 2'' of both sides of the base region 2, a voltage of several volts is applied between both probes, and a current is caused to flow, the emitter region shown in Fig. 1b is formed. A resistance appears that is inversely proportional to the thickness 4 of the base region at the bottom of 3. This is called a pinch resistance, and such a pinch resistance is usually from several KΩ to several tens of KΩ, and when a high resistance appears, a high h _FE The pinch resistance is measured to estimate h _FE and control the diffusion process.

However, in order to bring two probes into close contact in this way, there is a limit to the wire diameter of the probe, and it is difficult to apply strong contact pressure.As a result, contact resistance occurs on the surface, making it difficult to accurately pinch. There is a problem that the resistance value cannot be obtained.

In this case, h _FE will be estimated incorrectly, making it difficult to control the semiconductor element to have the desired characteristics.

In order to eliminate such problems and obtain an accurate pinch resistance value, the present invention includes a semiconductor substrate of one conductivity type, an epitaxial layer of an opposite conductivity type formed on the semiconductor substrate, a first high concentration impurity region of one conductivity type formed in the epitaxial layer and reaching the semiconductor substrate; a second high concentration impurity region of one conductivity type formed in the epitaxial layer and not reaching the semiconductor substrate; a monitor pattern having an impurity region of one conductivity type connected to the first and second high concentration impurity regions, and an impurity region of the opposite conductivity type formed to cross the impurity region and to be shallower than the impurity region; It is characterized by comprising:

Hereinafter, the present invention will be explained in detail by way of an example.

2a and 2b show one embodiment of the monitor pattern of the present invention formed on individual integrated circuit elements within a wafer; FIG. 2a is a plan view;
Figure b is a sectional view BB' of Figure 2a.

In the figure, after an n ⁺ type buried diffusion layer 12 is diffused into a P type semiconductor substrate 10, an n type epitaxial layer 11 is laminated on the substrate, and then a p ⁺ type element isolation region 13 is formed. At the same time, the P ⁺ type high concentration region 14 is also formed by diffusion.

Next, the P type base region 15 is formed by diffusion.
One end of the base region 15 is connected to the element isolation region 13, and the other end is a pattern region including the above-mentioned high concentration region 14.

Next, an n ⁺ type emitter region 16 is formed at the center of the base region and across the base region.

All of these are formed simultaneously with the integrated circuit elements using known photolithography and diffusion techniques.

When the monitor pattern is formed in such a structure, the pinch resistance becomes inversely proportional to the thickness 17 of the base region below the emitter region 16 shown in FIG. Since it is connected to region B, the measurement terminal can be taken from the back surface of the semiconductor substrate without using a probe.

The probe is brought into contact with the other end, but the contact portion is at a position 15' which overlaps with the P ⁺ type high concentration region 14 and is formed by diffusion, and has a very high concentration, so the surface The resistance is also low, and since only one probe is brought into contact with that position, a strong probe with a thick wire diameter can be strongly crimped and the contact resistance can be greatly reduced, allowing for accurate pinching. It is possible to measure the resistance value and thus to know h _FE which closely corresponds to the actual value.

In addition, since the probing test requires only one probe to be contacted and pressed, the measurement is easy and the number of man-hours is reduced, and it is not difficult to perform the measurement automatically.

As described above, since the present invention can determine h _{FE that} closely matches the actual integrated circuit element, it becomes easy to control transistor characteristics during the process, which is useful for forming high-quality semiconductor devices. Moreover, it has the effect of reducing the number of work hours, and can be said to be extremely valuable. Incidentally, in the above description, an npn type semiconductor element was used, but it goes without saying that the present invention can be applied to an npn type element.

[Brief explanation of the drawing]

Figures 1a and b are conventional monitor patterns;
Figures a and b show a plan view and a cross-sectional view, respectively, of a monitor pattern of the present invention. In the figure, 13 is an element isolation region, 14 is a high concentration region formed at the same time, 15 is a base region, and 16 is an emitter region.

Claims (1)

[Claims] 1 A semiconductor substrate of one conductivity type, an epitaxial layer of an opposite conductivity type formed on the semiconductor substrate, and a first high concentration impurity region of one conductivity type formed in the epitaxial layer and reaching the semiconductor substrate. , a second high concentration impurity region of one conductivity type formed in the epitaxial layer and not reaching the semiconductor substrate; an impurity region of one conductivity type connected to the first and second high concentration impurity regions; 1. A semiconductor device comprising a monitor pattern having an impurity region of an opposite conductivity type formed to cross an impurity region and to be shallower than the impurity region.