JPS5927097B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for evaluating the state of formation of a junction during the manufacturing process.

Conventionally, in the bonding process of a semiconductor substrate (hereinafter referred to as a semiconductor wafer) on which a plurality of semiconductor elements of a semiconductor device such as a transistor or a semiconductor integrated circuit are to be fabricated, the inside of the semiconductor element forming area of the semiconductor wafer is Alternatively, a monitor transistor is formed whose emitter-base junction is a junction that is formed separately and simultaneously with the junction of the semiconductor element, and this monitor transistor has electrical characteristics such as its junction breakdown voltage and its current amplification factor. A widely used method is to evaluate the characteristics, evaluate the state of bond formation between semiconductor wafers within the same rod based on the results, and control the bond formation process.

Below, the first method for evaluating the state of bond formation of transistor silicon wafers using a conventional monitor transistor will be described.
A description will be given of FIGS. 2 a to 2 c, which show the manufacturing process using the plan view shown in the figure and the vertical cross section taken along the line ■-■.

Since the monitor transistor junction and the silicon wafer junction are formed at the same time, only the monitor transistor will be described here to simplify the explanation.

This monitor transistor is formed on the surface of a silicon wafer 1 by a junction consisting of a base diffusion layer 2 and an emitter diffusion layer 3 having a pattern as shown in FIG.

The steps for creating this monitor transistor are shown in Figure 2 a-c.
Shown below.

First, a filled oxide film 4 is formed on the entire surface of the silicon wafer 1.

Next, base impurity diffusion windows are opened at required locations in the filled oxide film 4, and the base diffusion layer 2 is formed by selective diffusion from this base impurity diffusion window. Subsequently, an oxide film 5 is formed to cover the entire upper surface including the upper surface of the base diffusion layer 2. This state is shown in FIG. 2a. The preparation steps for this will be explained with reference to FIG. 2b.

First, an emitter impurity diffusion window is opened in the oxide film 5 at a predetermined location on the base diffusion layer 2, and the emitter diffusion layer 3 is formed by selective diffusion from this emitter impurity diffusion window. Subsequently, an oxide film 6 is formed to cover the entire upper surface including the upper surface of the emitter diffusion layer 3. This state is shown in FIG. 2b. At the production stage shown in FIG. 2c, the base diffusion layer 2, the emitter diffusion layer 3, and the field oxide film 4 and oxide films 5, 6 on the silicon wafer 1 at required locations around these diffusion layers 2, 3 are formed.
are removed by selective etching to expose the base diffusion layer 2 and emitter diffusion layer 3.

The monitor transistor manufactured through these manufacturing steps connects the back surface of the silicon wafer 1 to the collector contact surface 7.
and the exposed surface of the base diffusion layer 2 is the base contact surface 8,
The exposed surface of the emitter diffusion layer 3 is configured as an emitter contact surface 9.

Therefore, the measurement needle of the wafer prober is brought into contact with the collector contact surface 7, base contact surface 8, and emitter contact surface 9 of the monitor transistor, and the current amplification factor, forward voltage drop, and reverse dielectric strength of the monitor transistor are measured. The DC characteristics of the base diffusion layer 2 and the emitter diffusion layer 3 are evaluated based on the measurement results.

By the way, in this method of evaluating the junction formation state using a monitor transistor, even if the junction formation state is the same, the current amplification factor and the collector-emitter current of the monitor transistor are The disadvantage is that the measured values such as the reverse withstand voltage between the two electrodes fluctuate greatly, and the deviations caused by the fluctuations in the measured values make it difficult to accurately evaluate the state of the bond.

For example, when the base diffusion layer 2 has a thin layer thickness of about 0.6 μm or less, a voltage is applied between the measuring needle of the wafer prober and the base contact surface 8 and between the measuring needle of the wafer prober and the emitter contact surface 9. Another drawback was that the junction of the monitor transistor was destroyed due to sparks generated by the applied voltage, making measurement impossible. For these reasons, more difficult problems have arisen in automating and measuring the contact of the measurement needle of the wafer prober. Moreover, since the edge of the bond is exposed on the surface of the silicon wafer, it is susceptible to the influence of the external atmosphere, and there is a possibility that measurement errors may occur. The present invention has been made in view of the above-mentioned drawbacks, and is directed to the pinching of the first conductivity type diffusion layer which is pinched by the second conductivity type diffusion layer formed in the first conductivity type diffusion layer. By measuring the resistance value,
It is an object of the present invention to accurately evaluate the state of formation of a junction between the first conductivity type diffusion layer and the second conductivity type diffusion layer, and to control the process of forming this junction.

Hereinafter, the method for evaluating the formation state of a junction in a silicon wafer of a transistor according to the present invention will be described in a plan view shown in FIG. 3 and in FIG.
This will be explained in -c. The pattern of the monitor structure used in the evaluation method according to the present invention is a first pattern 10 consisting of a base diffusion layer 2 and an emitter diffusion layer 3 as shown on the left side of FIG. 3, and a first pattern 10 as shown on the right side of FIG. Such a party
and a second pattern 11 consisting of a base diffusion layer 2 of the same type. Each production step of producing a monitor structure having such a first pattern 10 and a monitor structure having a second pattern 11 inside or outside a region of the silicon wafer 1 where transistors are to be formed is performed. Figure 4a
-c will be explained.

Again, as described with reference to FIG. 2, since the bonding of the monitor structure and the bonding of the silicon wafers are formed at the same time, only the monitor structure will be described. First of all,
A field oxide film 4 is formed on a silicon wafer 1.

Next, the base diffusion layer 2 of the first pattern 10 and the second
Base impurity diffusion windows for forming the base diffusion layer 2 of the pattern 11 are opened in the field oxide film 4, and the base diffusion layers 2 are formed by selective diffusion from these base impurity diffusion windows. The dimensions and shapes of the base diffusion layer 2 of the first pattern 10 and the base diffusion layer 2 of the second pattern 11 formed at this time are set to be substantially the same. Subsequently, an oxide film 5 is formed to cover the entire upper surface of the base diffusion layer 2 including the exposed surface. This state is shown in FIG. 4a.
Next, the production stage will be explained with reference to FIG. 4b.

An emitter impurity diffusion window is opened in the oxide film 5 and has a width indicated by the reference numeral W2 in FIG. The emitter diffusion layer 3 is formed by selective diffusion from the emitter impurity diffusion window. In FIG. 3, the base diffusion layer 2 and the emitter diffusion layer 3 are shown to intersect at almost right angles, and the widths W and W2 of these diffusion layers are approximately the same.
They do not necessarily need to intersect at approximately right angles and have approximately the same width. Next, an oxide film 6 is formed to cover the entire upper surface of the emitter diffusion layer 3, including the exposed surface. This state is shown in FIG. 4b. Next, the production stage shown in FIG. 4c will be explained.

Contact holes 12 and 13 are formed by selectively etching the oxide films 5 and 6 on the base diffusion layer 2 at positions equidistant on both sides of the emitter diffusion layer 3 of the first pattern 10. At the same time, contact holes 14 and 15 are formed by selectively etching the oxide films 5 and 6 on the base diffusion layer 2 of the second pattern 11 at approximately the same distance as the contact holes 12 and 13. do. This state is shown in FIG. 4c. A measurement needle of a wafer prober is brought into contact with the contact holes 12 and 13 of the base diffusion layer 2 of the first pattern 10 created in this way, and the pinch resistance of the base diffusion layer 2 pinched by the emitter diffusion layer 3 is measured. Measure the value. This pinch resistance value is determined by the layer thickness of the base diffusion layer 2 and the emitter diffusion layer 3 formed on the base diffusion layer 2.
As the difference between the layer thickness and the layer thickness of The process can be controlled. Furthermore, a measuring needle of a wafer prober is brought into contact with the contact holes 14 and 15 of the base diffusion layer 2 of the second pattern 11 to measure the resistance value of the base diffusion layer 2,
The formation state of the base diffusion layer 2 can be evaluated. By using both the resistance value of the base diffusion layer and the pinch resistance value, it is possible to more accurately evaluate the formation state of the emitter-base junction of the transistor and control the junction formation process. Furthermore, even more accurate evaluation can be achieved by using a monitor transistor and evaluating electrical characteristics such as current amplification factor of the monitor transistor. In addition, in this evaluation method, the measuring needle of the wafer prober is not brought into contact with the emitter diffusion layer for measurement, so there is no risk of destroying the emitter-base junction as described above, and the emitter diffusion layer is not formed on the silicon wafer 1. Since the surface of the emitter diffusion layer 3 is covered with the oxide film 6, the edge of the emitter-base junction is not exposed, and there is no risk of measurement errors being affected by the external atmosphere. Furthermore, there is the advantage that the base spread resistance value, which is one of the factors that affect high frequency characteristics, can be determined during the wafer process.

In the above embodiment, a method has been described in which a monitor structure is formed inside or outside the region where a transistor is to be formed in the silicon wafer 1 to evaluate the formation state of a transistor junction. Insert the silicon wafer on which only the body is to be formed together with the silicon wafer rod of the product transistor,
By evaluating the formation state of the diffusion layer formed on the monitor structure after the rod has gone through the junction formation process, it is also possible to evaluate the formation state of the junctions of product transistors in the same lot.

Although the method for evaluating the junction formation state of transistors formed on a silicon wafer has been described so far, the evaluation method of the present invention is not limited to this, and can be applied to a method for evaluating the junction formation state of semiconductor devices such as semiconductor integrated circuits. You can also do that.

As described above in detail, in the evaluation method of the present invention for evaluating the formation state of the junction between the first diffusion layer and the second diffusion layer in the manufacturing process of the semiconductor device, A first diffusion layer, which is formed separately from the semiconductor element at the time of forming the junction, within or outside the region of the semiconductor element of the semiconductor wafer in which the element is to be fabricated, and has a required length and width; A monitor structure is formed of a second diffusion layer which is formed to intersect with the first diffusion layer almost in the center and has a required length and a required width, and the second diffusion layer of this monitor structure is The formation state of the bonding layer is evaluated by utilizing the fact that the pinch resistance value of the first diffusion layer pinched by the layers increases as the layer thickness of the second diffusion layer increases. There is no need to bring the measurement needle of the wafer prober into contact with the diffusion layer, and there is no risk of destroying the above-mentioned junction, unlike the conventional evaluation method using a monitor transistor.

In addition, since it is not necessary to selectively remove the oxide film covering the second diffusion layer to expose the second diffusion layer, the edge of the junction is exposed and is subject to the influence of the external atmosphere, making it difficult to perform measurements. There is no possibility of errors occurring. Furthermore, the base spread resistance value, which is one of the factors that influences high frequency characteristics, can be determined during the wafer process.

[Brief explanation of the drawing]

FIG. 1 is a plan view for explaining a method for evaluating the state of junction formation in a silicon wafer of a transistor using a conventional monitor transistor, FIGS. 2 a-c are longitudinal cross-sectional views taken along the - line in FIG. 4 is a plan view for explaining a method for evaluating the state of junction formation in a silicon wafer of a transistor according to the present invention, and FIGS. 4a-4c are vertical sectional views taken along a line in FIG. 3. In the figure, 1 is a silicon wafer, 2 is a base diffusion layer, 3 is an emitter diffusion layer, 4 is a field oxide film, 5, 6 are oxide films, 7, 8, and 9 are a collector contact surface, a base contact surface, and an emitter contact surface, respectively. contact surfaces, 10, 11 a first pattern and a second pattern of monitor arrangements, 12,
13, 14, and 15 indicate contact holes.

Claims (1)

[Claims] 1 A semiconductor substrate having a junction between a first conductivity type diffusion layer and a second conductivity type diffusion layer formed within the first conductivity type diffusion layer, and in which a plurality of semiconductor elements are to be fabricated. a diffusion layer of a first conductivity type having a required length and a required width, within or outside the region of the semiconductor element, and separate from the semiconductor element during formation of the junction; A monitor structure is formed of a second conductivity type diffusion layer having a required length and a required width, intersecting each other at approximately the center of the diffusion layer, and the second conductivity type diffusion layer of the monitor structure is A method for manufacturing a semiconductor device, characterized in that the formation state of the junction is evaluated by measuring the pinch resistance value of the diffusion layer of the first conductivity type that is pinched.