JPS6130757B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, a signal is first input into a serial transfer channel from an input end, and then transferred all at once to a large number of parallel channels. The so-called SPS type (serial/parallel/serial type) charge is transferred all at once to another serial channel with an output end at the end of the , and then transferred through the serial channel again and the signal is taken out at the output end. Regarding a transfer device.

Figure 1a is a conceptual diagram of an SPS type CCD, where 1 is an input terminal to which an input signal is added, 2 is an input serial channel CCD that transfers this, and 3 is an input serial channel.
A control gate (hereinafter referred to as the first control gate) that controls the timing of transferring the charge of CCD 2 to multiple parallel channels CCD 4, 5 is the output channel CCD
6 is a second control gate for controlling the timing and potential for transferring charges from the parallel channel CCD 4; 7 is an output terminal for taking out a signal transferred via the output serial channel CCD 6; Figure 1a
Input series channel CCD2 and parallel channel CCD
A part of the connection with 4 is surrounded by a circle 8, and an enlarged plan view of this is shown in Figure 1b.
It is.

In FIG. 1b, 9 and 10 are transfer electrodes of the input series channel CCD2, and the channel stop region 11 that defines the channel side of this input series channel CCD2 is parallel for each bit. It is interrupted by a channel region 14 which serves as a connection to the channel CCD 4. One or two transfer electrodes for each bit protrude so as to cover the channel region 14 serving as the connection section described above, and form a charge outflow section from the input series channel CCD 2. This transfer electrode is 10. 12 is an electrode constituting the first control gate 3;
3 is a transfer electrode of the parallel channel CCD 4. In FIG. 1b, FIGS. 2a and 2b show potential distributions when the channel width W of the channel region 14 serving as the charge outflow portion (transfer region) of the input series channel CCD 2 is wide and narrow.

In FIGS. 2a and 2b, 15 is a gate oxide film;
16 is a line showing potential distribution. The explanations of other reference numerals are the same as in FIG. 1b.

For convenience of explanation, it is assumed that both the input serial channel CCD 2 and the parallel channel CCD 4 are configured as N-channel embedded type. Transfer electrode 1 serving as a transfer gate
When a voltage is applied to 0, a deep potential is formed for charges (electrons), and the channel region 14 becomes a charge outflow region.
has been opened. However, the potential of the channel stop region 11 hardly changes even when a gate voltage is applied, and is fixed at a value close to the potential of the Si substrate. Moreover, because this high potential spreads to the channel region 14, which becomes the charge outflow section, due to the two-dimensional electric field distribution, the potential of the channel region 14 becomes smaller than the channel region 14, as shown in FIG.
It is pulled up as it approaches the stop area 11. When the channel width W of the channel region 14 is wide as shown in FIG. 2a, the minimum potential φ ₁ determined by the gate voltage is reached at the center of the width W, but When W becomes narrower, the spread of the higher potential from the left and right channel stop regions 11 also affects the center of the width W, and the lowest potential becomes shallow to _φ2 , creating a difference of only Δφ.

Since the channel width perpendicular to the direction of charge transfer of the input series channel CCD 2 is normally wider than the width W of the channel region 14 serving as the charge outflow portion, the width of the channel under the transfer electrode 10 in FIG. The potential differs depending on the location within the channel.
A diagram illustrating this is FIG. 3, which is a potential diagram cut along line A-A' in FIG. 1b. In the figure, 15 is a gate oxide film, 16 is a line showing the potential distribution, 17 is a line showing the potential distribution when the present invention is applied, which will be described later, and 18 is the transfer electrode 1.
The charge left below 0, 19, is the channel region 14
This is the charge transferred to the bottom of the transfer electrode 13 of the parallel channel CCD 4 through the . The other numbers are the same as explained in FIG. 1b. As shown in FIG. 3, the potential at the center of the transfer electrode 10 is φ ₁
However, the potential of the outflow portion at the end becomes shallower by Δφ as explained in FIG. 2b. Therefore, a potential wall of Δφ is created, and a part of the charge under the transfer electrode 10 is 18
There is a portion left as shown in , and a portion not transferred as shown in 19. This is the input series channel CCD
This results in a decrease in the dynamic range of 2. Computer analysis has recently revealed that Δφ can reach 3V or more in some cases. On the other hand,
The difference between the central potential under the transfer electrode of a buried series channel CCD with and without charge varies depending on the concentration and depth of the buried well, but if it is small, the limit is around 2V. Become. If more charge is injected, the charge will spread until it reaches the Si-SiO ₂ interface, and in the normal buried type operation mode it will not move and the transfer efficiency will deteriorate. In other words, in an extreme case, due to the influence of the width W of the narrow channel region 14, a disadvantage arises in that charges cannot be transferred from the buried channel of the input series channel CCD 2 to the parallel channel CCD 4. Moreover, even if it can be transferred, the dynamic range will be significantly impaired.

In the above explanation, the embedded type was used as an example, but even surface type devices have similar effects, although there are differences in degree. Furthermore, as the density of integration increases, the length of the electrodes becomes smaller, and the width W of the channel region 14 also becomes smaller, so that the degree of reduction in the dynamic range becomes even greater.

The present invention has a first relatively wide channel width.
A second channel passes through a narrow channel area at one end of the CCD.
The purpose of this is to expand the dynamic range of a CCD that has a part that transfers charge to the CCD. Basically, the method for this purpose is to reduce or completely eliminate the height Δφ of the potential wall of the channel region 14, which serves as the charge outflow portion, as shown in FIG. 2b and 17 in FIG. Bye.

The present invention will be described below based on examples together with drawings.

An embodiment of the invention is shown in FIGS. 4a-c. Figure a is a top view of the connection between the series channel CCD and parallel channel CCD, and Figures b and c are A-A in Figure A.
FIG. 3 is a cross-sectional view along A′. In FIGS. 4a to 4c, 15 is a gate oxide film, 21 is a silicon substrate which is a semiconductor substrate, and 20 is a transfer region including a charge outflow portion of transfer electrode 10. In FIGS. The rest is the same as explained in FIG. 1b. As shown in FIG. 4a, one simple way to deepen the potential in a portion of the transfer region 20 is to implant impurity ions. In the case of a surface type CCD, the transfer area 20
The purpose is to make the region more depressed than the region below the transfer electrode 10. Therefore, in the case of an N channel, since the substrate is a P substrate, for example, phosphorus ions may be implanted. In the case of a buried type N channel, for example, phosphorus ions are implanted over the entire channel portion under the transfer electrodes 9 and 10 to form the channel, but the potential from the channel stop region 11 is also implanted into the transfer region 20. Just inject the necessary amount to compensate for the spread. Ultimately, regardless of whether it is a surface type or a buried type, impurity ions that provide a conduction type equivalent to a conduction channel type may be implanted into at least a large area of the charge draining portion of the series CCD. A cross-sectional view of this is shown in FIG. 4b. Although this figure shows the case of a surface type, in the case of a buried type, ions may be further implanted into the region shown in FIG. 4b in addition to the dove in the normal buried region.

FIG. 4c shows an embodiment in which the potential depth is adjusted by adjusting the oxide film thickness. In a buried channel, for the same buried well concentration, depth, and gate voltage, the larger the oxide film thickness, the deeper the potential. In a calculation example, if the gate voltage is 10V, 3100
The potential under the oxide film at Å is about 1.5 V deeper than that under 1300 Å. This potential difference can also compensate for the potential wall indicated by Δφ in FIG.

The above describes a CCD with an SPS configuration as an example for explanation, but the effects of the present invention are not limited to this, and one end of the channel of the first CCD is narrowed, and the second CCD is It is clear that the present invention is effective for CCDs of all configurations in which charge is transferred to the CCD.

Now, as a specific method for manufacturing the embodiment shown in FIG. 4a for a buried type series channel, the buried type channel region can be formed by performing ion implantation twice as described above. In the method shown in FIG. 5, this can be achieved by one ion implantation. In FIG. 5, 31 is a silicon substrate which is a semiconductor substrate, 32 is a mask material for the first ion implantation, and is made of SiO ₂ , Si ₃ N ₄ , or other materials such as an auto-resist film or other insulating film or conductive film. Good too. The thickness d of this first mask material 32 needs to be close to the range of the implanted ions relative to the material. 33 shows a mask material for the second ion implantation, which may be the same as or different from the material of the first mask material 32. The thickness D of the second mask material 33 needs to be sufficiently thick to prevent implanted ions from passing through. After a cross-sectional structure as shown in FIG. 5 is formed by a normal photolithography process and ions are implanted, the opening 34 shown in FIG.
is Si equal to the implantation dose per unit area.
Injected into the substrate. However, in the region of film thickness d, some of the implanted ions are captured in the film, and the silicon substrate 3
As a result, the remaining portion is implanted into 1, resulting in an ion concentration distribution as shown by the dotted line 35. By driving in these ions to form a buried channel region, the series channel described above can be achieved.
The potential wall in the narrow channel region of the charge draining portion of the CCD can be reduced or eliminated.

In the present invention, by selecting the metal of the gate electrode on the other transfer region of each of the above embodiments, the potential can be deepened by utilizing the difference in work function. Taking advantage of the fact that the (111) plane has more interfacial charge than the 100) plane, it is also possible to deepen the potential by setting the substrate on the transfer region to the (111) plane.

With the configuration and method described above, when the channel width is partially narrowed, the SPS The dynamic range of the CCD structure can be significantly improved. Furthermore, as the density increases, the channel width becomes a few microns.
The height of the potential wall due to the aforementioned lifting effect becomes very dimensionally sensitive. On the other hand, in the structure in which a large number of parallel channels are provided as shown in FIG.
It is possible that the channel width W of 4 may differ for each parallel channel due to photo-etching or other irregularities. In such a case, the non-uniformity of the potential wall height Δφ for each parallel channel causes fixed pattern noise in the signal at the output end. Therefore, the present invention makes it possible to eliminate the cause of this problem, and therefore has the remarkable effect of reducing noise in the charge transfer device.

[Brief explanation of the drawing]

Figures 1a and b are schematic plan views and enlarged plan views of the SPS/CCD, Figures 2a and b are diagrams explaining the spread of the potential from the channel stop area, and Figure 3 is the potential in the channel stop area. Figures 4a to 4c are plan views and cross-sectional views of essential parts showing an embodiment of the present invention. FIG. 5 is an explanatory diagram of one manufacturing method when implementing the present invention. 1...Input end, 2...Input series channel
CCD, 3, 5... Control gate, 4... Parallel channel CCD, 6... Output series channel CCD, 7...
...Output end, 9, 10, 13...Transfer electrode, 11...
... Channel stop region, 12 ... Control gate electrode, 14 ... Channel region, 15 ... Gate oxide film, 20 ... Transfer region, 21, 31 ... Semiconductor substrate.

Claims (1)

[Scope of Claims] 1. Charges transferred through a first charge transfer device are transferred to a second charge transfer device through a transfer region having a channel width narrower than a channel width of the first charge transfer device. In a charge transfer device in which a charge is transferred, a structure in which the impurity concentration of the transfer region is higher than the impurity concentration of the other transfer regions is used as a means for making the potential of the transfer region deeper than that of the other transfer regions. A charge transfer device. 2 Charge transfer in which charges transferred through a first charge transfer element are transferred to a second charge transfer element via a transfer region having a channel width narrower than the channel width of the first charge transfer element. In the device, the thickness of the insulating film on the transfer region is made thicker than the thickness of the insulating film on other regions as a means for making the transfer region have a deeper potential than other transfer regions. A charge transfer device using a structure.