JPS6131487B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention is used in electronic equipment having a functional unit that executes calculations under microprogram control and recognizes and displays the calculation results, and is particularly suitable for display control in devices driven by a small-capacity internal power source. Regarding the method. In recent years, small electronic devices such as electronic desktop calculators that employ a microprogram method have become widespread. These small electronic devices use C-circuits to reduce power consumption and to make them smaller and lighter.
One that is composed of a MOS (complementary symmetrical MOS) LSI and uses a liquid crystal for the display has been put into practical use. This C
- It is well known that in MOS/LSI, reducing the amount of pulses used for various operations, that is, preventing switching operations in the C-MOS circuit, greatly contributes to reducing power consumption. However, in conventional electronic devices of this type, even when the content of a certain single digit is recognized and displayed, all digits of the display buffer are configured to be driven and controlled each time, so the display is not displayed every time the display operation is performed. A control operation pulse was required to serve as a display control signal to drive and control all digits of the buffer. For this reason, in the past, this type of display control system pulse drive had the disadvantage of consuming a considerable amount of wasted power. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a display control method that can reduce power consumption by suppressing the number of display control signals generated without interfering with display operations. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit block diagram showing one embodiment of the present invention, and numeral 11 in the figure is a ROM in which various microinstructions are stored. Then, from the ROM 11, a signal [F
_U ], a signal that specifies the row address of the register that stores operands [S _U ], a signal that specifies the column address of the register that stores operands in the RAM 12 or the processing start column address [F _L ], a signal specifying the column address of the register storing the operation number or the processing end column [S _L ], an instruction signal [INS] such as an operation instruction or a transfer instruction, and the above signals [F _L ], [S The mode setting signal [M] for switching to the mode of [ _L ], and the signal [NA] for specifying the next address of the bus line a to f, respectively.
are output in parallel via . The signal [NA] output via the bus line f is temporarily stored in the address register 13. The output of the address register 13 is input to the address decoder 14. This address decoder 14 decodes the input signal into each address and decodes it into the ROM 1.
1 and specifies the address of the ROM11. Further, the signals [INS] and [M] are sent to the instruction decoder 15 via the bus line e, respectively.
is applied to This instruction decoder 15 outputs control signals O ₁ to O ₃ in synchronization with three-phase timing signals t ₁ , t ₂ , and t ₃ input from the timing decoder 17 . The timing decoder 17 decodes the output of the timing counter 16 which generates timing signals such as clocks φ ₁ and φ ₂ and outputs the timing signals t ₁ to _{t 3} . Further, signals [F _U ] and [S _U ] specifying the row address of the register of the RAM 12 are applied to gate circuits G ₁ and G ₂ via bus lines a and b, respectively, and these gate circuits G ₁ and The output of _G2 is input to the row address input terminal [RAU] of the RAM 12 via the bus line h. In addition, the above gate circuit
The timing signal _{t 1 output} from the timing decoder 17 is supplied to G 1 via the inverter 18, and the timing signal t ₁ is directly supplied to the gate circuit G ₂ , and opening/closing is controlled by this timing signal.

【table】

[Table] Also, as shown in Table 1 above, when the mode signal [M] is "1", the signals [F _L ] and [S _L ] are ,Y
When the register column address and mode signal [M] is "0", the start and end column addresses of the process are specified, and each output is sent to the instruction decoder via bus lines c and d, respectively. 15 output signals O ₁ and O ₂ are applied to gate circuits G ₃ and G ₄ whose opening and closing are controlled. However,
The outputs of the gate circuits G ₃ and G ₄ are both output to the input/output common bus line i, input to the column address input terminal RAL of the RAM 12, and input to the adder circuit 22. On the other hand, the RAM 12 has, for example, X, Y, and Z accumulator registers and other various registers arranged in the row direction, and each of these registers can be accessed by input from the row address input terminal [RAU]. , the digits of each register are respectively designated by inputs to the column address input terminals [RAL].
Therefore, the data read out for the operation number, operand number, transfer, etc. addressed by the above row and column addresses is once read into the latch circuit provided in the RAM 12, and the output terminal [OUT ] is output as parallel 4-bit data. This output data is input to the buffer register 20 via the bus line j, where it is read and controlled by the timing signal _t1 · _φ1 and written out by the timing signal _φ2 . The data stored in this buffer register 20 is sent to an adder circuit 22 that performs parallel addition/subtraction operations via a gate circuit _G5 controlled by a timing signal ₁ and a signal _O4 output from an instruction decoder 15. It will be done. Further, the data outputted from the output terminal OUT of the RAM 12 to the bus line j is sent to the adder circuit via a gate circuit _G7 controlled by the timing signal ₁ and the signal _O5 outputted from the instruction decoder 15. Sent to 22. In this embodiment, the signal [S _U ] specifying the row address of the register storing the arithmetic operation number is sent to t ₁ by the gate circuit G ₂ .
The signal [F _U ] that specifies the row address of the register that stores the operand is output at timing t ₂ and t _{3, so the above signal is output at timing t 2 and t 3 .} bus line j
Among the data output to , the operand is stored in the buffer register 20, and then sent to the adder circuit 22 via the gate circuit G ₆ at timings t ₂ and t ₃ , and the operand is stored as is at t _{2 and t 3} . It is sent to the adder circuit 22 via the gate circuit _G7 at timing _t3 . The calculation result in this adder circuit 22 is
The _signal is sent to the data input terminal [IN] of RAM12.
It is written into a predetermined register of the RAM 12 at timing φ ₁ and read into the buffer register 19 at timing t ₁ ·φ ₁ . The data read into the buffer register 19 is read out at the timing t ₁ and φ ₂ and is output via the gate circuit G ₅ controlled by the signal O ₃ output from the instruction decoder 15. Ru. The data outputted from this buffer register 19 via the gate circuit _G5 is inputted to the column address input terminal "RAL" of the RAM 12, and also inputted to the adder circuit 22, and the column address S _L outputted from the ROM 11. It is also input to the coincidence circuit 23. Timing signals t ₁ to _{t 3} in this RAM 12
The operation start for each is shown in Table 2 below.

[Table] Also, reading and writing to RAM12 is as follows:
The output _O6 of the instruction decoder 15 and the timing signal _t3 are sent to the RAM via the gate circuit _G8 .
It is controlled by applying voltage to the R/W terminal of No. 12. The coincidence output of the coincidence circuit 23 is applied to the AND circuit 24 together with the timing signal _t3 , and the output of the AND circuit 24 is applied to the flip-flop 25 operating at the timing _t3 · _φ1 , and is also applied to the NAND circuit. Added to 26. The output of this NAND circuit 26 is sent to the address register 13 as an address control signal _φROMA . Further, the output of the flip-flop 25 is applied to an AND circuit 28 via an inverter 27. This AND circuit 28 further includes a timing signal.
t ₁ and the address increment instruction O ₇ output from the instruction decoder 15 are input, and the output signal thereof is input to the carry input terminal of the adder circuit 22 . When carrying data, the adder circuit 22 temporarily holds the carry signal internally and executes carry arithmetic processing within the adder circuit 22. The output of the adder circuit 22 is input to a display processing circuit 30 and also to a display control buffer register 31. In this display control buffer register 31,
It stores an address signal (column address) according to the display digit content input to the display processing circuit 30 in the display operation mode, and the address signal stored in the display control buffer register 31 is sent to the display clock generator 32. Sent. The display clock generating section 32 receives the display command [O ₈ ] and the t ₂ ·φ ₁ signal output from the instruction decoder 15, decodes the address signal, and generates a display control signal φ _DP specific to the address signal. , φ _D1 ~ φ _D8
This outputs the following. In addition, the display processing circuit 30
After decoding the input display data in units of digits, that is, numerical data and decimal point display digit data, this decoded signal is converted into a display segment signal by a segment encoder and output, and at the same time it is directly used for displaying the decimal point of the display buffer 33, which will be described later. It supplies an output signal to the buffer. The display segment signal outputted from the display processing circuit 30 is then sent to a static display buffer 33.
is sent to the data input terminal of each digit. The display control signals φ _DP , φ _D1 to φ _D8 outputted from the display clock generator 32 are sent to the display buffer 33 separately to the control terminals of the corresponding digits of the display buffer 33, so that the display control signals The display processing circuit 3 is connected to the corresponding digit of the display buffer 33 that receives the signal φ _Di.
The display segment signal and decimal point display signal output from 0 are written. That is, since the display buffer 33 is of a static type, the contents of each digit that does not receive the display control signal φ _Di are retained as they are, and only the contents of the digits that receive the display control signal φ _Di are updated and stored. Ru. The outputs of each digit of the display buffer 33 are sent to a display section (8 digits in this case) 35 via a display driver 34 which appropriately combines and drives the outputs of each digit. FIG. 2 shows the specific configuration of this display control system. The 4-bit display data obtained through the adder circuit 22, that is, the display numerical data 0 to 9 and the decimal point display digit data (1 to 8) are After being decoded by the data decoder ₃₀₁ of the display processing circuit 30, it is input to the segment encoder ₃₀₂ , and the outputs a to g of the segment encoder ₃₀₂ are input to each digit data input terminal of the data buffer ₃₃₂ of the static display buffer 33. is input. Further, the data decoder ₃₀₁ outputs decoded signals corresponding to the decoded numerical values 0 to 7 to a static display buffer 33.
It is also input to the decimal point display buffer ₃₃₁ . On the other hand, the address data obtained via the adder circuit 22 is read into the display control buffer register 31 by the _t1 · _φ1 signal, and sent to the decoder ₃₂₁ of the display clock generator 32 by the _φ2 signal to be decoded. After that, it is output from the output control gates A ₁ to _{A 9} in synchronization with the t ₂ · φ ₁ signal, and it is a display control specific to the address data output from the output control gates A ₁ to _{A 9} . Signals for φ _DP , φ _D1 ………
is supplied to the control end of the corresponding digit of the display buffer 33. Here, the above φ _DP is a signal for controlling decimal point display. The output of each digit of the display buffer 33 (output of numerical data and decimal point data) is composed of, for example, an exclusive OR circuit, and is input to the display driver 34 that AC drives the display section (liquid crystal) 35. be done. Further, a scanning signal SS for dynamic driving is applied to the display section 35. The operation will now be explained with reference to FIGS. 3a and 3b and FIGS. 4a to 4d. Here, as an example, a case will be described in which a three-digit numerical value "78.9" including a decimal point is displayed. In addition, the number of digits of data handled at this time is 4, which includes one decimal point designation code.
It becomes a digit. Also, the above numerical data “78.9” is RAM
12 is stored in the X register. First, the ROM 11 sends an instruction code to the instruction data 15 to display the contents of the X register in the RAM 12, and also specifies the signal S _U for specifying the X register and the 0th to 3rd digits. Signal for F _L
“0000” and S _L “0011” are output. As a result, the instruction decoder 15 outputs the display command.
_O8 is output, and a mode setting signal M for multiple digit processing is also output. When the timing signal _t1 is output from the timing decoder 17, the gate circuit _G2 is opened and the control signal output from the instruction decoder 15 is
Gate circuit G ₃ opens at O ₁ , and the signal S _U output from ROM 11 is sent to the row address input terminal of RAM 12.
In addition to being supplied to RAU, the signal F _L (“0000”)
is also supplied to the column address input terminal RAL. As a result, the contents of the 0th digit of the X register, that is, the contents of _X0 , are read from the RAM 12 at timing _t1 of the D _P period shown in FIG. 3A. The content of this X ₀ is “1” (decimal point specification code)
It is stored in the buffer register 20 at the timing of _t1 · _φ1 . Furthermore, during this period _t1 , the contents of F _L ("0000") via the gate circuit _G3 are sent to the adder circuit 22 via the bus line i, and at this time the flip-flop 25 is still in the reset state. , the AND circuit 28 receives the timing signal t ₁ and the address increment command O ₇ and outputs it to the adder circuit 22 at the timing of t ₁ . As a result, the contents of F _L input to the adder circuit 22 are incremented by 1 and output, and this column address signal "1"("0001") is stored in the buffer register 19, and the buffer register for display control is also stored in the buffer register 19. It can be stored in 31. This state is shown in FIG. 4a. Next, when the timing signal _t2 is output from the timing decoder 17, the buffer register 2
The content "1 _" of X0 stored in 0 is input to the adder circuit 22 via the gate circuit _G6 , and sent through the adder circuit 22 to the data decoder ₃₀₁ of the display processing circuit 30 for decoding. is,
Decimal point display buffer 3 of display buffer 33
3 Output to the signal line corresponding to the second digit of ₁ , that is, the signal line corresponding to the numerical value 1. On the other hand, the column address signal "1" stored in the display control buffer register 31 is sent to the decoder 321 of the display clock generator 32 at the timing t2 _{· φ2} and is decoded, so that the column address signal " ₁ " corresponds to "1". This decoded output D _P is output, and is taken out as a display control signal φ _DP from the output control gate A ₁ at the timing t ₂ ·φ ₁ . Then, this signal φ _DP is displayed on the buffer 33.
The signal is sent to the control end of the decimal point display buffer ₃₃₁ , and a signal "1" is written in the second digit of the decimal point display buffer ₃₃₁ based on the content "1" of the above _X0 . This state is shown in FIG. 4b. Then, after the timing at t ₃ , the timing signal t ₁ is output again in the D ₁ period.
By outputting , the buffer register 19
The column address signal “1” stored in the RAM
12 input terminal RAL and the next is the first digit of the X register, that is, the content of X ₁ is "9"
(“1001”) is read from the RAM 12 and its contents are stored in the buffer register 20. Further, the column address signal "1" is sent to the adder circuit 22 and added to the output "1" of the AND circuit 28, and the added column address signal "2"("0010") is stored in the buffer register 19. It is also stored in the display control buffer register 31. This state is shown in FIG. 4c. As the timing signal _t2 is output, the content "9"("1001") of _X1 stored in the buffer register 20 passes through the adder circuit 22 and is sent to the decoder 30 of the display processing circuit 30. After being _decoded , the segment encoder ₃₀₂ converts it into a display segment signal and supplies it to each digit data input terminal of the display buffer 33. Further, in synchronization with the timing of _t2 · _φ1 , the display clock generating section 32 outputs the display control signal _φD1 corresponding to the column address signal "2", and this is the first signal of the data buffer ₃₃₂ of the display buffer 33. The display segment signals a, b, c, d, f, and g corresponding to the numerical value "9" are sent to the control end of the digit and written into the first digit of the data buffer ₃₃₂ . In this way, the contents of the X register are updated and stored in the display buffer 33 in order from the lower digits. Therefore, the decimal point of the X register, the first
Reading of the digit and second digit is completed, and in the next _D2 , address increment and writing to the display buffer are performed in the same manner as described above. Then, when the column address signal "3" is output from the buffer register 19 to the bus line i during the _D3 period, this column address signal "3" is supplied to the RAM 12, and from the RAM 12, the content "7" of _X3 is output. ” is read out and its content “7” is stored in the buffer register 20, but at this time the column address signal “3” is
Since it matches the contents of S _L of the ROM 11, the output of the matching circuit 23 becomes "1", and the address control signal φ _ROMA is outputted from the NAND circuit 26 in synchronization with the timing of t ₃ ·φ ₁ . As a result, the contents of the address register 13 are updated, and the series of display control operations is completed. In this way, a display control signal is outputted only in response to an arbitrary display digit specified by the address, and it is possible to prevent unnecessary signal output to non-display digits. In the above embodiment, RAM addresses are specified by row and column, but the present invention can also be applied to a one-address system, and the point is to specify the address of the data to be displayed. Any device that generates a display control signal based on at least a portion of the address signal may be used. As described in detail above, according to the present invention, when data to be displayed is transferred from the storage means (RAM) to the display data storage means (display buffer), the address designation means uses a predetermined digit of data stored in the storage means At the same time, the display signal generating means generates a predetermined display control signal corresponding to the address designation, and stores the specified data in a predetermined storage area whose writing is controlled by the display control signal in the display data storage section. This has advantages such as eliminating the output of unnecessary signals, reducing the number of display control signals generated without affecting the display operation, and reducing power consumption. This is more effective because it is only necessary to transfer data of a predetermined digit in a case where the display state changes based on a certain rule, such as timekeeping information.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing one embodiment of the present invention, FIG. 2 is a circuit block diagram showing main parts of the above embodiment, and FIGS. It is an operation explanatory diagram. 11...ROM, 12...RAM, 13...address register, 14...address decoder, 15
...Instruction decoder, 16...Timing counter, 17...Timing decoder,
19, 20... Buffer register, 22... Adder circuit, 23... Matching circuit, 31... Display processing circuit, 32... Buffer register for display control, 34
. . . Display clock generator, 35 . . . Display buffer, 36 . . . Display driver, 37 . . . Display unit.

Claims (1)

[Claims] 1 A storage means for storing data to be displayed, an addressing means for specifying an address for the storage means, and an address specifying means for specifying an address for a predetermined digit of the data stored in the storage means. means for controlling the address designation means, display control signal generation means for outputting a display control signal in accordance with the address designated by the address designation means, and a number of storage areas corresponding to the number of display digits. display data storage means for controlling writing of data addressed by the address designation means using the display control signal and storing the data in a predetermined storage area; and display means for displaying the data stored in the display data storage means. 1. A display control system, comprising: a display control system, wherein only data of a predetermined digit stored in the storage means can be stored in the display data storage means.