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JPS6131620B2 - - Google Patents
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JPS6131620B2 - - Google Patents

Info

Publication number
JPS6131620B2
JPS6131620B2 JP53075786A JP7578678A JPS6131620B2 JP S6131620 B2 JPS6131620 B2 JP S6131620B2 JP 53075786 A JP53075786 A JP 53075786A JP 7578678 A JP7578678 A JP 7578678A JP S6131620 B2 JPS6131620 B2 JP S6131620B2
Authority
JP
Japan
Prior art keywords
metal plate
adhesive layer
lsi
main surface
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53075786A
Other languages
Japanese (ja)
Other versions
JPS553657A (en
Inventor
Tsuyoshi Shiragasawa
Masaharu Noyori
Hiroaki Fujimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7578678A priority Critical patent/JPS553657A/en
Publication of JPS553657A publication Critical patent/JPS553657A/en
Publication of JPS6131620B2 publication Critical patent/JPS6131620B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01Manufacture or treatment
    • H10W70/05Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/941Dispositions of bond pads
    • H10W72/9413Dispositions of bond pads on encapsulations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/10Configurations of laterally-adjacent chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 本発明は電子回路装置に関し、放熱効果の大な
る高密度実装薄形電子回路装置を提供し、特にハ
イパワーの高密度実装薄形電子回路装置の提供を
可能にするものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic circuit device, and provides a high-density-packaged thin electronic circuit device with a large heat dissipation effect, and in particular makes it possible to provide a high-power, high-density-packaged thin electronic circuit device. It is something.

ポリイミドフイルムとメタルフレームを組合せ
た多層配線構造によるLSI高密度実装技術を本出
願人はすでに提案している。すなわち、これは高
密度実装を実現するために、フイルム上に形成さ
れた微細スルーホール(貫通孔)を介してLSI電
極パツドとフイルム上の配線を直接接続するワイ
ヤレスボンデイング技術を用い、さらに多層配線
とするためにメタルフレームを用いたもので、最
小線幅、間隔が50μ程度とでき、LSIチツプ上で
も配線形成を可能にしたもので、高密度でかつ極
めて薄い小型の電子回路実装体を実現したもので
ある。この従来の装置を第1図に示す。
The applicant has already proposed a high-density LSI mounting technology using a multilayer wiring structure combining polyimide film and metal frames. In other words, in order to achieve high-density packaging, this technology uses wireless bonding technology that directly connects the LSI electrode pads and the wiring on the film through fine through holes formed on the film, and also uses multilayer wiring. It uses a metal frame to achieve a minimum line width and spacing of about 50μ, making it possible to form wiring even on LSI chips, realizing a compact electronic circuit package with high density and extremely thinness. This is what I did. This conventional device is shown in FIG.

第1図においてポリイミドフイルム等の絶縁樹
脂フイルム1の第1主面上に形成された導体配線
3と1の第2の主面に接着層6により電子部品
(たとえば半導体集積回路素子)4が取付けられ
ており、更に4の表面電極5は1に形成された貫
通孔2を介して3と電気的に接続がなされ高密度
実装薄形電子回路装置が構成されている。本電子
回路装置の問題点は、半導体チツプ、チツプ抵抗
等の電子部品4が熱伝導率の低い絶縁樹脂フイル
ム1に固着されているために放熱効果が悪く信頼
性の低下をきたし、特にパワー素子を用いたハイ
パワーの高密度実装薄形電子回路の実現が困難で
あつた。
In FIG. 1, conductive wiring 3 formed on the first main surface of an insulating resin film 1 such as a polyimide film and an electronic component (for example, a semiconductor integrated circuit element) 4 are attached to the second main surface of the insulating resin film 1 by an adhesive layer 6. Further, the surface electrode 5 of 4 is electrically connected to 3 through the through hole 2 formed in 1 to constitute a high-density packaging thin electronic circuit device. The problem with this electronic circuit device is that electronic components 4 such as semiconductor chips and chip resistors are fixed to the insulating resin film 1 with low thermal conductivity, which results in poor heat dissipation and reduced reliability, especially for power devices. It has been difficult to realize high-power, high-density, thin electronic circuits using

従来、この問題解決策として第1図に示す如く
前記電子部品4のヒートシンクとなる金属層7を
電子部品基体部から接着層6に至る領域に蒸着等
により形成し、電子部品の放熱効果を高める試み
が行なわれている。しかるにこの方法には、 (1) ヒートシンクとなる金属層の面積は実装電子
〓〓〓〓
回路装置の平面面積に制限され大きな放熱効果
を得ることができない。
Conventionally, as a solution to this problem, as shown in FIG. 1, a metal layer 7 serving as a heat sink of the electronic component 4 is formed by vapor deposition or the like in a region extending from the electronic component base to the adhesive layer 6, thereby enhancing the heat dissipation effect of the electronic component. An attempt is being made. However, in this method, (1) the area of the metal layer that becomes the heat sink is
It is not possible to obtain a large heat dissipation effect because it is limited by the planar area of the circuit device.

(2) 外部ヒートシンク装置への接続が考慮されて
いないため、外部ヒートシンク装置への接続が
困難であり、大きな放熱効果を得ることができ
ない。
(2) Since connection to an external heat sink device is not taken into consideration, connection to an external heat sink device is difficult, and a large heat dissipation effect cannot be obtained.

(3) 複数の電子部品を用いた電子回路装置を実施
する際の電子部品基体部相互の絶縁にはフオト
エツチング等の工程が必要となりコストが高く
なる。
(3) When implementing an electronic circuit device using a plurality of electronic components, a process such as photoetching is required to insulate the electronic component base portions from each other, which increases the cost.

等の欠点がある。There are drawbacks such as.

本発明はこのような問題点に鑑み、放熱効果が
極めてすぐれ、複数の半導体チツプを薄くかつ強
固に実装できる電子回路装置を実現したもので、
本発明の構成を第2図及び第3図に示す実施例を
用いて説明する。
In view of these problems, the present invention has realized an electronic circuit device that has an extremely excellent heat dissipation effect and can mount multiple semiconductor chips thinly and firmly.
The structure of the present invention will be explained using the embodiment shown in FIGS. 2 and 3.

第2図は本発明に用いるLSIチツプと放熱板の
要部を示し、第2図Aは平面図、第2図Bは平面
図における−′線間の断面図を示し第1図と
同一のものは同一番号を付している。第2図にお
いて外部リードを兼用する金属枠体8(ステンレ
ス、ニツケル、コバール等の金属よりなる。)に
よつて支えられた絶縁樹脂フイルム本実施例にお
いてはポリイミドフイルム1の第1の主面に導体
配線3が形成されている。第2の主面にFEP等
の接着層6に依り電子部品、本例においてはLSI
チツプ4が接着固定されている。このチツプ4は
たとえば電力用の素子である。ここで導体配線3
はCr、Cu、Al等の金属よりなる。又電子部品と
してはLSIチツプの他にチツプ抵抗、チツプコン
デンサ及びトランジスタチツプ等もしばしば用い
られる。更に前記LSIチツプ4の表面電極5と前
記導体配線3は、ポリイミドフイルムの一部に設
けられた貫通孔2を介して電気的接続がなされて
いる。なお、この貫通孔2は図のごとくテーパー
状をなし、電気的接続の断線を起りにくくし、信
頼性を高めている。
Fig. 2 shows the main parts of the LSI chip and heat sink used in the present invention, Fig. 2A is a plan view, and Fig. 2B is a sectional view taken along the line -' in the plan view. The items are given the same number. In FIG. 2, an insulating resin film is supported by a metal frame 8 (made of metal such as stainless steel, nickel, or Kovar) that also serves as an external lead. Conductor wiring 3 is formed. An adhesive layer 6 such as FEP is attached to the second main surface to form an electronic component, in this example an LSI.
A chip 4 is fixed with adhesive. This chip 4 is, for example, a power device. Here conductor wiring 3
is made of metals such as Cr, Cu, and Al. In addition to LSI chips, chip resistors, chip capacitors, transistor chips, etc. are often used as electronic components. Furthermore, the surface electrodes 5 of the LSI chip 4 and the conductor wiring 3 are electrically connected through a through hole 2 provided in a portion of the polyimide film. Note that this through hole 2 has a tapered shape as shown in the figure to make electrical connection less likely to break and improve reliability.

次にLSIチツプ4の基体部は導電性接着層9に
依つてヒートシンクとなる金属板10と機械的に
接続されている。ここに用いる導電性接着層とし
て、シリコーン系の銀ペーストを用いると4の基
体部と金属板10とを容易に機械的に接続するこ
とができる。この接続の方法は、接続を所望する
電子部品の基体部又は接続を所望する電子部品の
基体部位置に対応する金属板10上に銀ペースト
等の接着剤を塗布したのちに、電子部品基体部と
金属板10とを貼り合わせれば良い。また金属板
10には厚さ10〜100μm程度のニツケル、コバ
ール又はステンレス等の薄板を用いればよい。
Next, the base portion of the LSI chip 4 is mechanically connected to a metal plate 10 serving as a heat sink by means of a conductive adhesive layer 9. If silicone-based silver paste is used as the conductive adhesive layer used here, the base portion 4 and the metal plate 10 can be easily mechanically connected. This connection method involves applying an adhesive such as silver paste on the base of the electronic component to which connection is desired or on the metal plate 10 corresponding to the position of the base of the electronic component to which connection is desired. and the metal plate 10 may be bonded together. Further, the metal plate 10 may be a thin plate of nickel, kovar, stainless steel, or the like with a thickness of about 10 to 100 μm.

更に第2図から明らかなように金属板10の一
部には外部装置に対する取付部11が設けられて
いる。この取付部11の形状大きさは外部装置に
依つて決まり、取付部11の中央部に取付用の貫
通孔12を設け、該貫通孔部分をねじ止めして取
付けられる様にしてある。又取付部11の部分は
ハンダにより外部装置に取付けてもよい。
Furthermore, as is clear from FIG. 2, a portion of the metal plate 10 is provided with a mounting portion 11 for attaching to an external device. The shape and size of the mounting portion 11 is determined depending on the external device, and a through hole 12 for mounting is provided in the center of the mounting portion 11, and the through hole portion is screwed to allow the mounting. Further, the attachment portion 11 may be attached to an external device using solder.

このようにして、電子部品、即ちLSIチツプ4
の基体部は金属板10に接続され、4に依る発熱
量は10,11を介して外部装置に伝導される。
ここで外部装置としては放熱板又は電子機器装置
のヒートシンク効果の大きな放熱装置が用いられ
る。尚、図において金属板10が折曲げてあるの
は、外部装置の形状に合わせたものである。なお
複数の電子部品を用いる電子回路装置における一
部の電子部分の基体部を、他の電子部品基体部と
電気的に絶縁する必要がある場合は、所望の電子
部品基体部を他の電子部品基体部より薄くして接
着層を付さないか、所望の電子部品基体部を絶縁
樹脂で被覆する等の方法がある。また、本実施例
によれば、複数の電子部品を用いた電子回路装置
を実施する際の電子部品基体部相互の絶縁のため
のフオトエツチング等の工程は不要である。
In this way, the electronic component, that is, the LSI chip 4
The base portion of is connected to a metal plate 10, and the heat generated by 4 is conducted to an external device via 10 and 11.
Here, as the external device, a heat sink or a heat sink device with a large heat sink effect for electronic equipment is used. Note that the metal plate 10 is bent in the figure to match the shape of the external device. In addition, if it is necessary to electrically insulate the base portion of some electronic parts from other electronic component base parts in an electronic circuit device using multiple electronic components, the desired electronic component base part may be insulated from other electronic component base parts. There are methods such as making it thinner than the base portion and not attaching an adhesive layer, or coating the desired electronic component base portion with an insulating resin. Further, according to this embodiment, when implementing an electronic circuit device using a plurality of electronic components, steps such as photoetching for insulating the electronic component base portions from each other are unnecessary.

次に第3図にて本発明の一実施例を説明する。
この例は複数のLSIチツプを用い、所定のLSIチ
ツプのみを放熱用金属板と電気的に、かつ薄形か
つ高密度で強固なLSI実装を可能としたものであ
る。
Next, an embodiment of the present invention will be explained with reference to FIG.
In this example, multiple LSI chips are used, and only a predetermined LSI chip is connected electrically to a metal plate for heat dissipation, making it possible to implement a thin, high-density, and strong LSI.

第3図において、金属枠体8に支持されたポリ
イミドフイルム1の第1主面に形成された導体配
線3は、フイルム1に設けられた貫通孔2を介し
てフイルム1の第2主面に固着されたLSIチツプ
4,4′の表面電極5,5′と電気的に接続されて
いる。この点では第2図の場合と同じである。
In FIG. 3, the conductor wiring 3 formed on the first main surface of the polyimide film 1 supported by the metal frame 8 is connected to the second main surface of the film 1 through the through hole 2 provided in the film 1. It is electrically connected to the surface electrodes 5, 5' of the fixed LSI chips 4, 4'. In this respect, it is the same as the case in FIG.

LSIチツプ4及び4′の基本部はFEP等よりな
る絶縁性接着層13により埋設され、かつ、LSI
チツプ4の基体部裏面の絶縁性接着層13が除去
され、この除去部14に銀ペースト等の導電性接
着層9が設置され、金属板10とチツプ4との電
〓〓〓〓
気的接続がなされている。
The basic parts of the LSI chips 4 and 4' are buried with an insulating adhesive layer 13 made of FEP or the like, and
The insulating adhesive layer 13 on the back surface of the base portion of the chip 4 is removed, and a conductive adhesive layer 9 made of silver paste or the like is placed on this removed portion 14 to reduce the electrical connection between the metal plate 10 and the chip 4.
A physical connection is made.

この第3図の構造の製造は、チツプ4,4′を
フイルム1に固着し、配線3とチツプ4,4′の
電極を接続したのち、チツプ4,4′の周囲なら
びに裏面を絶縁性の接着層13で覆う。この接着
層13としてはFEPの様な熱可塑性のものがよ
い。すなわち、接着層13の埋設は300℃程度に
FEPを加熱してFEPを流体化して行い、冷却固
形化した状態とする。そして、この固形の状態で
チツプ4の裏面の接着層13の一部のみを、酸素
プラズマエツチングで除去する。なお4,4′の
裏面の接着層は薄い方が良く本実施例では10μm
程度である。次に、除去部14に前述の銀ペース
トを設置してチツプ4と金属板10を接続する。
なおこの実施例のLSIチツプ4′は金属板10と
は絶縁する必要があるもので絶縁性接着層13に
て金属板10とは電気的に絶縁されている。
To manufacture the structure shown in FIG. 3, the chips 4, 4' are fixed to the film 1, the wiring 3 and the electrodes of the chips 4, 4' are connected, and then the periphery and back surface of the chips 4, 4' are covered with insulating material. Cover with adhesive layer 13. This adhesive layer 13 is preferably made of thermoplastic material such as FEP. In other words, the adhesive layer 13 is buried at about 300°C.
This is done by heating FEP to make it into a fluid, and then cool it into a solid state. Then, in this solid state, only a part of the adhesive layer 13 on the back surface of the chip 4 is removed by oxygen plasma etching. Note that the adhesive layer on the back side of 4 and 4' should be thinner, and in this example it is 10 μm.
That's about it. Next, the above-mentioned silver paste is placed in the removed portion 14 to connect the chip 4 and the metal plate 10.
The LSI chip 4' of this embodiment needs to be insulated from the metal plate 10, and is electrically insulated from the metal plate 10 by an insulating adhesive layer 13.

第3図において、第2図と同じく金属板10は
絶縁性接着層13と接続されかつLSIチツプ基体
部と一体化され、本電子回路装置を堅固なものに
している。そして金属板10は外部装置に対する
取付部11を有しており、本発明の電子回路装置
の実使用時は、外部リード部8とともに11が外
部装置に接続される。こうしてLSIチツプ4即ち
発熱素子の基体部は金属板10即ちヒートシンク
に接続されており、チツプ4による発熱量は1
0,11を介して外部装置に伝導される。又、
LSIチツプ4′の基体部は、絶縁性接着層13を
介して金属板10に接続されているが、接着層1
3が10μm程度と薄いため、4′に依る発熱量も
10,11を介して外部装置に伝導される。
In FIG. 3, as in FIG. 2, the metal plate 10 is connected to an insulating adhesive layer 13 and integrated with the LSI chip base, making the electronic circuit device rigid. The metal plate 10 has a mounting portion 11 for an external device, and when the electronic circuit device of the present invention is actually used, the metal plate 10 and the external lead portion 8 are connected to the external device. In this way, the base portion of the LSI chip 4, that is, the heat generating element, is connected to the metal plate 10, that is, the heat sink, and the amount of heat generated by the chip 4 is 1.
0,11 to the external device. or,
The base portion of the LSI chip 4' is connected to the metal plate 10 via an insulating adhesive layer 13.
Since 3 is as thin as about 10 μm, the amount of heat generated by 4' is also conducted to the external device via 10 and 11.

なお、本発明にかかる金属板10は任意の個数
設け、発熱用素子のみを効果的に放熱させること
ができる。
Note that any number of metal plates 10 according to the present invention can be provided to effectively dissipate heat from only the heat generating elements.

第3図から明らかなように、半導体集積回路基
体すなわちLSIチツプ4,4′は薄い平板チツプ
状であるため、フイルム1にすべて表面を接着
し、裏面を放熱用金属板10に接着し、チツプ間
のフイルムと金属板の間を接着層13にて埋める
構造を採用している。したがつて、薄い多くの
LSIチツプを均一に全体的に厚くなることなくフ
イルム1と金属板10間に実装でき、かつその実
装状態も強固なものとすることが可能となる。こ
のことは、薄いLSIチツプの特長を損なうことな
く、多くのLSIを高密度かつ薄く強固な実装でき
る点で極めて好都合である。
As is clear from FIG. 3, since the semiconductor integrated circuit substrates, that is, the LSI chips 4, 4', are in the form of thin flat chips, the front surface is adhered to the film 1, the back surface is adhered to the metal plate 10 for heat dissipation, and the chips are A structure is adopted in which the space between the film and the metal plate is filled with an adhesive layer 13. Therefore, many thin
The LSI chip can be uniformly mounted between the film 1 and the metal plate 10 without increasing the overall thickness, and the mounting state can also be made strong. This is extremely advantageous in that many LSIs can be mounted in a high-density, thin, and robust manner without sacrificing the features of thin LSI chips.

以上のように本発明によれば、ヒートシンクと
なる金属板の面積はLSIチツプの平面面積ならび
に数に制限されず任意に選択できるため、大きな
放熱効果を得ることができる。さらに本発明では
ヒートシンクとなる金属板の一部が外部装置に対
する取付部を有するため、大きな放熱効果を得る
ことができ、特にハイパワーの高密度実装薄形電
子回路装置の提供が可能となる。また、本発明は
多くのLSIチツプの放熱構造を有しながらも、均
一かつ強固な薄形実装が可能となり、LSIチツプ
を含む高密度薄形電子回路実装体の応用範囲の拡
大に大きく寄与するものである。
As described above, according to the present invention, the area of the metal plate serving as a heat sink can be arbitrarily selected without being limited by the planar area and number of LSI chips, so that a large heat dissipation effect can be obtained. Furthermore, in the present invention, since a part of the metal plate serving as a heat sink has a mounting portion for an external device, a large heat dissipation effect can be obtained, and in particular, it is possible to provide a high-power, high-density packaging thin electronic circuit device. In addition, the present invention enables uniform and strong thin mounting while having the heat dissipation structure of many LSI chips, and greatly contributes to expanding the range of applications of high-density thin electronic circuit packages including LSI chips. It is something.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のフイルム実装の電子回路装置の
構造断面図、第2図Aは本発明に用いるフイルム
実装電子回路装置の要部平面図、同BはAの−
′線断面図、第3図は本発明の一実施例にかか
るフイルム実装電子回路装置の構造断面図であ
る。 1……絶縁樹脂フイルム、2……絶縁樹脂フイ
ルム貫通孔、3……導体配線、4,4′……電子
部品(LSIチツプ)、5……電子部品の表面電
極、6……接着層、8……金属枠体、9……導電
性接着層、10……金属板、11……取付部、1
2……取付部貫通孔、13……絶縁性接着層。 〓〓〓〓
FIG. 1 is a structural sectional view of a conventional film-mounted electronic circuit device, FIG. 2A is a plan view of the main part of the film-mounted electronic circuit device used in the present invention, and FIG.
3 is a structural sectional view of a film-mounted electronic circuit device according to an embodiment of the present invention. 1... Insulating resin film, 2... Insulating resin film through hole, 3... Conductor wiring, 4, 4'... Electronic component (LSI chip), 5... Surface electrode of electronic component, 6... Adhesive layer, 8... Metal frame, 9... Conductive adhesive layer, 10... Metal plate, 11... Mounting part, 1
2... Attachment portion through hole, 13... Insulating adhesive layer. 〓〓〓〓

Claims (1)

【特許請求の範囲】[Claims] 1 一方の主面に配線用金属層が選択的に形成さ
れた耐熱性絶縁基板の他方の主面に、接着層を介
して電極を有する複数の半導体集積回路基体の一
方の主面が固着され、前記基体の電極と前記配線
用金属層とが前記絶縁基板に形成された貫通孔を
介して電気的に接続され、前記複数の半導体集積
回路基体の他方の主面が放熱用金属板に固着さ
れ、この金属板の一部に外部への接続用取付部を
設け、前記複数の半導体集積回路基体と金属板間
に絶縁性又は導電性接着層が充填されて、前記複
数の半導体集積回路基体の間の前記絶縁基板と金
属板間に、絶縁性接着層が設置されてなることを
特徴とする電子回路装置。
1 One main surface of a plurality of semiconductor integrated circuit substrates having electrodes is fixed to the other main surface of a heat-resistant insulating substrate on which a wiring metal layer is selectively formed on one main surface via an adhesive layer. , the electrodes of the substrate and the wiring metal layer are electrically connected through through holes formed in the insulating substrate, and the other main surface of the plurality of semiconductor integrated circuit substrates is fixed to a heat dissipation metal plate. A mounting portion for connection to the outside is provided in a part of the metal plate, and an insulating or conductive adhesive layer is filled between the plurality of semiconductor integrated circuit substrates and the metal plate, so that the plurality of semiconductor integrated circuit substrates An electronic circuit device characterized in that an insulating adhesive layer is provided between the insulating substrate and the metal plate.
JP7578678A 1978-06-21 1978-06-21 Electronic circuit device Granted JPS553657A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7578678A JPS553657A (en) 1978-06-21 1978-06-21 Electronic circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7578678A JPS553657A (en) 1978-06-21 1978-06-21 Electronic circuit device

Publications (2)

Publication Number Publication Date
JPS553657A JPS553657A (en) 1980-01-11
JPS6131620B2 true JPS6131620B2 (en) 1986-07-21

Family

ID=13586235

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7578678A Granted JPS553657A (en) 1978-06-21 1978-06-21 Electronic circuit device

Country Status (1)

Country Link
JP (1) JPS553657A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021192172A1 (en) * 2020-03-26 2021-09-30 太陽誘電株式会社 Power module and production method for same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5722441Y2 (en) * 1974-02-27 1982-05-15
JPS52152672U (en) * 1976-05-14 1977-11-18
JPS52141566A (en) * 1976-05-20 1977-11-25 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacture

Also Published As

Publication number Publication date
JPS553657A (en) 1980-01-11

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