JPS6131634B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a junction field effect transistor (J-
The present invention relates to a method for manufacturing a semiconductor device in which a bipolar transistor (FET) and a bipolar transistor are integrated into the same chip, and it realizes the following features.

Compared to normal bipolar ICs, only one additional mask alignment process and one impurity introduction process are required.

The characteristics of the J-FET and the characteristics of the bipolar transistor can be controlled independently.

The channel width of a J-FET does not depend on the epitaxial growth layer thickness.

The J-FET channel is far from the silicon surface and is free of noise due to surface phenomena.

First, conventional methods for obtaining a J-FET and a bipolar transistor in the same chip are: Conventional Example 1: Utilizing the P-type base layer b directly under the emitter e diffusion of the transistor as channel ch ₁ . things (first
figure).

Conventional Example 2 A thin channel region ch ₂ near the surface (Fig. 2).

Conventional Example 3 A narrow region of the epitaxial layer sandwiched between the substrate and the diffusion is used as channel ch ₃ (Fig. 3).

etc., but each has the following drawbacks. In addition, in Figures 1, 2, and 3, S and D are
Source formed by selectively removing SiO ₂ film,
This is the drain electrode.

Now, the channel width of the J-FET of conventional example 1 is
〓〓〓〓
It is determined as the difference between the base diffusion depth and
Therefore, the controllability of the channel width is poor, and the variation in I _DSS is large. In addition, since the channel part is also the base of the npn transistor, the optimal conditions for a J-FET and the optimal conditions for an npn bipolar transistor do not match, so either one of the characteristics must be sacrificed or an appropriate compromise must be made. I have no choice but to design it.

Conventional Example 2 avoids the drawbacks mentioned above in Conventional Example 1 because a shallow channel layer is formed near the surface, but since the channel is formed near the surface, noise is generated due to surface phenomena. This halves the J-FET's advantage of inherently low noise due to the use of multiple carriers.

In Conventional Example 3, the channel width of the J-FET uses the difference between the epitaxial thickness and the diffusion depth, so variations in each result in variations in the channel width, poor controllability of the channel width, and I _DSS .
There is also large variation.

In view of the above-mentioned circumstances, the present invention proposes a structure that realizes the above-mentioned features, and will be described in detail below using examples.

4A to 4G are cross-sectional views showing an outline of a process for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 5 is a conceptual plan view of the same embodiment.

The manufacturing process will be explained below in order. In this example
Both the npn transistor and the p-ch J-FET are formed on the left and right sides, respectively, and are separated from each other.
In FIG. 4A, 1 is a P-type silicon substrate,
It contains about 1×10 ¹⁵ cm ^-3 of boron as an impurity. Using the oxide film 21 as a mask, apply antimony 2×
N ⁺ type buried layers 3 and 4 containing about 10 ¹⁹ cm ^-3 are formed.

Next, as shown in the same figure B, regions 5 and 6 containing boron of about 1×10 ¹⁷ cm ^-3 using the oxide film 22 as a mask.
form. 5 is formed within the n ⁺ type region 3, so it does not invert to the P type. Also, since it is formed within a P-type substrate, it remains P-type.

Next, as shown in Figure C, 1×10 ¹⁶ cm of phosphorus was applied to the entire surface.
An n-type epitaxial layer 7 having a thickness of about 3μ including about ^-3 is formed.

Next, as shown in FIG. D, a P-type region 8 containing boron of ^about 2×10 ¹⁸ cm
Form 9 and 10. At this time, boron is diffused into the epitaxial layer 7 from regions 5 and 6 by the drive-in process, forming P-type regions 51 and 61, respectively. The thickness of 51 and 61 is about 0.5μ, and the diffusion depth of P-type regions 8, 9, and 10 is all 2.5μ~
3.0μ, 8 and 9 are connected to both ends of 51, and 10 is connected to 61. 5
1 is the channel region of the J-FET, 8 and 9 are the source and drain parts, respectively, and the p-ch J-FET
An isolation region is formed by 61 and 10, and each island region is electrically isolated. At this time, the buried layers 3 and 4 contain a high concentration of impurities,
Since the impurity is antimony and the diffusion coefficient is smaller than that of boron, the epitaxial layers 71 and 72
The spread to is negligible.

Next, as shown in FIG. E, a region 11 containing about 5×10 ¹⁸ boron is formed using the oxide film 24 as a mask. The diffusion depth of No. 11 is about 1.5μ, and npn
It becomes the base of the transistor.

Next, ^as shown in ^FIG .
3 and 14 are formed. 12 is a P-type base region 11
It is formed inside the emitter, and 13, 14
are n ⁺ diffusions for contact extraction for n-type regions 71 and 72, respectively.

After that, as shown in FIG. G, the electrodes 15, 16, 17, 18,
20 are attached and serve as the source, drain, and gate electrodes of the J-FET, and the emitter, base, and collector electrodes of the NPN transistor, respectively.

A conceptual plan view of the structure shown in FIG. 4 is shown in FIG. Since the numbers in the figure correspond to those in FIG. 4, the explanation will be omitted.

In addition, in FIG. 4C, the epitaxial layer 7
At the time of formation, HCl etching or the like is performed to improve the crystallinity, thereby changing the amount of poron in the boron-containing regions 5 and 6, which may impair the controllability of the channel width or I _DSS . One way to improve this is to implant boron ions into the regions 5 and 6 so that the peak of the impurity distribution is located slightly inside the surface.

As explained in the above embodiments, the present invention is a low concentration thin layer formed by reactive conductive impurities that diffuse into the epitaxial growth layer from a buried region containing a high concentration of impurities with a small diffusion coefficient. De Chiyane〓〓〓〓
This area forms the main area.

As can be seen from the above description of the embodiments, the present invention requires only one additional masking process and one impurity introduction process compared to a normal bipolar IC, and the J-
FET characteristics can be controlled. Further, according to the present invention, the channel width is determined by a single diffusion step, and variations in the thickness of the epitaxial layer do not affect I _DSS . Since the channel is away from the surface, there is no noise generation due to surface phenomena, and the present invention is suitable for use in semiconductor integrated circuits.
This will greatly contribute to the creation of FETs.

[Brief explanation of the drawing]

1 to 3 are cross-sectional views of conventional J-FET structural examples, FIGS. 4A to 4G are manufacturing process diagrams of a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. FIG. 2 is a conceptual plan view of an embodiment of the invention. 1... P-type silicon substrate, 3... Buried layer containing antimony, 5... Region containing boron, 7...
...N-type epitaxial layer, 8,9...P-type region,
51...P-type area (channel area). 〓〓〓〓〓

Claims (1)

[Scope of Claims] 1. A first buried region containing a high concentration of a first impurity of one conductivity type is selectively formed in a semiconductor substrate from one main surface thereof, and the first buried region a second buried region selectively containing a second impurity of the other conductivity type having a larger diffusion coefficient than the first impurity; forming a channel region of a junction field effect transistor comprising a low concentration diffusion layer formed by the second impurity diffused into the epitaxial growth layer; A source, a drain region, and an isolation region of the junction field effect transistor are selectively formed from the surface of the layer, and a bipolar transistor is formed in a portion of the epitaxial growth layer other than the junction field effect transistor formation region. A method for manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first impurity is antimony and the second impurity is boron.