JPS6131655B2 - - Google Patents
Info
- Publication number
- JPS6131655B2 JPS6131655B2 JP5039477A JP5039477A JPS6131655B2 JP S6131655 B2 JPS6131655 B2 JP S6131655B2 JP 5039477 A JP5039477 A JP 5039477A JP 5039477 A JP5039477 A JP 5039477A JP S6131655 B2 JPS6131655 B2 JP S6131655B2
- Authority
- JP
- Japan
- Prior art keywords
- pulse amplitude
- output
- signal
- equalization circuit
- amplitude modulation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- 230000005540 biological transmission Effects 0.000 claims description 24
- 230000004044 response Effects 0.000 claims description 14
- 230000003111 delayed effect Effects 0.000 claims description 3
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 7
- 238000005070 sampling Methods 0.000 description 7
- 239000000969 carrier Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000010363 phase shift Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03114—Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals
- H04L25/03133—Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals with a non-recursive structure
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Filters And Equalizers (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Description
【発明の詳細な説明】
本発明は、直交多重信号の受信器における等化
器に関し、特に複数個のベースバンドPAM信号
(パルス振幅変調信号)が各々周波数又は位相の
異つたキヤリアで変調され、これら被変調信号を
全て加え合わせた信号が直交多重されたQAM信
号(直交振幅変調信号)となる直交多重信号の受
信器における等化器に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an equalizer in a receiver for orthogonal multiplexed signals, and in particular, a plurality of baseband PAM signals (pulse amplitude modulation signals) are modulated with carriers having different frequencies or phases, The present invention relates to an equalizer in a receiver for orthogonally multiplexed signals, in which a signal obtained by adding all these modulated signals becomes an orthogonally multiplexed QAM signal (quadrature amplitude modulated signal).
直交多重されたQAM信号の送受信方式につい
ては、昭和51年特許願68523号にて詳細に述べら
れている。即ち、送信側においては第1図に示す
如く、以下に述べる過程で直交多重信号を生成す
る。 The transmitting and receiving method of orthogonally multiplexed QAM signals is described in detail in Patent Application No. 68523 of 1978. That is, on the transmitting side, as shown in FIG. 1, an orthogonal multiplexed signal is generated in the process described below.
第1図において、入力端11〜12Nにはクロツ
ク周期T秒で互いに同期のとれた2N個のデータ
の組{a(1)k},{a(2)k},…,{a(2N) k}
(但しk=
−∝,…,−1,0,1,……+∝}によつてパ
ルス振幅変調を受けたパルス振幅変調信号α1
(t),α2(t),……α2N(t)が印加され
る。入力端11,12,…1Nに加えられたN個
パルス振幅変調信号α1(t),…αN(t)は
各々31,32,…3Nで表わされる互いに周波
数応答特性が等しく且つ2個継続接続した時その
伝達特性がナイキスト条件を満たすN個のベース
バンドフイルタに入力される。一方入力端1N+
1,1N+2,……12Nに加えられた他のN個のパ
ルス振幅変調信号αN+1(t),…,α2N(t)は
各々2N+1,2N+2,…22Nで表わされるN個の遅
延素子を介してT/2秒の遅延を受けた後、前記
N個のベースバンドフイルタと周波数応答特性の
等しい他のN個のベースバンドフイルタ3N+1,
3N+2,…32Nに入力される。更に前記N個のベ
ースバンドフイルタ31,32,…3Nの出力β
1(t),β2(t)…,βN(t)は、各々N個
の変調器41+42,…,4Nにおいて、各々
cosω1t,sinω2t,cosω3t,…sinωNtで表わさ
れるキヤリアで変調される。(但しωl−ωl-1=2
π/T,またここでは説明の便宜上Nは偶数と考
える)更に前記、他のN個のベースバンドフイル
タ3N+1,3N+2,…32Nの出力βN+1(t),βN+2
(t),…,β2N(t)は各々他のN個の変調器4
N+1,4N+2,…,42Nにおいて各々sinω1t,cos
ω2t,sinω3t,…,cosωNtで表わされるキヤリ
アで変調される。2N個の変調器41,42,
…,42Nの出力は加算器5によつて全て加算され
た後、出力端6から伝送路へ送出される。 In FIG. 1, input terminals 1 1 to 1 2N have 2N data sets {a(1) k }, {a(2) k }, ..., {a (2N) k }
(However, k=
-∝,...,-1,0,1,...+∝} Pulse amplitude modulated signal α 1
(t), α 2 (t), ... α 2N (t) are applied. The N pulse amplitude modulated signals α 1 (t), ... α N (t) applied to the input terminals 1 1 , 1 2 , ... 1 N have mutual frequency response characteristics expressed by 3 1 , 3 2 , ... 3N, respectively. are equal and two are continuously connected, their transfer characteristics are input to N baseband filters that satisfy the Nyquist condition. One input end 1 N+
The other N pulse amplitude modulation signals α N+1 ( t), ..., α 2N (t) added to 1 , 1 N+2 , ...1 2N are 2 N+1 , 2 N+2 , respectively . ,...2 After receiving a delay of T/2 seconds through N delay elements represented by 2N , other N baseband filters 3 N+ having the same frequency response characteristics as the N baseband filters are applied. 1 ,
3 N+2 ,...3 Input to 2N . Furthermore, the output β of the N baseband filters 3 1 , 3 2 ,...3 N
1 (t), β 2 (t)..., β N ( t ) are respectively
It is modulated by carriers expressed as cosω 1 t, sinω 2 t, cosω 3 t, ...sinω N t. (However, ω l −ω l-1 = 2
π/T, and here N is assumed to be an even number for convenience of explanation) Further, the outputs β N+1 (t) of the other N baseband filters 3 N+1 , 3 N+2 , ...3 2N , β N+2
(t), ..., β 2N (t) are each other N modulators 4
sinω 1 t, cos at N+1 , 4 N+2 ,…, 4 2N respectively
It is modulated by carriers expressed as ω 2 t, sin ω 3 t, ..., cosω N t. 2N modulators 4 1 , 4 2 ,
..., 4 2N are all added together by an adder 5, and then sent from an output end 6 to a transmission line.
第2図に示すように、受信側では、前記送信側
に対する逆変換を行うことにより元データを復元
する。即ち第2図において、入力端11には伝送
路を介して伝送された直交多重信号が印加され、
この直交多重信号は2N個の復調器121,12
2,…122Nにおいて各々cosω1t,sinω2t,cos
ω3t,…sinωNt,sinω1t,cosω3t,…,cosωN
tにより復調される。2N個の復調器121,1
22,…122Nの出力は各々前記送信側ベースバ
ンドフイルタと同一の周波数応答特性を有する
2N個のベースバンドフイルタ131,132,
…132Nに入力される。この2N個のベースバン
ドフイルタ131,132,…132Nの出力のう
ち131,132,…13Nの出力は各々、14
1,142,…14Nで表わされる遅延素子を介
してT秒の遅延を受けた後、各々出力端151,
152,……15Nに印加され、他のベースバン
ドフイルタ13N+1,13N+2,…132Nの出力は
14N+1,14N+2,…142Nで表わされる遅延素
子を介して、T/2秒だけ遅延を受けた後、各々
出力端15N+1,15N+2,…152Nに印加され
る。このようにして出力端151,152,…1
52Nに得られた信号γ1(t),γ2(t),…,
γ2N(t)を適当な時刻でサンプリングすれば
2N個の元データの組{a(1)k},{a(2)k},…{a
(2N) k}が復元される。 As shown in FIG. 2, the receiving side restores the original data by performing inverse transformation to the transmitting side. That is, in FIG. 2, an orthogonal multiplexed signal transmitted via a transmission path is applied to the input end 11,
This orthogonal multiplexed signal is transmitted to 2N demodulators 12 1 , 12
2 ,...12 2N , cosω 1 t, sinω 2 t, cos
ω 3 t,…sinω N t, sinω 1 t, cosω 3 t,…, cosω N
It is demodulated by t. 2N demodulators 12 1 , 1
The outputs of 2 2 ,...12 2N each have the same frequency response characteristics as the transmitting baseband filter.
2N baseband filters 13 1 , 13 2 ,
...13 Input to 2N . Out of the outputs of these 2N baseband filters 13 1 , 13 2 , ... 13 2N , the outputs of 13 1 , 13 2 , ... 13 N are 14
After receiving a delay of T seconds through delay elements denoted by 1 , 14 2 , . . . 14 N , the output terminals 15 1 , .
15 2 ,...15 N , and the outputs of other baseband filters 13 N+1 , 13 N+2 ,...13 2N are delay elements represented by 14 N+1 , 14 N+2 ,...14 2N are applied to the respective outputs 15 N+1 , 15 N+2 , . . . 15 2N after a delay of T/2 seconds. In this way, the output ends 15 1 , 15 2 ,...1
Signals γ 1 (t), γ 2 (t), ..., obtained at 5 2N
If we sample γ 2N (t) at an appropriate time, we get
A set of 2N original data {a(1) k }, {a(2) k }, ... {a
(2N) k } is restored.
以上の説明は伝送路に歪の無い場合であるが、
一般には、伝送路は必ず何らかの歪を有するた
め、受信側でこの歪に対応した等化を行い歪を除
去しなければならない。 The above explanation assumes that there is no distortion in the transmission path, but
Generally, since a transmission path always has some kind of distortion, it is necessary to perform equalization corresponding to this distortion on the receiving side to remove the distortion.
この目的で使用される等化器としては、第2図
の入力端11と信号分岐点16の間に挿入される
帯域通過形等化器が考えられる。しかしながら、
このような帯域通過形等化器は、全信号伝送帯域
を等化する必要があるため帯域通過形等化器とし
て用いられるバンドパスフイルタの比帯域が大き
くなり、等化精度を上げる事が難かしい。更に、
一般に帯域通過形の伝送路を用いる場合、帯域の
両端で歪が増大し、帯域の中心近傍では比較的歪
が小さい事が多い。このような伝送路に対して
は、全帯域を等化する帯域通過形等化器は甚だ非
能率な等化器となる恐れがある。 As an equalizer used for this purpose, a band-pass equalizer inserted between the input terminal 11 and the signal branch point 16 in FIG. 2 can be considered. however,
Such a band-pass equalizer needs to equalize the entire signal transmission band, so the band-pass filter used as the band-pass equalizer has a large fractional band, making it difficult to improve equalization accuracy. That's funny. Furthermore,
Generally, when a bandpass type transmission line is used, distortion increases at both ends of the band, and distortion is often relatively small near the center of the band. For such a transmission path, a bandpass type equalizer that equalizes the entire band may become a very inefficient equalizer.
本発明の目的は帯域形等化器の以上の欠点を鑑
み、ベースバンド等化器を可能とする新規なる直
交多重信号の受信器における等化器を提供するも
のである。 SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks of the band type equalizer, an object of the present invention is to provide a new equalizer in a receiver for orthogonal multiplexed signals, which enables a baseband equalizer.
第3図は前記の直交多重信号伝送系の等価伝送
路モデルである。第3図において例えばkを奇数
として101および102は、各々第1図の(N
+k−1)番目の入力端1N+k-1および(k+
1)番目の入力端1k-1に対応する入力端であ
り、141および142は、各々第2図の(N+
k−1)番目の出力端15N+k-1および(k−
1)番目の出力端15k-1に対応する出力端であ
り、201および202は各々第1図のk番目の
入力端1kおよび(N+k)番目の入力端1N+k
に対応する入力端であり、241および242は
各々第2図のk番目の出力端15kおよび(N+
k)番目の出力端15N+kに対応する出力端であ
り、301および302は各々第1図の(N+k
+1)番目の入力端1N+k+1および(k+1)番
目の入力端1k+1に対応する入力端であり、34
1および342は各々第2図の(N+k+1)番
目の出力端15N+k+1および(k+1)番目の出
力端15k+1に対応する出力端であり、103,
114,123,204,213,224,30
3,314,323は全て、T/2秒の時間遅れ
を与える時間遅れ回路、104,113,12
4,203,214,223,304,313,
324は全てT/2秒の時間進みを与える時間進
み回路、105〜108および115〜118お
よび125〜128および205〜208および
215〜218および225〜228および30
5〜308および315〜318および325〜
328は等価ベースバンド伝送路であり、10
9,110,119,120,129,130,
131,132,209,210,219,22
0,229,230,231,232,309,
310,319,320,329,330,33
1,332,は全て複数個の入力信号を図中の極
性符号+,−に従つて加算回路である。また20
で示される破線内は、出力端241および242
に得られる出力信号対に寄与する部分を示してい
る。 FIG. 3 is an equivalent transmission line model of the above-mentioned orthogonal multiplex signal transmission system. In FIG. 3, for example, if k is an odd number, 101 and 102 are respectively (N
+k-1)th input end 1 N+k-1 and (k+
1) is the input terminal corresponding to the input terminal 1 k-1 , and 141 and 142 are the input terminals corresponding to (N+
k-1)th output end 15 N+k-1 and (k-
1) An output terminal corresponding to the 15th output terminal 15k -1 , and 201 and 202 are the k-th input terminal 1k and the (N+k)th input terminal 1 N+k in FIG. 1, respectively.
241 and 242 are the input terminals corresponding to the k-th output terminals 15k and (N+
k)th output terminal 15 N+k , and 301 and 302 are the output terminals corresponding to (N+k) in FIG.
+1)th input terminal 1 N+k+1 and (k+1)th input terminal 1 k+1 , which corresponds to 34
1 and 342 are output ends corresponding to the (N+k+1)th output end 15 N+k+1 and the (k+1)th output end 15 k+1 in FIG. 2, respectively;
114, 123, 204, 213, 224, 30
3, 314, and 323 are all time delay circuits that provide a time delay of T/2 seconds; 104, 113, and 12;
4,203,214,223,304,313,
324 are time advance circuits all giving a time advance of T/2 seconds, 105-108 and 115-118 and 125-128 and 205-208 and 215-218 and 225-228 and 30
5-308 and 315-318 and 325-
328 is an equivalent baseband transmission line, and 10
9,110,119,120,129,130,
131, 132, 209, 210, 219, 22
0,229,230,231,232,309,
310, 319, 320, 329, 330, 33
1 and 332 are adder circuits that add a plurality of input signals according to the polarity codes + and - in the figure. 20 again
The dashed lines indicated by are the output terminals 241 and 242.
The portions that contribute to the output signal pair obtained in the figure are shown.
いま、第1図の31などで表わされるベースバ
ンドフイルタの伝達関数をG(ω)とし、直交多
重信号の伝送される伝送路の伝達関数をQ(ω)
とすれば、第3図の125および128で表わさ
れる等価ベースバンド伝送路の伝達関数をS1
(ω),126および127で表わされる等価ベー
スバンド伝送路の伝達関数をS2(ω)、215お
よび218で表わされる等価ベースバンド伝送路
の伝達関数をP1(ω)、216および217で表
わされる等価ベースバンド伝送路の伝達関数をP2
(ω)、315および318で表わされる等価ベー
スバンド伝送路の伝達関数をR1(ω)、316お
よび317で表わされる等価ベースバンド伝送路
の伝達関数をR2(ω)とした時、
P1(ω)=1/2・G2(ω)〔Q(ω+ωk)
e-j〓+Q(ω−ωk)ej〓〕 ……(1)
P2(ω)=j/2・G2(ω)〔Q(ω+ωk)
e-j〓−Q(ω−ωk)ej〓〕 ……(2)
R1(ω)=1/2・G(ω)〔G(ω−ω0)Q
(ω+ωk)e-j〓+G(ω+ω0)
Q(ω−ωk)ej〓〕 ……(3)
R2(ω)=j/2・G(ω)〔G(ω−ω0)Q
(ω+ωk)e-j〓−G(ω+ω0)
Q(ω−ωk)ej〓〕 ……(4)
S1(ω)=1/2・G(ω)〔G(ω+ω0)Q
(ω+ωk)e-j〓+G(ω−ω0)
Q(ω−ωk)ej〓〕 ……(5)
S2(ω)=j/2・G(ω)〔G(ω+ω0)Q
(ω+ωk)e-j〓−G(ω−ω0)
Q(ω−ωk)ej〓〕 ……(6)
と表わされる。但しω0=2π/Tであり、θは
復調キヤリアcosωktおよびsinωktの位相ずれ
であり、jは虚数単位を表わす。 Let G(ω) be the transfer function of the baseband filter represented by 31 in Fig. 1, and let Q(ω) be the transfer function of the transmission path through which the orthogonal multiplexed signal is transmitted.
Then, the transfer function of the equivalent baseband transmission path represented by 125 and 128 in FIG .
The transfer function of the equivalent baseband transmission path represented by (ω), 126 and 127 is S 2 (ω), and the transfer function of the equivalent baseband transmission path represented by 215 and 218 is P 1 (ω), 216 and 217. The transfer function of the equivalent baseband transmission path expressed as P 2
(ω), the transfer function of the equivalent baseband transmission path represented by 315 and 318 is R 1 (ω), and the transfer function of the equivalent baseband transmission path represented by 316 and 317 is R 2 (ω), then P 1 (ω)=1/2・G 2 (ω) [Q(ω+ω k ) e -j 〓+Q(ω−ω k )e j 〓] ...(1) P 2 (ω)=j/2・G 2 (ω) [Q (ω + ω k ) e -j 〓-Q (ω - ω k ) e j 〓] ...(2) R 1 (ω) = 1/2・G (ω) [G (ω −ω 0 )Q (ω+ω k )e -j 〓+G(ω+ω 0 ) Q(ω−ω k )e j 〓] ...(3) R 2 (ω)=j/2・G(ω)[G (ω−ω 0 )Q (ω+ω k )e -j 〓−G(ω+ω 0 ) Q(ω−ω k )e j 〓〕 ……(4) S 1 (ω)=1/2・G(ω ) [G(ω+ω 0 )Q (ω+ω k )e -j 〓+G(ω-ω 0 ) Q(ω-ω k )e j 〓] ...(5) S 2 (ω)=j/2・G (ω) [G(ω+ω 0 )Q (ω+ω k )e -j 〓-G(ω-ω 0 ) Q(ω-ω k )e j 〓] ...(6). However, ω 0 =2π/T, θ is a phase shift between demodulated carriers cosω k t and sin ω k t, and j represents an imaginary unit.
本発明による直交多重信号受信器における等化
器は、第3図の出力端241,242にて得られ
る出力信号に対しベースバンド等化を行うもので
ある。 The equalizer in the orthogonal multiplex signal receiver according to the present invention performs baseband equalization on the output signals obtained at the output terminals 241 and 242 in FIG.
第4図a,bに、本発明による直交多重信号受
信器における等化器の実施例を示す。なお第4図
a,bは各々後述のように等化すべきチヤンネル
によつてこの二種類を使い分ける。 4a and 4b show an embodiment of an equalizer in an orthogonal multiplex signal receiver according to the present invention. Note that in FIGS. 4a and 4b, these two types are used depending on the channels to be equalized, as will be described later.
まず、第4図aにおいて、251および252
は各々第3図の出力端241および242に接続
される入力端子、261および262は出力端
子、270および71および272は全てT/2
秒遅延を与えるT/2遅延回路273はT秒遅延
を与えるT遅延回路、274は第一の等化回路、
275は第二の等化回路、276は該第二の等化
回路、275と同一の周波数応答特性を有する第
三の等化回路、277は前記第一の等化回路27
4と同一の周波数応答特性を有する第四の等化回
路278は前記第一の等化回路274の出力から
前記第二の等化回路275の出力を減ずる減算回
路、279は前記第三の等化回路276の出力
と、前記第四の等化回路277の出力とを加算す
る加算回路を表わす。入力端251に印加された
信号は270および271で表わされるT/2遅
延回路を介して総計T秒の遅延を受けた後、第一
の等化回路274により等化され減算器278の
第一の入力となる。他方入力端252に印加され
た信号はT遅延回路273およびT/2遅延回路
272を介して総計3T/2秒の遅延を受けた後
275で示される第二の等化回路275により等
化され減算器278の第二の入力となる。減算器
278の第二の入力となる。減算器278は該第
一の入力から該第二の入力を減算し出力端261
に第一の等化信号xk(t)を出力する。また、
入力端252に印加された信号はT遅延回路27
3を通過した後分岐して、第四の等化回路277
で等化され加算器279の第一の入力となる。他
方251に印加された信号はT/2遅延回路27
0を通過した後第三の等化回路276で等化され
加算器279の第二の入力となる。加算器279
は該第一の入力と該第二の入力とを加算し出力端
262に第二の等化信号xk+N(t)を出力す
る。なお、第一の等化回路と第四の等化回路の伝
達関数をC1(ω)、第二の等化回路と第三の等化
回路の伝達関数C2(ω)は伝送路歪に対応して
概略次式で与えられるものとする。 First, in FIG. 4a, 251 and 252
are input terminals connected to output terminals 241 and 242 in FIG. 3, respectively, 261 and 262 are output terminals, and 270, 71, and 272 are all T/2
A T/2 delay circuit 273 that provides a second delay is a T delay circuit that provides a T second delay, 274 is a first equalization circuit,
275 is a second equalization circuit, 276 is the second equalization circuit, a third equalization circuit having the same frequency response characteristics as 275, and 277 is the first equalization circuit 27.
A fourth equalization circuit 278 having the same frequency response characteristic as 4 is a subtraction circuit that subtracts the output of the second equalization circuit 275 from the output of the first equalization circuit 274; It represents an adder circuit that adds the output of the equalization circuit 276 and the output of the fourth equalization circuit 277. The signal applied to the input terminal 251 is delayed for a total of T seconds through T/2 delay circuits 270 and 271, and then equalized by the first equalization circuit 274 and output to the first subtracter 278. becomes the input. The signal applied to the other input terminal 252 is delayed for a total of 3T/2 seconds via a T delay circuit 273 and a T/2 delay circuit 272, and then is equalized by a second equalization circuit 275 indicated by 275. This becomes the second input of subtractor 278. This becomes the second input of subtractor 278. The subtractor 278 subtracts the second input from the first input and outputs the output terminal 261.
The first equalized signal x k (t) is outputted to. Also,
The signal applied to the input terminal 252 is transmitted to the T delay circuit 27.
3 and then branches to the fourth equalization circuit 277.
and becomes the first input of the adder 279. The signal applied to the other 251 is the T/2 delay circuit 27
After passing through 0, it is equalized by a third equalization circuit 276 and becomes the second input of an adder 279. Adder 279
adds the first input and the second input and outputs a second equalized signal x k+N (t) at the output terminal 262. The transfer function of the first equalization circuit and the fourth equalization circuit is C 1 (ω), and the transfer function of the second equalization circuit and the third equalization circuit C 2 (ω) is the transmission line distortion. Corresponding to , it is roughly given by the following equation.
C1(ω)=Q(ω+ωk)e−j〓+Q(ω−ωk)ej〓/2Q(ω+ωk)・Q(ω−ωk) ……(7)
C2(ω)=−j〔Q(ω+ωk)e−j〓−Q(ω−ωk)ej〓〕/2Q(ω+ωk)・Q(ω−ωk)…
…(8)
第4図aで表わされる本発明による直交多重信
号受信器における等化器の入力端251,252
を各々第3図に示した等価伝送モデルの出力端2
41,242に接続すると、第3図の入力端20
1から第4図aの出力端261までの伝達関数
H1(ω)は(1)〜(8)式を用いて以下のように表わ
される。(但しT秒の線形遅延分は除いて考え
る)
同様にして第3図の入力端202から第4図a
の出力端262までの伝達関数H2(ω)は、
となる。ここで、伝達係数H1(ω)の時間応答
をh1(t)とすれば、よく知られているように、
t1(t)はH1(ω)のフーリエ逆変換として与え
られる。即ち、
h1(t)=1/2π∫∞ −∞H1(ω)ej〓tdω
従つて、時刻nTにおけるh1(t)の標本値h1
(nT)は、
h1(nT)=1/2π∫∞ −∞H1(ω)ej〓nTdω
と表わされるが、関数ej〓nTのωに関する周期
性に着目すれば上式は次のように変形される。 C 1 (ω)=Q(ω+ω k )e −j 〓+Q(ω−ω k )e j 〓/2Q(ω+ω k )・Q(ω−ω k ) ……(7) C 2 (ω)= −j[Q(ω+ ωk )e −j 〓−Q(ω− ωk )e j 〓]/2Q(ω+ ωk )・Q(ω− ωk )…
...(8) Input terminals 251, 252 of the equalizer in the orthogonal multiple signal receiver according to the present invention shown in FIG. 4a
Output terminal 2 of the equivalent transmission model shown in Figure 3.
41, 242, the input terminal 20 in FIG.
Transfer function from 1 to the output end 261 of Fig. 4a
H 1 (ω) is expressed as follows using equations (1) to (8). (However, consider excluding the linear delay of T seconds) Similarly, from the input terminal 202 in FIG. 3 to the input terminal 202 in FIG.
The transfer function H 2 (ω) to the output end 262 of becomes. Here, if the time response of the transfer coefficient H 1 (ω) is h 1 (t), then as is well known,
t 1 (t) is given as the inverse Fourier transform of H 1 (ω). That is, h 1 (t)=1/2π∫ ∞ −∞ H 1 (ω)e j 〓 t dω Therefore, the sample value h 1 of h 1 (t) at time nT
(nT) is expressed as h 1 (nT)=1/2π∫ ∞ −∞ H 1 (ω)e j 〓 nT dω, but if we focus on the periodicity of the function e j 〓 nT with respect to ω, the above equation can be It is transformed as follows.
但し、上式の変形においてk→−k,ω→ω−
2kπ/Tなる置換を施している。従つて、もし、(9)
式の〔 〕内が恒等的にTであれば
となり、h1(t)は所望の標本化時刻でのみ1と
なり他の標本化時刻では0となるいわゆるナイキ
スト条件を満足することとなる。 However, in the modification of the above equation, k→−k, ω→ω−
A substitution of 2kπ/T is performed. Therefore, if the inside of [ ] in equation (9) is identically T, then Therefore, h 1 (t) becomes 1 only at a desired sampling time and becomes 0 at other sampling times, satisfying the so-called Nyquist condition.
ここで、前記G(ω)としてルートナイキスト
フイルターを考える。即ち、これを二乗して得ら
れるG2(ω)が
を満たすものとする。これにより、前記時間応答
h1(t)は前述のように、所望の標本化時刻での
み1となり他の標本化時刻では0となり、符号間
干渉の無い理想的な時間応答となることが判る。
通常、ベースバンドフイルターG(ω)は、その
帯域が|ω|<2π/Tに制限される。この場合
(10)式の条件は、結局、|ω|<2π/Tの範囲に
て
G2(ω)+G2(ω−2π/T)=T
を満足することと等価になる。また第3図の入力
端201から第4図aの出力端262までの干渉
信号に対する伝達関数H3(ω)および第3図の
入力端202から第4図aの出力端261までの
干渉信号に対する伝達関数H4(ω)は次式の如
く零となる。 Here, a root Nyquist filter is considered as G(ω). That is, G 2 (ω) obtained by squaring this is The following shall be satisfied. This allows the time response
As mentioned above, h 1 (t) becomes 1 only at the desired sampling time and becomes 0 at other sampling times, which indicates an ideal time response without intersymbol interference.
Typically, the band of the baseband filter G(ω) is limited to |ω|<2π/T. in this case
The condition of equation (10) is eventually equivalent to satisfying G 2 (ω)+G 2 (ω−2π/T)=T in the range |ω|<2π/T. Also, the transfer function H 3 (ω) for the interference signal from the input end 201 in FIG. 3 to the output end 262 in FIG. 4a, and the interference signal from the input end 202 in FIG. 3 to the output end 261 in FIG. 4a. The transfer function H 4 (ω) for the equation becomes zero as shown in the following equation.
更に第3図の入力端101から第4図aの出力
端261,262までの干渉信号に対する伝達関
数を各々H5(ω),H6(ω)とすれば
となり、T秒間隔の適当なサンプリング操作によ
りH5(ω),H6(ω)共に零時間応答を与えるこ
とが判る。即ちH5(ω),H6(ω)の時間応答を
h5(t),h6(t)とすれば(9)式におけると同様
となるが、これらの式の〔 〕内に前記H5
(ω),H6(ω)を代入すれば
いまルートナイキストフイルターG(ω)が|ω
|<2π/Tに帝域制限されていることを考慮す
ると0<ω2π/Tにおいては上記級数のうちk
=0,1の項のみが寄与することになり、
となり、結局h5(t),h6(t)の標本値h5
(nT),h6(nT)は全て零となることが判る。即
ち、任意の標本化時刻においてチヤンネル間干渉
が零となる。同様にして他の干渉信号に対する伝
達関数、即ち第3図の入力端102から第4図a
の出力端261,262までほ伝達関数を各々
H7(ω),H8(ω)とし、第3図の入力端301
から第4図aの出力端261,262までの伝達
関数を各々H9(ω),H10(ω)とし、第3図の
入力端302から第4図aの出力端261,26
2までの伝達関数を各々H11(ω),H12(ω)と
すれば、
と表わされる。従つて第4図aに示す如き本発明
になる直交多重信号受信器における等化器を用い
れば、全ての伝送路歪に対し所望の信号のみなら
ずチヤネル間干渉分についても、同時に等化が行
われ出力端261,262において得られる出力
信号を適当にサンプリングすれば、各々k番目お
よび(k+N)番目のテータ系列が正確に復元で
きる。 Furthermore, if the transfer functions for the interference signal from the input terminal 101 in Fig. 3 to the output terminals 261 and 262 in Fig. 4 a are respectively H 5 (ω) and H 6 (ω), then It can be seen that by appropriate sampling operations at intervals of T seconds, both H 5 (ω) and H 6 (ω) give zero-time responses. In other words, the time responses of H 5 (ω) and H 6 (ω) are
If h 5 (t), h 6 (t), then the same as in equation (9) However, in these formulas, the above H 5
(ω) and H 6 (ω), we get Now the root Nyquist filter G(ω) is |ω
| Considering the imperial limit to <2π/T, k of the above series at 0<ω2π/T
Only the terms =0, 1 will contribute, So, in the end, the sample value h 5 of h 5 (t), h 6 (t)
(nT) and h 6 (nT) are all zero. That is, inter-channel interference becomes zero at any sampling time. Similarly, the transfer function for other interference signals is calculated from the input terminal 102 in FIG. 3 to a in FIG. 4.
The transfer functions up to the output terminals 261 and 262 of
H 7 (ω), H 8 (ω), input terminal 301 in Fig. 3
Let the transfer functions from the input terminal 302 in FIG. 3 to the output terminals 261, 262 in FIG. 4a be H 9 (ω) and H 10 (ω), respectively, and
If the transfer functions up to 2 are H 11 (ω) and H 12 (ω), respectively, It is expressed as Therefore, by using the equalizer in the orthogonal multiplex signal receiver according to the present invention as shown in FIG. By appropriately sampling the output signals obtained at the output terminals 261 and 262, the k-th and (k+N)-th theta sequences can be accurately restored, respectively.
なお、上記の説明では、kが奇数の場合につい
て述べたが、kが偶数の場合は第3図における入
力端101および102が各々第1図の(k−
1)番目の入力端1k-1および(N+k−1)番
目の入力端1N+k-1に対応し、第3図における出
力端141および142は各々第2図の(k−
1)番目の出力端15K-1および(N+k−1)
番目の出力端15N+k-1に対応し、第3図におけ
る入力端201および202は各々第1図の(N
+k))番目の入力端1N+kおよびk番目の入力端
1kに対応し、第3図における出力端241およ
び242は各々第2図の(N+k)番目の出力端
15N+kおよびk番目の出力端15kに対応し、
第3図における入力端301および302は各々
第1図の(k+1)番目の入力端1k+1および
(N+k+1)番目の入力端1N+k+1に対応し、第
3図における出力端341および342は各々第
2図の(k+1)番目の出力端15k+1および
(N+k+1)番目の出力端15N+k+1に対応し、
第3図の104,113,124,203,21
4,223,304,313,324は全てT/
2秒の時間遅れを与える時間遅れ回路、103,
114,123,204,213,224,30
3,314,323は全てT/2秒の時間進みを
与える時間進み回路となる。またこれに対応し
て、第4図bは、第4図aに示す本発明による直
交多重信号受信器における等化器の構成の変形を
示すものである。但し、第4図において、入力端
451,452は各々第3図の出力端241,2
42に接続され470,471,472は全て
T/2遅延回路であり、473はT遅延回路であ
り、474,475,476,477は各々第4
図aの274,275,276,277と同一の
等化回路であり478,479は各々278,2
79に対応する減算回路および加算回路である。 In the above explanation, the case where k is an odd number has been described, but when k is an even number, the input terminals 101 and 102 in FIG.
1) correspond to the (N+k-1)th input terminal 1 k-1 and the ( N+k-1)th input terminal 1 N+k-1 , and the output terminals 141 and 142 in FIG.
1) th output end 15 K-1 and (N+k-1)
The input terminals 201 and 202 in FIG. 3 correspond to the (N+k-1) th output terminal 15 in FIG.
+k))-th input terminal 1 N+k and k-th input terminal 1 k , and the output terminals 241 and 242 in FIG. 3 respectively correspond to the (N+k)-th output terminal 15 N+k and Corresponding to the k-th output end 15k,
Input terminals 301 and 302 in FIG. 3 correspond to the (k+1)th input terminal 1 k+1 and (N+k+1)th input terminal 1 N+k+1 in FIG. 1, respectively, and the output terminals in FIG. 341 and 342 correspond to the (k+1)th output terminal 15 k+1 and the (N+k+1)th output terminal 15 N+k+1 in FIG. 2, respectively;
104, 113, 124, 203, 21 in Figure 3
4,223,304,313,324 are all T/
time delay circuit providing a 2 second time delay, 103;
114, 123, 204, 213, 224, 30
3, 314, and 323 are all time advance circuits that provide a time advance of T/2 seconds. Correspondingly, FIG. 4b shows a modification of the equalizer configuration in the orthogonal multiplex signal receiver according to the present invention shown in FIG. 4a. However, in FIG. 4, the input terminals 451 and 452 are the output terminals 241 and 2 in FIG. 3, respectively.
42, 470, 471, and 472 are all T/2 delay circuits, 473 is a T delay circuit, and 474, 475, 476, and 477 are each a fourth delay circuit.
The equalization circuits 274, 275, 276, and 277 in Figure A are the same, and 478 and 479 are the same as 278 and 277, respectively.
These are a subtraction circuit and an addition circuit corresponding to 79.
また第4図a,bに示される本発明による直交
多重信号受信器における等化器はT秒の線形遅延
分を除いて考えると一般に第5図の如く表わされ
る。即ち、
第5図に示す本発明による直交多重信号受信器
における等化器の一般的な概念図において55
1,552は入力端561,562は出力端、5
74は第一の等化回路、576は第三の等化回
路、577は第四の等化回路、578は減算回
路、579は加算回路であり、571および57
2は等化すべきチヤンネルによつて、
T/2時間遅れ回路とT/2時間進み回路、ま
たはT/2時間進み回路とT/2時間遅れ回路と
なる。 Further, the equalizer in the orthogonal multiplex signal receiver according to the present invention shown in FIGS. 4a and 4b is generally expressed as shown in FIG. 5, excluding the linear delay of T seconds. That is, in the general conceptual diagram of the equalizer in the orthogonal multiplex signal receiver according to the present invention shown in FIG.
1,552 is the input end 561,562 is the output end, 5
74 is a first equalization circuit, 576 is a third equalization circuit, 577 is a fourth equalization circuit, 578 is a subtraction circuit, 579 is an addition circuit, 571 and 57
2 is a T/2 time delay circuit and a T/2 time lead circuit, or a T/2 time lead circuit and a T/2 time delay circuit, depending on the channel to be equalized.
以上述べた如く、本発明による直交多重信号受
信器における等化器を用いれば、各チヤンネルに
対しベースバンド等化が可能になり、簡単な構成
で、全ての伝送路歪に対し、所望信号の等化およ
びチヤンネル間干渉信号に対する等化が同時に達
成される。 As described above, by using the equalizer in the orthogonal multiplex signal receiver according to the present invention, baseband equalization is possible for each channel, and with a simple configuration, the desired signal can be Equalization and equalization for interchannel interference signals are achieved simultaneously.
第1図は直交多重信号の送信装置を表わすブロ
ツク図、第2図は、第1図の送信装置に対応する
受信装置を表わすブロツク図、第3図は、第1図
の送信装置から伝送路に送出された直交多重信号
が第2図の受信装置で受信される伝送系の等価伝
送路モテルを示すブロツク図、第4図a,bは等
化すべきチヤネルによつて使い分ける本発明によ
る直交多重信号受信器における等化器の実施例を
示すブロツク図、第5図は本発明による直交多重
信号受信器における等化器の一般的な概念図であ
る。
図において、11,12…12Nは2N個の入力
端、2N+1,2N+2,…22NはN個のT/2秒遅延
素子、31,32,…32Nは2N個のベースバン
ドフイルタ、41,42,…42Nは2N個の変調
器、5は加算器、6は出力端、11は入力端、1
2N+1,12N+2,…122Nは2N個の復調器13
1,132,…132Nは2N個のベースバンドフ
イルタ、141,142,…14NはN個のT秒
遅延素子、14N+1,14N+2,…142NはN個の
T/2秒遅延素子、151,152,…152Nは
2N個の出力端、103,104,113,11
4,123,124,203,204,213,
214,223,224,303,304,31
3,314,323,324等は、T/2秒の時
間遅れ回路又は、T/2秒時間進み回路であり、
105〜108,125〜128,205〜20
8,215〜218,225〜228,305〜
308,315〜318,325〜328等は全
て等価ベースバンド伝送路、270,271,2
72,470,471,472は全てT/2遅延
回路、273,473はT遅延回路、274,4
74は第一の等化回路、275,475は第二の
等化回路、276,476は第三の等化回路、2
77,477は第四の等化回路、571,572
は各々T/2時間遅れ回路とT/2時間進み回路
またはT/2時間進み回路とT/2時間遅れ回
路、574は第一の等化回路、575は第二の等
化回路、576は第三の等化回路、577は第四
の等化回路である。
FIG. 1 is a block diagram showing a transmitting device for orthogonal multiplexed signals, FIG. 2 is a block diagram showing a receiving device corresponding to the transmitting device in FIG. 1, and FIG. 3 is a block diagram showing a transmission path from the transmitting device in FIG. A block diagram showing an equivalent transmission line model of a transmission system in which the orthogonal multiplexed signal sent to the receiver is received by the receiving device shown in FIG. FIG. 5 is a block diagram showing an embodiment of an equalizer in a signal receiver. FIG. 5 is a general conceptual diagram of an equalizer in an orthogonal multiplex signal receiver according to the present invention. In the figure, 1 1 , 1 2 ... 1 2N are 2N input terminals, 2 N+1 , 2 N+2 , ... 2 2N are N T/2 second delay elements, 3 1 , 3 2 , ... 3 2N is 2N baseband filters, 4 1 , 4 2 ,...4 2N is 2N modulators, 5 is adder, 6 is output end, 11 is input end, 1
2 N+1 , 12 N+2 ,...12 2N is 2N demodulators 13
1 , 13 2 , ... 13 2N are 2N baseband filters, 14 1 , 14 2 , ... 14 N are N T-second delay elements, 14 N+1 , 14 N+2 , ... 14 2N are N T/2 second delay elements, 15 1 , 15 2 ,...15 2N are
2N output terminals, 103, 104, 113, 11
4,123,124,203,204,213,
214, 223, 224, 303, 304, 31
3, 314, 323, 324, etc. are T/2 second time delay circuits or T/2 second time advance circuits,
105-108, 125-128, 205-20
8,215~218,225~228,305~
308, 315 to 318, 325 to 328, etc. are all equivalent baseband transmission lines, 270, 271, 2
72, 470, 471, 472 are all T/2 delay circuits, 273, 473 are T delay circuits, 274, 4
74 is a first equalization circuit, 275, 475 is a second equalization circuit, 276, 476 is a third equalization circuit, 2
77,477 is the fourth equalization circuit, 571,572
are respectively a T/2 time delay circuit and a T/2 time lead circuit or a T/2 time lead circuit and a T/2 time delay circuit, 574 is a first equalization circuit, 575 is a second equalization circuit, and 576 is a The third equalization circuit 577 is a fourth equalization circuit.
Claims (1)
個のパルス振幅変調信号α1(t),α2(t)
……α2N(t)のうち、N個のパルス振幅変調信
号α1(t),α2(t)……αN(t)を各々周
波数応答特性の等しいN個のベースバンドフイル
タに通した出力β1(t),β2(t)……βN
(t)と、他のN個のパルス振幅変調信号αN+1
(t),αN+2(t)……α2N(t)を各々T/2
秒遅延させた後、各々前記N個のベースバンドフ
イルタと同一の周波数応答特性を有する他のN個
のベースバンドフイルタに通して得られる出力β
N+1(t),βN+2(t),……β2N(t)とを用
い、k番目の出力βk(t)(但しk=1,2,…
N)および(k+N)番目の出力βk+N(t)に
対してkが奇数の時は各々同相キヤリア例えば
cos ωktおよび直交キヤリア例えばsin ωkt
を乗じた後両乗算出力を加算し、kが偶数の時は
各々sinωktおよびcos ωktを乗じた後両乗算
出力を加算する事により、(但しωk−ωk-1=2
π/T)k番目の直交振幅変調信号Jk(t)を
得、こうして得られたN個の直交振幅変調信号J1
(t),J2(t),……JN(t)が全て加算された
後伝送路を介して受信された受信信号に対し前記
送信側と逆変換を行う事により、前記複数個の送
信パルス振幅変調信号α1(t),α2(t),…
…α2N(t)に対応する受信パルス振幅変調信号
γ1(t),γ2(t),……γ2N(t)を得る直
交多重信号受信器において、k=(k=1,2,
……Nなる各々のkに対し)が奇数の時は、k番
目の受信パルス振幅変調信号γk(t)を第一の
等化回路C1に通して得られる出力から(k+
N)番目の受信パルス振幅変調信号γk+N(t)
をγk(t)に対し相対的にT/2秒遅延させた
後、第二の等化回路C2に通して得られる出力を
減算する事によりk番目の等化パルス振幅変調信
号xk(t)を得、他方(k+N)番目の受信パ
ルス振幅変調信号γk+N(t)を前記第一の等化
回路C1と同一の周波数応答特性を有する第四の
等化回路C4に通して得られる出力と、k番目の
受信パルス振幅変調信号γk(t)をγk+N(t)
に対し相対的にT/2秒進めた後前記第二の等化
回路C2と同一の周波数応答特性を有する第三の
等化回路C3に通した出力とを加算することによ
り(k+N)番目の等化パルス振幅変調信号xk+
N(t)を得、kが偶数の時は、(k+N)番目の
受信パルス振幅変調信号γk+N(t)を前記第一
の等化回路C1に通して得られる出力から、k番
目の受信パルス振幅変調信号γk(t)をγk+N
(t)に対し相対的にT/2秒進めた後前記第二
の等化回路C2に通して得られる出力を減算する
ことにより(k+N)番目の等化パルス振幅変調
信号xk+N(t)を得、他方k番目の受信パルス
振幅変調信号γk(t)を前記第四の等化回路C4
に通して得られる出力と、(k+N)番目の受信
パルス振幅変調信号γk+N(t)をγk(t)に対
し相対的にT/2秒遅延させた後、前記第三の等
化回路C3に通して得られる出力とを加算するこ
とにより、k番目の等化パルス振幅変調信号xk
(t)を得、全ての伝送路歪が等化される事を特
徴とする直交多重信号受信器における等化器。1 2N synchronized with each other with a clock period of T seconds
pulse amplitude modulated signals α 1 (t), α 2 (t)
...Among α 2N (t), N pulse amplitude modulation signals α 1 (t), α 2 (t)…α N (t) are passed through N baseband filters each having the same frequency response characteristic. output β 1 (t), β 2 (t)...β N
(t) and other N pulse amplitude modulated signals α N+1
(t), α N+2 (t)...α 2N (t) are each T/2
After a delay of seconds, the output β is passed through another N baseband filters, each having the same frequency response characteristics as the N baseband filters.
Using N+1 (t), β N+2 (t), ...β 2N (t), the k-th output β k (t) (where k=1, 2, ...
N) and (k+N)th output β k+N (t), when k is an odd number, the in-phase carrier, e.g.
cos ω k t and orthogonal carrier e.g. sin ω k t
When k is an even number, by multiplying by sinω k t and cos ω k t and then adding the square calculation outputs (however, ω k −ω k-1 = 2
π/T) to obtain the k-th orthogonal amplitude modulation signal J k (t), and thus obtain the N orthogonal amplitude modulation signals J 1
(t), J 2 (t), ...J N (t) are all added up, and then the received signal received via the transmission path is inversely transformed with the transmitting side. Transmission pulse amplitude modulation signals α 1 (t), α 2 (t),...
In an orthogonal multiplex signal receiver that obtains received pulse amplitude modulated signals γ 1 ( t), γ 2 (t), ... γ 2N (t) corresponding to α 2N (t), k=(k=1, 2 ,
. . . for each k of N) is an odd number, from the output obtained by passing the k-th received pulse amplitude modulation signal γ k (t) through the first equalization circuit C1, (k+
N)th received pulse amplitude modulation signal γ k+N (t)
is delayed by T/2 seconds relative to γ k (t), and then the k-th equalized pulse amplitude modulated signal x k is obtained by subtracting the output obtained through the second equalization circuit C 2 (t), and the (k+N)th received pulse amplitude modulated signal γ k+N (t) is converted to a fourth equalizer circuit C 4 having the same frequency response characteristic as the first equalizer circuit C 1 . and the k-th received pulse amplitude modulation signal γ k (t) as γ k+N (t)
By adding the output passed through the second equalization circuit C 2 and the third equalization circuit C 3 having the same frequency response characteristics after advancing T/2 seconds relative to (k+N) Equalized pulse amplitude modulation signal x k+
N ( t ), and when k is an even number, k γ k +N
By advancing T/2 seconds relative to (t) and subtracting the output obtained through the second equalization circuit C2 , the (k+N)th equalized pulse amplitude modulation signal x k+N (t), and the k-th received pulse amplitude modulated signal γ k (t) is input to the fourth equalization circuit C 4
After delaying the (k+N)th received pulse amplitude modulated signal γ k+N (t) by T/2 seconds relative to γ k (t), By adding the output obtained through the equalization circuit C3 , the k-th equalized pulse amplitude modulation signal x k
An equalizer for an orthogonal multiplex signal receiver, characterized in that it obtains (t) and equalizes all transmission path distortions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5039477A JPS53135212A (en) | 1977-04-30 | 1977-04-30 | Equalizer of orthogonal multiple signal receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5039477A JPS53135212A (en) | 1977-04-30 | 1977-04-30 | Equalizer of orthogonal multiple signal receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS53135212A JPS53135212A (en) | 1978-11-25 |
| JPS6131655B2 true JPS6131655B2 (en) | 1986-07-22 |
Family
ID=12857646
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5039477A Granted JPS53135212A (en) | 1977-04-30 | 1977-04-30 | Equalizer of orthogonal multiple signal receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS53135212A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6464774A (en) * | 1987-09-03 | 1989-03-10 | Mitsubishi Metal Corp | Polishing device |
-
1977
- 1977-04-30 JP JP5039477A patent/JPS53135212A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6464774A (en) * | 1987-09-03 | 1989-03-10 | Mitsubishi Metal Corp | Polishing device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS53135212A (en) | 1978-11-25 |
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