JPS6131891B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a small-sized electronic computer having an integral calculation function that automatically sets the number of divisions of an integrand according to the accuracy of a definite integral calculation result. Conventionally, when performing an integral such as ∫a ^b 1/x + 1dx, for example, [n(x+1)] ^b _a was calculated in advance by hand calculation, etc., and the calculation of n(b+1) - n(a+1) was performed using a computer. However, this method had the disadvantage that only those who were familiar with integral calculations could perform the calculation, and that it became extremely troublesome when the equation became complicated. So, for example, the definite integral ∫a ^b of the nth degree polynomial of x
(k ₁ x ⁿ + k ₂ x ^n-1 +...) for dx, [k ₁ /n+1x
_o+1 +k ₂ /nx _o +...] ^b The indefinite integral of the integrand is stored in the ROM as a formula as shown in _a , and when the calculation is executed, the integral intervals a, b, coefficients k ₁ , k ₂ , etc. . . , a system has been considered in which an integral operation can be performed simply by inputting data such as an exponent n. However, in the above method, the indefinite integral of the integrand must be stored in ROM in advance, so
The drawback was that the types of integrands that could be stored there were also limited. Therefore, the applicant proposed a compact electronic computer that can integrate any function using Simpson's formula. When such a calculator integrates a predetermined interval, it divides the interval into predetermined parts and performs the calculation, so it is necessary to set the number of divisions each time the calculation is performed. However, according to Simpson's formula, etc., the higher the number of divisions, the higher the calculation accuracy, but if the division width becomes too small, the number of calculations will increase, and rounding errors in the calculation results will accumulate, and from a certain number of divisions, the calculation accuracy will be higher. The error will increase. The present invention has been made in view of the above circumstances, and calculates the calculation accuracy by comparing the previous calculation result and the current calculation result, and performs calculations sequentially until the calculation accuracy reaches a certain level of accuracy. It is an object of the present invention to provide a small electronic calculator having an integral calculation function that automatically sets the number of divisions. In order to achieve the above object, the present invention uses, for example, Simpson's formula, and when the integrand is (x) and the interval [a, b] is divided into 2 _o , the following gradual It is expressed by the following formula. S ₁ =h ₁ /3{(a)+(b)}+4/3h ₁ (a+h ₁
)…(1) T ₁ =4/3h ₁ (a+h ₁ )…(2) Sn=1/2 {S _o-1 -1/2T _o-1 }+Tn...(4) However, hn=ba/2n As a result, Sn becomes an integral value. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit block diagram showing the configuration of the present invention. In the figure, numeral 1 is a ROM (read-on memory) in which various microinstructions are stored. A row address signal U for specifying a register of RAM (random access memory) 2, which will be described later, from this ROM1, a column address signal L for specifying a digit of the above register, and a numerical value used for various calculations, size comparisons, etc. Instruction signals such as code signal C ₀ , operation command, gate control signal, etc.
INS and a next address signal NA specifying its own next address are output in parallel via bus lines a to e, respectively. The next address signal NA output via bus line e is sent to the ROM address section 3. The ROM address section 3 specifies the address of the ROM 1 in accordance with the next address signal NA. Further, the instruction INS is supplied to the instruction decoder 4 via the bus line d. This instruction decoder 4
decodes the instruction INS and outputs gate control signals I ₁ to I ₈ , read/write signals R/W ₁ ,
R/W ₂ , subtraction instruction SUb, specified digit length mode M,
Outputs various control signals such as increment signal INC. The specified digit length mode M is sent to the first address counter 2a, and is output when specifying a plurality of digits in the register of the RAM 2. Row address signal U output from ROM1 above
is input to the row address input terminal RU of RAM2 via bus line a. Further, the column address signal L is inputted to the column address input terminal RL via the bus line b and the first address counter 2a. As shown in FIG. 2, RAM2 has operation registers for X, Y, Z, and
It consists of registers for integration of S and E, etc.
The A register contains the lower limit data (a) of the integral interval [a, b], and the B register contains the upper limit data of the integral interval.
(b) is memorized. Further, the division parameter is stored in the N register. The H register contains the step width b - a/2 _o , which is the width of the above integral interval a to b divided by 2 _o .
is stored, and the accumulation parameter in the above equation (3) is stored in the K register. R register is above (4)
S _o-1 in the equation, that is, the previous integral value is stored. Further, the Tn and Sn values expressed by the above equations (3) and (4) are stored in the T and S registers. The E register stores a value representing the calculation accuracy determined from the previous integral value stored in the R register and the current integral value stored in the S register. The writing and reading of data in each of the above registers is controlled by the R/W1 signal. On the other hand, the data output from the output terminal OUT of RAM2 is controlled by the control signals I _{3 and 3} as the operand and operand, respectively.
I ₄ is input to input terminals a and b of the arithmetic circuit 5 via gate circuits G ₃ and G ₄ to which it is input. The calculation result calculated by the calculation circuit 5 is input to the input terminal of the RAM 2 mentioned above.
Input to IN. The RAM 2 is also indirectly addressed by setting the address data stored therein into the first address counter _2a via the gate circuit G2. Further, the output data of the arithmetic circuit 5 is also sent to the display section ₆ via the gate circuit G5 to which the gate control signal _I5 is applied, and is displayed. Furthermore, the arithmetic circuit 5 outputs a judgment signal indicating the presence or absence of data and the presence or absence of carry when making judgments such as comparing the size of data.
It is output to the ROM address section 3. 7 is the key input section, which specifies the write mode for writing the integrand, the execution mode for performing integration, or the mode for normal calculations, etc.

[Formula] Key 7a, instructs execution of integral

It is equipped with a [Formula] key 7b, a numeric key for inputting data, and a function key for instructing various operations such as four arithmetic operations, S1n, and COS. And the above mode specification is

[Formula] This is performed using a combination of the key 7a and the numeric key. This key input section 7
Key sampling data from a register (not shown) in the RAM 2 is sequentially passed through a gate circuit _G7 , decoded and inputted to a decoder 8, and key sampling is performed. However, if no key operation is performed in the key input section 7, the above register is incremented by "+1" and the same operation is repeated, and when a key is operated, the key data is sent to the gate circuit G ₈ and the arithmetic circuit 5. The data is written to a predetermined register in RAM2 via the data. In addition, the above mode specification key

When the write mode of the integrand function is specified by [Formula 7a], the function data input from the key input section 7 is once written to the RAM 2, and then sent to the gate circuit G ₆
In the integral execution mode, the integrand function written to the RAM 9 is read out to the RAM 2 and the integral operation is executed. Note that this RAM 9 has a second register counter 9 that is incremented by the above INC signal.
Addresses are sequentially specified by a, and writing and reading are controlled by a read/write signal R/ _W2 . Next, the operation of the present invention configured as described above will be explained with reference to the state diagrams and flowcharts of FIGS. 3 to 5. Here, for example, let's assume that the integrand is (x) = 1/x + 1 and the interval is [0.2] ∫
Let us perform the calculation ² ₀ 1/x + 1dx. First, the key input section 7

The integrand function writing mode is set by operating the [Formula] key 7a and the numeric key. Then, by operating a key to input the function 1/x+1, it is written into the RAM 9 as program data as shown in FIG. That is, for example

[Formula] □The definition of variable x is completed by key operation 1. be done. and

A variable is read by key operation of [Formula], and "+1" is added to the variable by the next key operation of □+ and □1. Furthermore,

The [Formula] key operation instructs the reciprocal function 1/x+1 of "x+1", and the □= key operation executes it. The above key operations complete the input of the integrand function (x)=1/x+1. next,

By operating the [Formula] key 7a and the numeric key, the mode is switched to the integral execution mode. Therefore, when the integral interval data "0" and "2" are entered, "0" and "2" are written in the A register and the B register, respectively. In this state, press the integral execution key.

When Equation 7b is operated, the definite integral is executed according to the flowchart shown in FIG. Note that the numbers (1) to (20) shown in this flowchart correspond to the state diagram in FIG. In step _S1 , the numerical code signal C0 _" 1" outputted from the N register ROM1 as a division parameter is written into the N register of the RAM2 via the arithmetic circuit 5. In the next process _S2 , the above A,
Set the width of the integral interval stored in the B register to 2 _o
The step width divided by is memorized. That is, the contents of the A and B registers are read out to the arithmetic circuit 5 and
After the subtraction of "0" is performed, the subtraction result "2" is temporarily written to the B register. Then, 2 _N operations are performed on the contents of the N register by the operation register. Therefore, the content of the N register is now "1"
Therefore, 2 _N becomes "2". Furthermore, the subtraction result "2" stored in the B register is divided by the value "2" of 2 _N in the arithmetic circuit 5, and the arithmetic result "1" is written to the H register, and the process proceeds to step _S3 . move on. Process _S3 is the calculation of the value (a+h) of x=a+h, in which the contents of the A register and the contents of the H register are added, and the addition result is then assigned to the integrand function 1/x+1 input in advance. After the value is calculated, the value is written to the T register. That is, since the contents of the A register and the H register are "0" and "1", respectively, the addition result is "1". The integrand function written in the RAM 9 is stored in the second address counter 9a.
The program contents shown in FIG. 3 are sent step by step to the RAM 2 and the arithmetic circuit 5 while being addressed by , and the arithmetic operation (1) is performed based on the addition result "1". As a result, the value of (1) becomes "0.5" and is written to the T register as shown in FIG. 5 (1). Next, proceed to process S ₄ , and calculate the previous term h ₁ /3 {(
a) +(b)} is performed. Now, since the content of the A register is "0", (a) = (0) is "1"
Since the content of the B register is "2",
(b)=(2) becomes "0.3...3". and (a)
The addition result in (b) is multiplied by 1/3, which is the content of the H register divided by 3, and the result is 0.4...
4'' is written to the S register as shown in FIG. 5(1). Processing _S5 is to perform the operation of 4/3h ₁ (a+h ₁ ) in the latter term of the above equation (1), which is to multiply the contents of the H register and the T register by a constant 4/3, The calculation result is written to the T register again. That is, the content "1" of the H register and the content "0.5" of the T register are supplied to the arithmetic circuit 5 and become "1".
×0.5'' is performed, and the result of the operation is once written to the T register and then sent to the arithmetic circuit 5 again. At the same time, the numerical code signal C ₀ (4/3 = 1.3...3) from the ROM 1 is also sent to the arithmetic circuit 5. multiplication is performed. The calculation result “0.6…6” is shown in Figure 5.
The data is written to the T register as shown in (2), and the process advances to the next step _S6 . Step _S6 is to add the first and second terms of equation (1) above, and the contents of the S register "0.4...4" and the contents of the T register "0.6...6" are read out to the arithmetic circuit 5. will be added. and,
The addition result "1.1...1" is again written to the S register as shown in FIG. 5(2). Therefore, this S
The value of S ₁ in the above equation (1) is stored in the register. The next step _S7 is R
The accuracy of the integral value is determined by calculating the difference between the contents of the register and the contents of the S register that stores the current integral value, and dividing the difference by the current integral value of the contents of the S register. That is, S, R
The contents of the registers are both sent to the arithmetic circuit 5 to find the difference between the two, and further calculation is performed based on the contents of the S register. Now, the contents of the R register are shown in Figure 5 (2)
Since it is "0" as shown in FIG. 5, "1" is written in the E register as shown in FIG. 5(3). and,
In the next step _S8 , it is determined whether the contents of the E register are smaller than 1.times.10.sup. ^-4 to determine whether the integral value has been calculated to a predetermined accuracy. The contents of the E register and the numerical code signal C ₀ output from ROM 1 are sent to the arithmetic circuit 5.
(1×10 ⁻⁴ ) is supplied, and a comparison judgment of size is made there. The judgment result is sent to the ROM address section 3 as a judgment signal indicating the presence or absence of data and the presence or absence of carry.
sent to. Now, the contents of the E register are shown in Figure 5 (3).
As shown in , it is "1", so it becomes "NO" and the process proceeds to the next step _S9 . Step _S9 determines whether the value of the division parameter stored in the N register has reached a specific value ("10"), and performs integration if the integrand function does not reach a predetermined accuracy. This is to terminate the calculation midway. As in the above step, the contents of the N register and the numerical code signal C ₀ (10) are sent to the arithmetic circuit 5 and a match comparison is made. Since the content of the N register is "1" here, the process advances to the next step _S10 . In step _S10 , the operation of transferring the contents of the S register to the R register is performed via the arithmetic circuit 5, and as shown in FIG. 5(3), "1.1...1" is written to the R register, and the next processing Proceed to S ₁₁ . Process S ₁₁ executes the previous term of equation (4) above,
The contents of the T register are set to “2” from the contents of the S register.
Subtract the value divided by , and then divide it by 2. As a result, "0.38...8" is written in the S register as shown in FIG. 5(3). What to do next
At _S12 , a ^2N operation is performed in which the division parameter of the N register is raised to a power, and the result is written to the K register. Therefore, since the content of the N register is "1", "2" is written to the K register as shown in FIG. 5(4), and the process proceeds to the next step _S13 . Step _S13 adds “+1” to the contents of the N register.
By doing this, the division parameter is increased by "1", and the content of the N register becomes "2". In the next process _S14 , a new step width is set by dividing the step width of the contents of the H register by "2", and the contents of the H register become "0.5", and the process proceeds to step _S15 . At step _S15 , "0" is written to register T and cleared. Therefore, in the next process _S16 to step _S20 , the above equation (3) is

The calculation of [Formula] is performed. First, in process _S16 , "2K-1" is set for the accumulation parameter stored in the K register.
The calculation result is multiplied by the step width of the H register. Further, the contents of the A register are added to the result of the operation. Now, K
Since the content of the register is “2”, “2×2−
Then, the operation result "3" is multiplied by the contents of the H register "0.5". Furthermore, the multiplication result "1.5" and the content of the A register are added, but since the content of the A register is "0", the content of the X register becomes "1.5" as shown in Figure 5 (5), and the following Proceed to process _S17 . Processing S ₁₇
Now, based on the above integrand function, an operation is performed on the content "1.5" of the X register. the result,
(1.5) becomes "0.4" and is written to the X register as shown in FIG. 5(6). Further step S ₁₈
Then, the cumulative value of (x) up to the previous time and the current value of (x) are added. At this point T
Since the contents of the register are "0" and the contents of the X register are "0.4", "0.4" is written to the T register. Next, the process advances to step _S19 , and the accumulation parameter of the contents of the K register is set to "-".
1 is performed, and the process advances to step _S20 . In step _S20 , it is determined whether the accumulation parameter of the K register is "0" or not. Figure 5(7)
As shown in the figure, the content of the K register is "1", so the process advances to the next step _S16 . In process _S16 , the same process as last time is performed on the content "1" of the K register,
As shown in FIG. 5(7), "1" is written to the X register. Then, processing _S17 to step _S19
is executed in the same way as before. As a result, Figure 5
As shown in (8), the content of the K register becomes "0", and in the next step _S20 , it is determined as "YES" and the process advances to step _S5 . In process _S5 , the accumulated value is multiplied by 4/3 hn in the above equation (3). As a result, as shown in Figure 5 (9), the T register contains "0.71...
1" is written. Then, after step _S6 ,
In step _S7 , the contents of the E register are “0.01010.
. . ”, and further steps _S8 to _S11 are executed in the same manner as described above, and each register becomes as shown in FIG. 5(10). Therefore, in process _S12 , the operation "2 2 " is performed on the content " ² " of the N register, and "4" is written to the K register as shown in FIG. 5 (11). The following steps _S13 , Processing _S14 , Steps
_S15 is executed in the same manner as described above, and each register becomes as shown in FIG. 5 (11). Furthermore, each process from step _S16 to step _S20 is sequentially executed in the same manner as described above until the contents of the K register become "0". As shown in FIG. 5 (13), when the contents of the K register become "0", the process proceeds to process _S5 and step _S6 .
In step _S6 , the content of the T register "0.72650..." obtained this time is added to the content of the S register obtained previously "0.372...", and as shown in FIG. 5 (14), "1.09872..." is added. ...” is written to the S register. In the next step _S3 , see Figure 5 (15).
As shown in the figure, the contents of the E register are “1.616…×
10 ^-3 ''. However, in the next step _S9 , E
Since the content of the register is greater than "1×10 ^-4 ", the process advances to step S ₁₀ and processing S ₁₁ , and each register becomes as shown in FIG. 5 (15). And the next process
In step _S12 , the operation ``2 <sup>3</sup> '' is performed and ``8'' is written in the K register, and in the next step _S13 , the contents of the N register are incremented by ``1'' to become ``4''. Thereafter, processing S ₁₄ and step S ₁₅ are executed, resulting in a process as shown in FIG. 5 (16). Furthermore, processing _S16 to step
_S20 is sequentially executed in a circular manner until the contents of the K register become "0". Therefore, in step _S19 , as shown in FIG. 5 (18), when the content of the K register becomes "0", it is determined as "YES" in the next step _S20 , and the process proceeds to step _S5 , step _S6 , and process. Proceed to S ₇ . In this process _S7 , the contents of the E register become as shown in FIG. 5 (19). However, in the next step _S3 , the contents of the E register are "9.58...×10 ^-5 " as described above, so E<1×
10 ^-4 and proceeds to processing _S21 . In process _S21 , only significant digits are extracted from the integral value stored in the S register. That is, the currently computed integral value stored in the S register is compared with the previously computed integral value stored in the R register, and only the digits that match are extracted. Therefore, the contents of the S register are "1.098" as shown in FIG. 5 (20). Then, proceeding to the next step _S22 , the contents of the S register are transferred to the X register, and
This is displayed on the display unit 6 as the desired integral value. In addition, in the above example, the value of calculation accuracy (|S-R/S|) was set to "1 x 10 ^-4 ", but if this value is made smaller, a more accurate integral value can be obtained. Of course. Further, in the above embodiment, Simpson's formula is used, but for example, the trapezoidal formula, Ponsley's formula, etc. may be used. In short, it is sufficient that it does not depart from the gist of the present invention, and various applications and modifications are possible. As described above in detail, according to the present invention,
The calculation accuracy is derived by comparing the previous and current integral calculation results, and the number of divisions is automatically set so that calculations are performed sequentially until the calculation accuracy reaches a predetermined accuracy. Since definite integral calculations can be performed simply by specifying an integral range without the need for key input, definite integral calculations can be performed with fewer key operations, and calculation results can be obtained with constant accuracy.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing an embodiment of the present invention, FIG. 2 is a register configuration diagram of RAM 2 in FIG. 1, FIG. 3 is a storage state diagram of an integrand function in RAM 9 in FIG. 1, and FIG. is a flowchart for explaining the operation, and FIG. 5 is a register state diagram accompanying the above flowchart. 1...ROM, 2...RAM, 3...ROM address section, 4...instruction decoder, 5
...Arithmetic circuit, 7...Key input section, 9...
RAM.

Claims (1)

[Claims] 1. A first storage means for storing an integrand, a dividing means for dividing an externally input definite integral range into a plurality of parts according to the number of divisions, and a readout for sequentially reading out the integrand stored in the storage means. means, a calculation means for sequentially performing an integral calculation for each divided range divided by the division means based on the integrand read out from the reading means, and storing integral values calculated this time and last time by the calculation means. a second storage means for
Accuracy calculation means for calculating calculation accuracy according to the current and previous calculated integral values stored in the second storage means, and whether or not the accuracy calculated by the accuracy calculation means has reached a predetermined value. and a detecting means for detecting, and performing an integral operation while sequentially increasing the number of divisions of the dividing means until the detecting means detects that the integral value has reached a predetermined accuracy. A small electronic calculator with arithmetic functions.