JPS6132685B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic device using a processor such as a microcomputer.

With recent advances in digital circuit technology, processors such as microcomputers have become smaller and available at lower prices.As a result, attempts have been made to incorporate microcomputers into analog processing devices. There is. In this case, as shown in FIG. 1, an analog-to-digital converter (hereinafter referred to as an A/D converter) 1 for converting an analog signal into a digital signal is installed on the input side of the processor 2, and an analog-to-digital converter (hereinafter referred to as an A/D converter) 1 is installed on the input side of the processor 2, and a digital signal is input on the output side. Generally, a digital-to-analog converter (hereinafter referred to as a D/A converter) 3 for converting into an analog signal is provided. Further, it is common practice to provide a necessary number of thumbwheel switches 101, 102 to 104 on the input side of the processor 2 from which digital signal outputs can be directly obtained for various calculation parameters. However, the A/D converter has a complex circuit configuration and is expensive, so if an arithmetic unit is configured with an A/D converter and a microcomputer, the overall device will also be complicated and expensive. be. Additionally, in order to accept digital signals from each thumbwheel switch, the processor 2
A plurality of bits must be applied to each input terminal, which is undesirable from the standpoint of effectively utilizing the limited number of input terminals.

Here, the present invention does not require an A/D converter on the input side of the processor, and can provide calculation parameters in an analog manner. Therefore, the overall configuration is simple and the processor is limited. The aim is to realize an inexpensive arithmetic device that can effectively utilize the number input terminal.

FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, 11, 12, 13, 1
4 and 15 are comparators, respectively, and 20 is a processor which receives the signals from each comparator as input, and is a microcomputer, for example. 30 is a D/A converter that converts the digital signal from the processor 20 into an analog signal and supplies its output to the other input end of each comparator in common; 40 is analog signal holding means, such as a semiconductor switch 41, a capacitor, etc.; 4
2 and an amplifier 43 are used. Note that this analog signal holding means is not required when the calculation result is obtained as a digital signal. Reference numeral 50 denotes a calculation parameter setting circuit, which includes a DC power supply 51 and a plurality of (four in this case) variable resistors 52, 53, 54, 55 commonly connected to the DC power supply 51 to form potentiometers. The various calculation parameters required for a given calculation are set here in an analog manner. 60 is an output terminal for outputting a digital signal, and a digital indicator 61 is connected here.

The comparator 11 is provided with a signal to be operated on (signal to be operated on) e ₁ at one input terminal, and receives a signal e ₁ from the D/A converter 30 provided at the other input terminal. The _comparison result is provided as an input signal to the processor 20. Similarly, comparators 12 to 15
compares the analog signals e ₂ to _{e 5} corresponding to each parameter from the calculation parameter setting circuit 50 given to one input terminal with the analog signal e _f from the D/A converter 30, and calculates the comparison result. is given as an input signal to the processor 20. The processor 20 is composed of an input port 21, a data memory section 22 composed of, for example, a read/write memory, an arithmetic control section 23, a program memory section 24 composed of, for example, a read-only memory, and an output port 25. The input port 21 is supplied with signals from the comparators 11 to 15, and here, the signals from the comparators 11 to 15 are inputted to the input port 21.
Waiting for output signals to be read sequentially or selectively. For example, the data memory section 22 is connected to the input port 2 by a signal from the arithmetic control section 23.
It temporarily stores signals given from 1 and stores calculation results. Program memory section 2
4 stores in advance conversion procedures for converting analog signals into digital signals, procedures for controlling peripheral circuits, various calculation procedures, and data necessary for calculations, the contents of which are transmitted from the calculation control unit 23. It is read out by the signal. Arithmetic control unit 23
reads the state of the signal applied to the input port 21, writes it to the data memory section 22, decodes the calculation procedure from the program memory section 24, and reads the data read from here or from the data memory section 22. Digital calculations are performed using the signals obtained. The output port 25 is supplied with a digital signal output from the data memory section 22 or the arithmetic control section 23, and is connected to the D/A converter 3 by the signal from the arithmetic control section 23.
0 to digital signal or signal holding circuit 4
0 to output a control signal for controlling this circuit. The D/A converter 30 converts the digital signal output from the output port 25 into an analog signal,
This signal is commonly applied to the other input terminals of the comparators 11 to 15, and is output to the analog signal holding means 40 when the switch 41 is made conductive by the output command signal (control signal) from the processor 20.

The operation of the apparatus constructed as described above will now be explained with reference to the time chart of FIG.

3A shows the operated signal _e1 , and FIG. 3B shows the sampling clock signal that governs the operation within the processor 20. Here, the period t of the sampling clock signal is determined in consideration of the rate of change of the signal _e1 to be operated, etc. First, the processor 20 reads the output signal from the comparator 11 according to the signal (program) stored in the program memory section 24, for example, at the rising edge of the sampling clock, as shown in FIG. Comparator 11, processor 20 and D/A converter 30
An analog-to-digital conversion loop constituted by converts the operated signal applied to the input terminal of the comparator 11 into a digital signal.

There are various methods for converting an analog signal into a digital signal, and the flowchart in FIG. 4 will explain the successive approximation method as an example. That is, first, the most significant bit of the A register formed in a part of the arithmetic control section 23 is set to "1" (). As a result, a digital amount corresponding to 50% of the total capacity of this A register is set in the A register. Next, the contents of the A register are output to the D/A converter 30 (). As a result, the D/A converter 30 converts the digital quantity corresponding to the 50% into an analog quantity, and this analog signal e _f is applied to the other input terminal of the comparator 11. Next, the output signal of the comparator 11 is read and the state of the signal is determined (). Here, if the state of the read signal is "0", that is, e ₁ < _ef , the "1" initially set in the most significant bit of the A register is reset to "0" ().
Also, the state of the read signal is “1”, that is, e ₁
> _ef , the "1" set in the most significant bit of the A register is left as is. Next, it is determined whether all digits of this A register have been completed (), and if not, the next digit, that is, the second bit for the most significant bit (1/2 of the most significant bit) is determined. (with weight) is set to "1" (). This means that a digital signal corresponding to 25% or 75% of the total capacity is set in the contents of the A register. Here, the procedure returns to step 1 again, and operations .about. are performed in the same manner as described above. In this operation, "1" is set to the third bit. In this way, the above operations are continued until all digits of the A register are completed, that is, until the least significant bit of the A register is set to "1" or "0". When all digits are completed, the procedure ends, and the content left in the A register is the value obtained by converting the input analog signal _e1 into a digital signal.

The digital signal converted in this way is
For example, it is written into a part of the data memory section 22 as _E1 . Next, the processor 20 processes the comparator 12
Read the output signal from comparator 12,
An analog-to-digital conversion loop composed of a processor 20 and a D/A converter 30 converts the calculation parameter e ₂ given as an analog signal to the input terminal of the comparator 12 into a digital signal using the same procedure as described above. However, this is written to a part of the data memory section 22 as _E2 , for example. Thereafter, in the same manner, the processor 20 converts the calculation parameters e ₃ , e ₄ , e ₅ given as analog signals to the input terminals of the comparators 13 , 14 , 15 into digital signals, and converts these into digital signals. They are written into a part of the memory section 22 as E ₃ , E ₄ , and E _{5 ,} respectively.

FIG. 5 is a conceptual diagram of data storage in the data memory section 22 written as described above.

Next, as shown in FIG. is used to perform desired calculations such as addition, subtraction, multiplication, division, square root calculation, etc. The type of calculation to be performed depends on the contents of the program stored in the program memory section 24 in advance. When the predetermined calculation is completed, the calculation result is outputted to the digital output terminal 60 via the output port 25 as shown in FIG. 3E, and the calculation result is displayed on the display 61. Further, if necessary, the signal is output to the D/A converter 30, where it is converted into an analog signal. Then, as shown in FIG. 3, by outputting an output command signal to the sample/hold switch 41, the D/A converter 30
The analog signal from is applied to the analog signal holding means 40 via the switch 41, and the output terminal 4
5 to 3G can be obtained continuously. Note that at this time, the analog signal from the D/A converter 30 is also applied to the other input terminal of each comparator 11 to 15, but the output signal of the comparator 11 to 15 is applied to the processor 2.
Since it is not read into 0, it is not related in any way.
Thereafter, the above operation is repeated in units of periods of the sampling clock signal, and the output terminal 6
0 or an updated calculation result can be obtained from the output terminal 45.

In the device of the present invention having such a configuration, the processor performs A/D conversion of the signal to be operated on, various calculation parameters given as analog signals, predetermined calculations, output to the D/A converter, and as needed. It is characterized by time-division control of the control signal (output command signal) output to the analog signal holding means, and an expensive A/D on the input side of the processor.
There is no need to provide a converter, and the overall configuration can be made simple and inexpensive. In addition, all the various calculation parameters are applied to the input side of the processor via comparators, and in order to receive the output signal from each comparator, one input end of processor 2 must be applied. Bye. Therefore, the limited number of input terminals of the processor can be effectively utilized. In other words, a large number of calculation parameters can be given to the processor, allowing it to perform complex calculations. Furthermore, since various calculation parameters can be set in an analog manner using variable resistors or the like, operability is good, and furthermore, calculation parameters are retained as they are even in the event of a power outage. Furthermore, since the calculation parameter setting circuit is configured with a plurality of variable resistors commonly connected to the DC power supply so as to form potentiometers, each analog signal indicating the calculation parameter obtained from each potentiometer can be can be set to the same level as the input analog signal within the range of the DC power supply size, and therefore each circuit for A/D conversion can be shared for each input signal. . Further, since the calculation parameter setting circuit can be configured as a common ground circuit using a common power source, this setting circuit can be easily configured.

FIGS. 6 and 7 are block diagrams showing other embodiments of the present invention.

The embodiment shown in FIG. 6 uses the operated signal e ₁ and various calculation parameter signals from the calculation parameter setting circuit
A multiplexer 10 that switches between e ₂ and _{e 5} is connected to a comparator 1.
The analog signal selected here is applied to one input terminal of the comparator 11, and the multiplexer 10 is controlled by the output control signal from the processor 20. It is. Further, on the input side of the processor 20, a terminal 16 is provided for applying, for example, an interrupt signal for appropriately changing the order of commands or calculation procedure from the calculation control section, or a digital signal for performing indexing by a program. be. The device configured in this manner has the advantage that only one comparator is required instead of the multiplexer 10, and is more effective when there are a large number of calculation parameters. Furthermore, by applying an interrupt signal to the terminal 16, for example, the calculation procedure, signal processing order, etc. within the processor 20 can be changed as appropriate.

In the embodiment shown in FIG. 7, a digital signal pulse width signal converter 30, which is a type of D/A converter, is provided on the output side of the processor 20 to convert the digital signal into a pulse width signal, and converts the digital signal into a pulse width signal, such as a photocoupler. The voltage is commonly applied to the other input terminals of the comparators 11 to 13 through an isolation means 31 and a smoothing circuit 32 such as the above. Furthermore, the outputs of the comparators 11 to 13 are sent to the processor 2 via isolation means 33 to 35.
0 and the output of the digital signal pulse width signal converter 30 to the isolation means 36.
The signal is supplied to the analog signal holding means 40 via the analog signal holding means 40. Further, the digital output from the processor 20 is outputted to the digital device 62 via the isolation means 37. In addition, here, two types of operand signals e ₁ ,
e ₂ as input, these are comparators 11 and 1
The signals e ₃ to e ₆ from the calculation parameter setting circuit 50 are applied to one input terminal of the multiplexer 1.
0 is selected and applied to one input terminal of the comparator 13. Note that the multiplexer 10 receives the output control signal from the processor 20,
It is provided via isolation means 38 and is controlled thereby. The apparatus of this embodiment has the advantage that the input side and the output side can be easily insulated. Further, it is possible to perform calculations in which the two types of operated signals e ₁ and e ₂ are related to each other. Note that in this embodiment, the operated signal
e ₁ and e ₂ may be applied to the multiplexer 10 and selected here, or the multiplexer 1
0 may be omitted and each signal may be applied to the processor 20 via a comparator. Further, the number of signals to be operated on may be two or more.

In the device according to the invention, one of the signals to be calculated is a measurement signal from a process, and
If the calculation parameter setting circuit 50 is configured so that any of the set value (target value), proportional band, integral time constant, and differential time constant can be set in an analog manner,
It is possible to have it function as a controller.

As described above, according to the present invention, it is possible to realize an arithmetic device with a simple configuration, in which various arithmetic parameters can be set in an analog manner, and in which each parameter value does not disappear due to a power outage or the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an arithmetic device using a conventional processor, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a time chart for explaining the operation of the device shown in FIG. FIG. 4 is a flowchart showing an example of conversion means when the processor converts an analog signal into a digital signal, FIG. 5 is a conceptual diagram of data storage written in the data memory section in the processor, and FIGS. FIG. 7 is a block diagram showing another embodiment of the present invention. 11-15... comparator, 20... processor,
21...Input port, 22...Data memory section,
23... Arithmetic control unit, 24... Program memory unit, 25... Output port, 30... D/A converter, 40... Analog signal holding means, 50... Arithmetic parameter setting circuit, 60... Digital signal Output terminal, 10... multiplexer.

Claims (1)

[Scope of Claims] 1 Consists of a processor, a digital-to-analog converter that converts digital signals output from the processor into analog signals, a DC power supply, and two or more variable resistors each commonly connected to the DC power supply. a calculation parameter setting circuit for setting two or more calculation parameters in an analog manner; a plurality of analog DC voltage signals indicating input analog signals to be calculated and calculation parameters obtained from each variable resistor of the calculation parameter setting circuit; a signal reading circuit including a comparator for inputting an output signal of an analog converter and reading these signals into the processor; A loop formed including a converter converts the input analog signal to be calculated and the plurality of analog DC voltage signals indicating the calculation parameters obtained from each potentiometer into digital signals, and converts each of these digital signals into digital signals. An arithmetic device characterized in that it repeatedly performs a predetermined arithmetic operation using a signal and outputs the result of the arithmetic operation via the digital-to-analog converter. 2. The arithmetic device according to claim 1, which uses a digital pulse width converter that converts a digital signal into a pulse width signal corresponding to the digital signal as the digital to analog converter. 3. A signal reading circuit is connected to an isolation means for inputting a pulse width signal from a digital pulse width converter, and a signal applied through this isolation means, an input analog signal, and/or an analog input from the calculation parameter setting circuit. 3. An arithmetic device according to claim 2, comprising: a comparator for comparing the signals; and isolation means for inputting the output signal of the comparator.