JPS6132700B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an error correction and error correction code generation circuit. In particular, in an information processing device using an error correction code, when a binary information code and this error correction code are given, errors in both are corrected by the given binary information code and this error correction code. and
The present invention also relates to an error correction and error correction code generation circuit that can configure a circuit that generates its own error correction code using the given binary information when only a binary information code is given. With rapid progress in integrated circuit technology in recent years, it has become possible to integrate this type of circuit on one substrate. However, the conventional circuit has a first operation means that performs a first exclusive OR operation based on an information code and an error correction code corresponding to the information code, an output means that outputs the first operation result to the outside, and an external A group of input terminals into which the exclusive OR result given from the above is input, a second exclusive OR operation is performed based on the exclusive OR result given from the outside and the first operation result, and the second operation result is The present invention is comprised of a second arithmetic means for generating a syndrome from , a decoding means for decoding the syndrome, and a correction circuit for correcting errors in the information code and the error correction code corresponding thereto based on the decoding result. , it has the following drawbacks: In other words, in such a conventional configuration, separate input terminals are used for all inputs of the error correction code and the exclusive OR result given from the outside, so the number of input terminals is large and the circuit lacks versatility. For,
It has the disadvantage of being unsuitable for integrated circuits. An object of the present invention is to eliminate such drawbacks and provide an error correction and error correction code generation circuit suitable for high integration. The circuit of the present invention is an information processing apparatus that processes information having an information code having a width of N×M (natural number) bytes and an error correction code corresponding thereto. a first calculation means for performing an exclusive OR operation; an output means for outputting the first calculation result to the outside; A sorting means for sorting and outputting the operation result and the second external operation result, and the same terminal inputs an error correction code that is one of the operation targets in the first operation means according to the N×M byte width and the exclusion A group of shared input terminals used for either input of the logical OR result, a second exclusive OR operation based on the first operation result and the first external operation result, and from this second operation result A second calculation means for generating a syndrome, a decoding means for decoding the syndrome and the second external calculation result, and a correction means for correcting an error in the N-byte wide information based on the decoding result are formed on the same substrate. Next, an embodiment of the present invention will be described in detail with reference to the drawings.The embodiment of the present invention shown in FIG. ', and the internal logic configurations of the first and second logic blocks 13 and 13' are the same, and their respective circuits and terminals correspond to 1 to 12 and 1' to 12'. Logic block 13
The explanation will focus on the second logic block 13', and the differences will also be explained regarding the second logic block 13'. That is, this embodiment of the present invention includes a code generator/decoder 1 as a first calculation means, an output terminal 6 as an output means, and input terminals 73 to 7 as a group of shared input terminals.
6, a byte width designator 2 as a sorting means, a comparator 3 as a second calculation means, a discriminator 4 as a decoding means, and a corrector 5 as a correction means. The logic block 13 can constitute a circuit that performs error correction of 2-, 4-, and 8-byte width information and generates an error correction code according to the value of the byte width control signal BW. In other words, the information code, the corresponding error correction code, and the exclusive OR result given from the outside are:
Input is possible from input terminal 10, input terminals 71 to 76, input terminals 73 to 76, and input terminals 81 to 84, respectively, but code generator/decoder 1 and byte width designator 2 can input data according to the value of byte width designation signal BW. The input terminals are electrically connected/disconnected to each input terminal to produce different effects on subsequent circuits. The first calculation results CS0 to CS5 are obtained by exclusive ORing using the information code input to the input terminal 10 and the error correction code input to the input terminals 71 to 76 according to the variation generation matrix shown in FIG. This is the result of the calculation. Byte width specification signal
The input terminal electrically disconnected by the BW is considered to give a logic "0" to the code generator/decoder 1. The exclusive OR result given from the outside is specified by the byte width specifier 2 as the first external operation result ES0 to ES.
5 and the second external calculation results ES6, ES7, and the respective values are input to input terminals 73, 75, 81.
.about.84 and the values of the signals at input terminals 74 and 76. However, the first external calculation result and the second external calculation result corresponding to the input terminal whose electrical connection is cut off become logic "0". Syndromes S0 to S7 are the first calculation result CS0
~CS5 and the first external calculation results ES0 to ES5 are generated according to the following equation.

[Table] (i) In the case of 2-byte wide information In this case, the purpose can be achieved with only one logical block 13. The code generator/decoder 1 has input terminals 10 and 2 applied to input terminals 71 to 76, respectively.
Byte information code and 1 bit error correction and 2
Accepting all 6-bit error correction codes for bit error detection, the first calculation results CS0 to CS
Outputs 5. The byte width specifier 2 does not accept all inputs, and in the end, error correction can be performed only with the first calculation results CS0 to CS5. (ii) In the case of 4-byte wide information In this case, logic block 13 and logic block 13' having the same configuration are used,
Connect both logic blocks as shown in FIG. In FIG. 1, the number at the tail end of the arrow pointing toward the input terminal 75 etc. indicates the number of the output terminal connected to this common terminal. Further, among the connections, thick lines indicate a collection of multiple signal lines. Now, of the 4-byte information, the first 2-byte information code B01 and the latter 2-byte information code B23 are given to input terminals 10 and 10', respectively, and a 1-bit error corresponding to these 4-byte information codes is detected. 7-bit error correction codes C0 to C6 (C0
is the smallest bit) is the input terminal 71-73, 71'
~74'. Input terminals 75-76,
75'-76', 81-84 and 81'-8
4' initially has no input signal. The code generator/decoder 1 has input terminals 10 and 71~
It accepts the 2-byte information code and the corresponding 4-bit error correction code given to 74, generates first operation results CS0 to CS5, supplies them to the comparator 3, and outputs them to the logic block 13 through the output terminal 6. It is also supplied to input terminals 75', 76' and 81' to 84' of ' as an externally applied calculation result. The byte width specifier 2 accepts the operation results supplied from the logic block 13' to input terminals 75, 76 and 81 to 84, and receives the results of the first external operation.
Output as ES1 to ES5 and second external calculation result ES6. Therefore, syndromes S0 to S6 are the first
From the formula and by tracing the generation process of the first calculation results CS0' to CS5', it can be seen that the following results are obtained. S0=C0B01(A), S1=C1B01(B)B23(F), S2=C2B01(C)B23(E), S3=C3B01(D)B23(C), S4=C4B01(E)B23(B) , S5=C5B01(F)B23(D), S6=C6B23(A) Here, B01(A) means that the first half 2-byte information code B01 is pattern A of the parity generation matrix shown in Figure 2. This shows that even parity is taken. Patterns A to F are related to the occurrence of syndromes S0 to S5, respectively.
It means the 16-bit pattern on the side of byte information code B01. Similarly, the syndromes S0' to S6' are determined as follows. S0′=C6B23(A), S1′=C4B01(E)B23(B), S2′=C3B01(D)B23(C), S3′=C5B01(F)B23(D), S4′=C2B01(C )B23(E), S5'=C1B01(B)23(F) S6'=C0B01(A) If the pattern of the parity generation matrix shown in Fig. 2 is compared with the formula of each syndrome, the syndromes S0 to S6 are Error correction code C0-C
6, the syndromes S0' to S6' are error correction codes C6, C4, C3, C5, C, respectively.
2, C1 and C0. (iii) In the case of 8-byte width information As shown in Figure 3, logic blocks 13, 1
3′, 13″ and additional circuit 14 on top of 13
Error correction can be performed by using a parity generation matrix as shown in FIG. Logic blocks 13-13 shown in FIG. 3 have the same structure as logic blocks 13 and 13' shown in FIG. . In Figure 4, the reference symbol
A' to F' are respectively patterns A in Figure 2.
~Has the same meaning as F. In this case, 64
Bit information codes B01-B67 and 8-bit error correction codes C0-C7 for 1-bit error correction and 2-bit error detection are divided into four equal parts and applied to four logic blocks 13-13. The exclusive OR results ES to ES given to each logic block 13 to 13 from the outside are obtained by the following equations.

[Table] By considering the parity generation matrix shown in Figure 4 and equation (2), each exclusive OR result ES ~ ES
has an 8-bit configuration, for example, the input terminals 73 to 76 and 81 to 8 of the logic block 13
given to 4. On the other hand, error correction codes are applied to input terminals 71 and 72. Although only error correction has been explained above, it is obvious that error correction codes can be generated when only information codes are input to the code generator/decoder. As described above, the present invention has a configuration in which the same terminal is used for either inputting an error correction code or inputting an exclusive OR result given from the outside, depending on the byte width of the information to be error corrected. By adopting this, the input terminals can be used without play, and the circuit configuration can be made versatile even with a small number of terminals and information of various byte widths, making it suitable for error correction and error correction for high integration. This has the effect of providing a code generation circuit.

[Brief explanation of the drawing]

1 and 3 show two structural examples of an embodiment of the present invention, and FIG. 2 and FIG. 4 are diagrams for explaining the structural examples of FIGS. 1 and 3, respectively. In the figure, 1, 1'... code generator/decoder,
2, 2'... byte width specifier, 3, 3'... comparator, 4, 4'... discriminator, 5, 5'... corrector,
6,6',61~66,61'~66',11,1
1', 12, 12'...Output terminal, 7, 7', 71
~76,71'~76',8,8',81~84,
81' to 84', 10, 10'...Input terminal, 1
3, 13', 13'', 13...Logic block, 1
4...Additional circuit, BW...Byte width control signal, B
01, B23, B45, B67...2-byte information code, B0' to B31'...1-bit information code, C
0 to C7...Error correction code, A' to F'...Pattern, S0 to S7...Syndrome, CI, CI'...
Corrected information code, CC, CC'...Corrected error correction code, CD, CD'...Corrected information, CS~CS,
CS0 to CS5, CS0' to CS5'...first operation result, ES to ES...exclusive OR result given from the outside, ES0 to ES5, ES0' to ES5'...first external operation result, ES6, ES6', ES7, ES7'
...Second external operation result, 0...Logic level 0.

Claims (1)

[Claims] 1. In an information processing device that processes information having an N×M (natural number) byte width information code and a corresponding error correction code, a first exclusive OR operation is performed based on N (natural number) byte width information. The first thing to do is
An arithmetic means, an output means for outputting the first arithmetic result to the outside, and a first external arithmetic result and a second external arithmetic result based on a predetermined bit position of the exclusive OR result given from the outside. a sorting means for distributing and outputting; the same terminal is either an input of an error correction code, which is one of the calculation targets in the first calculation means, or an input of the exclusive OR result, according to the N×M byte width; A group of shared input terminals used for
a second calculation means for performing a second exclusive OR operation based on the first operation result and the first external operation result and generating a syndrome from the second operation result;
A decoding means for decoding this syndrome and the second external operation result, and a correction means for correcting an error in the N-byte wide information based on the decoding result are formed on the same substrate. Error correction code generation circuit.