JPS6046741B2 - Error correction code and syndrome generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error correction code/syndrome generation circuit for an information processing device that operates based on binary logic.

Information processing devices are becoming larger and more sophisticated, and it has long been known that error correction codes are an effective method to meet the demands for high reliability in these devices. well known. In conventional devices, when generating error correction codes based on information codes and when generating syndrome codes based on these error correction codes and information codes, a large number of logic integrated circuits are interconnected. This is done using a different configuration. on the other hand,
With the rapid development of integrated circuit technology in recent years, logic circuits used to generate error correction codes and syndrome codes have come to be constructed by interconnecting one or several large-scale integrated circuits. However, conventional logic configurations are usually designed primarily to reduce the amount of hardware, so they lack versatility and have the disadvantage of increasing the number of input/output terminals. An object of the present invention is to provide an error correction code/syndrome generation circuit which can be used both for error correction code generation and syndrome generation.

Another object of the present invention is to provide a multifunctional error correction code/syndrome code generation circuit without increasing the number of input terminals. Another object of the present invention is to provide an error correction code/syndrome code generation circuit that satisfies the above two objects and can be constructed not only from a single logic block but also from a plurality of equal logic blocks. It is in.

The circuit of the present invention is an error correction code/syndrome generation circuit which inputs input data and either a parity code or an error correction code as a check code corresponding to the input data. an error correction code/syndrome generation means for generating a syndrome based on the input data and the error correction code; a check means for performing a parity check based on the input data and the parity code; A switching means is provided on the same semiconductor substrate for switching the error correction code/syndrome generation means to send the error correction code/syndrome generation means when a correction code is given, and to send the error correction code and syndrome generation means to the parity checking means when a parity code is given. Generates an error correction code from the error correction code/syndrome generation circuit when a parity code is given, and generates a syndrome from the error correction code/syndrome generation circuit when the error correction code is given to the switching means. It is characterized by being made to do.

Next, the present invention will be explained in detail with reference to the drawings.

Table 1 is a table showing an error correction code/syndrome generation matrix used in the first embodiment of the present invention, and the first arbitrary information code D of 4 bits shown in this table.

, Dl, D2, and D3 (hereinafter referred to as first data), 1-bit error correction codes CO, Cl, and C2 are added based on this table, and similarly, a 4-bit second arbitrary information code D 1-bit error correction codes C"0, C"1 and C"2 are added to "0, D"1, D"2 and D"3 (hereinafter referred to as second data), and these D"o
-1 from this table based on D″3 and C″o-C″2
A syndrome S″o-S″2 necessary for bit error correction is generated. FIG. 1 is a diagram showing a first embodiment of the present invention, which is composed of a logic block 4 constructed from a large-scale integrated circuit, and first data or second data is given as input data 11. In this case, the parity code of the first data or the second data is an error correction code as the check code 12. is given. Switching circuit 1
separately outputs the two given as check code 12. As a result, the error correction code 13 is given to the error correction code/syndrome generation circuit 2 together with the input data 11, and D is input as the input data 11. -Error correction code C if D3 is given. -C2 is generated, D″o-D″3 and an error correction code C″o-C″ is added as check code 12.
2, a syndrome is generated. In addition,
This generation circuit 2 is formed by combining multiple stages of exclusive ORs. D as input data 11.

-D3 is obtained and a parity code is given to the switching circuit 112, then the parity code 14 is supplied to the parity check circuit 3 together with the input data 11. This parity check circuit 3 outputs a parity check result 16.

When the first state designation signal is applied to the line 17 in the switching circuit, the first data D is applied together with the input data 11.

- If the parity code P of D3 is selected and the second state designation signal is given, the error correction code C given together with the data D″o-D″7 given as the input data 11
It is assumed that "o-C"2 is selected. Furthermore, when the first state designation signal 17 is given, the switching circuit 2
The parity code P given as the check code 12 given to It functions as a code generation circuit.A parity check is performed in the parity check circuit 3 using D.-D3 given as input data 11 and P which is a parity code 14, and the result is output as a parity check result 6. In this case,
As the check code 12, only one specific signal line is used to input the parity code P to the switching circuit 112.

On the other hand, when the second state designation signal is applied to line 17, check code 12 applied to switching circuit 112 is regarded as error correction code C″o-C″2.

Therefore, in this case, the first data D"o-D"3 and the error correction code C"o-C"2 are given to the error correction code/syndrome generation circuit 2, and this circuit generates the syndrome. Works as a circuit. Next, Table 2 shows the information error correction code/syndrome generation matrix used in the second embodiment.

This embodiment is an example showing a case where one unit (for example, one byte) of data is divided and provided to each board. First, the information code used in this embodiment is an 8-bit information code D.

1-bit third error correction codes CO, Cl, C2 and C3 are added to -D7 (hereinafter referred to as third data), and similarly arbitrary information codes D''.~D''7 (hereinafter referred to as fourth data) are added. 1-bit fourth error correction code C
"0, C"1, C"2 and C"3 are added, and this data and error correction codes D"o-D"7 and C"o-C"
Syndromes S″0, S″1, S″2 and S″3 corresponding to S″3 are formed. FIG. 2 is a diagram showing a second embodiment of the present invention. In FIG. 2, it is assumed that the first and second logic blocks 24 and 34 are made of completely identical large-scale integrated circuits. This embodiment shows a case where a 4-bit error correction code is provided as two sets of 2 bits to 8-bit data bits.

First, when the switching designation signal 47 indicates the second state, information codes D″0, D″1, D″2, and D″3 of the fourth data are given to the input data 41, and together with this, the error Correction codes C″o and C″1 are given as check codes 42.

As a result, the error correction code/syndrome generation circuit 22 outputs 2 bits in the intermediate process of forming the syndrome (a part of the 4-bit fourth data given as the input data 41 and 2 bits given as the check code 42). The exclusive OR result of the fourth data with a part of the error correction code) 48 is output. Also, the remaining information codes D″4, D″5, D″6 and D″7 of the fourth data are given as input data 51, and together with this, the remaining error correction codes C″2 and C″3 are checked. given as code 52,
An exclusive OR operation is performed by the error correction code/syndrome generation circuit 32, and the result of this operation and the 2-bit result 4 are
8 is further subjected to an exclusive OR operation, and S″o-S″3 is output as a syndrome 55.

In the above example, for convenience of explanation, the intermediate result was given from the first block 24 to the second block 34, but the intermediate result 58 may be given from the second block 34 to the first block 24 in the same way. . The Yanghe syndrome is the first
S″o-S″3 as syndrome 45 from the block of
is output. When a parity code is given as check code 42 or 52, input data D. -Error correction code C corresponding to D7. , Cl or C2, C3, or only some of them may be required. For example, in the case of the second embodiment in which one bit of parity is added to each of two sets of 4-bit data, only one signal line of the check code 42 or 52 is required. When the parity code for these data bits is given to the switching circuit 21 as a check code 42, it is given to the parity code check circuit 273 via a line 44, and a parity check is performed in the circuit 23 together with the data 41, and a parity check result 46 is given. At the same time, the input data 41 causes the error correction code/syndrome generation circuit 22 to output it as an intermediate result 48 for error correction code generation, and then to the error correction code/syndrome generation circuit 32 to output the error correction code 55. . The process of obtaining these output results is the same as in the first embodiment described above, and the same operations are performed in both the first block and the second block. Next, returning to this second embodiment, it will be explained in what states the error correction code/syndrome generation circuits 22 and 32 are used as error correction code generation circuits and as syndrome generation circuits.

First, when the switching designation signal 47 is in the first state, the input data 41 and 51 are the third data D.

- D as check codes 42 and 52, with D3 and D4 to D7 given; - Parity code P corresponding to D3 and D, ~D7. , Pl, the error correction codes 43 and 53 output from the switching circuits 21 and 31 are all in the ゜゜0゛ state, and the lines 44 and 54 are respectively the parity code P. and P1, and the intermediate result codes 48 and 58, which are the outputs of the error correction code/syndrome generation circuits 22 and 32, are given as inputs to the error correction code/syndrome generation circuits 32 and 22 of different logic blocks, respectively. data 45
and 55 are error correction codes C, respectively. , Cl and C2
, C3, and the parity check circuit 2
3 and 33, respectively, a parity code PO which is a part 41 (DO-D3) of the input data and a check code 42, and a parity code P1 which is the other part 51 (D4 to D7) of the input data and a check code 52. parity is taken to obtain a first parity check result 46 and a second parity check result 56. Next, the switching designation signal 47
In this case, part of the fourth data (D"o-D"3) and other parts (D"4 to .D"7) are given as input data 41 and 51, respectively, and When these error correction codes C″0, C″1 and C″2, C″3 are given as the check codes 42 and 52, respectively, the error correction code 4 which is the output of the switching circuits 21 and 31
3 and 53 are error correction codes C″0, C″1 and . C″2 and C″3, and intermediate result codes 48 are generated from the error correction code/syndrome generation circuits 22 and 32, respectively.
and 58 are outputted and given to different error correction code/syndrome code generation circuits, thereby outputting syndrome codes S'' to outputs 45 and 55, respectively.

, S''1 and S''2, S''3.As explained above in the first and second embodiments of the present invention, the present invention uses the same error correction code and syndrome code generation circuit. When the circuit is constructed, the error correction code input terminal used for syndrome code generation can be used as a terminal for inputting the parity of the information code when the error correction code is generated. This has the advantage that tests can be performed simultaneously.

Furthermore, as explained in the second embodiment of the present invention, the present invention has the advantage that a logical configuration meeting the above conditions can be configured not only by a single logical block but also by a plurality of equal logical blocks. . Therefore, the present invention is very effective when applied to large-scale integrated circuits that have been significantly developed in recent years, where the number of input/output pins is limited compared to the number of logic circuits.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a first embodiment of the present invention, and FIG. 2 is a diagram showing a second embodiment of the present invention.

Claims (1)

[Claims] 1. In an error correction code/syndrome generation circuit which inputs either a parity code or an error correction code as input data and a check code corresponding to this data,
error correction code/syndrome generating means for generating an error correction code based only on the input data and generating a syndrome based on the input data and the error correction code; and a parity check based on the input data and the parity code. and a switching means that switches to transmit the error correction code/syndrome generating means when an error correction code is given as the check code and to the parity check means when a parity code is given. provided on a semiconductor substrate, when the parity code is given to the switching means, an error correction code is generated from the error correction code/syndrome generation circuit; and when the error correction code is given to the switching means, the error correction code is generated. An error correction code/syndrome generation circuit characterized in that a syndrome is generated from the correction code/syndrome generation circuit.